debuggers.hg

view xen/arch/ia64/linux-xen/sn/kernel/sn2_smp.c @ 0:7d21f7218375

Exact replica of unstable on 051908 + README-this
author Mukesh Rathor
date Mon May 19 15:34:57 2008 -0700 (2008-05-19)
parents
children 62cf917432fa
line source
1 /*
2 * SN2 Platform specific SMP Support
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000-2006 Silicon Graphics, Inc. All rights reserved.
9 */
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/spinlock.h>
14 #include <linux/threads.h>
15 #include <linux/sched.h>
16 #include <linux/smp.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/mmzone.h>
20 #include <linux/module.h>
21 #include <linux/bitops.h>
22 #include <linux/nodemask.h>
23 #include <linux/proc_fs.h>
24 #include <linux/seq_file.h>
26 #include <asm/processor.h>
27 #include <asm/irq.h>
28 #include <asm/sal.h>
29 #include <asm/system.h>
30 #include <asm/delay.h>
31 #include <asm/io.h>
32 #include <asm/smp.h>
33 #include <asm/tlb.h>
34 #include <asm/numa.h>
35 #include <asm/hw_irq.h>
36 #include <asm/current.h>
37 #ifdef XEN
38 #include <asm/sn/arch.h>
39 #endif
40 #include <asm/sn/sn_cpuid.h>
41 #include <asm/sn/sn_sal.h>
42 #include <asm/sn/addrs.h>
43 #include <asm/sn/shub_mmr.h>
44 #include <asm/sn/nodepda.h>
45 #include <asm/sn/rw_mmr.h>
47 DEFINE_PER_CPU(struct ptc_stats, ptcstats);
48 DECLARE_PER_CPU(struct ptc_stats, ptcstats);
50 static __cacheline_aligned DEFINE_SPINLOCK(sn2_global_ptc_lock);
52 extern unsigned long
53 sn2_ptc_deadlock_recovery_core(volatile unsigned long *, unsigned long,
54 volatile unsigned long *, unsigned long,
55 volatile unsigned long *, unsigned long);
56 void
57 sn2_ptc_deadlock_recovery(short *, short, short, int,
58 volatile unsigned long *, unsigned long,
59 volatile unsigned long *, unsigned long);
61 /*
62 * Note: some is the following is captured here to make degugging easier
63 * (the macros make more sense if you see the debug patch - not posted)
64 */
65 #define sn2_ptctest 0
66 #define local_node_uses_ptc_ga(sh1) ((sh1) ? 1 : 0)
67 #define max_active_pio(sh1) ((sh1) ? 32 : 7)
68 #define reset_max_active_on_deadlock() 1
69 #ifndef XEN
70 #define PTC_LOCK(sh1) ((sh1) ? &sn2_global_ptc_lock : &sn_nodepda->ptc_lock)
71 #else
72 #define PTC_LOCK(sh1) &sn2_global_ptc_lock
73 #endif
75 struct ptc_stats {
76 unsigned long ptc_l;
77 unsigned long change_rid;
78 unsigned long shub_ptc_flushes;
79 unsigned long nodes_flushed;
80 unsigned long deadlocks;
81 unsigned long deadlocks2;
82 unsigned long lock_itc_clocks;
83 unsigned long shub_itc_clocks;
84 unsigned long shub_itc_clocks_max;
85 unsigned long shub_ptc_flushes_not_my_mm;
86 };
88 #define sn2_ptctest 0
90 static inline unsigned long wait_piowc(void)
91 {
92 volatile unsigned long *piows;
93 unsigned long zeroval, ws;
95 piows = pda->pio_write_status_addr;
96 zeroval = pda->pio_write_status_val;
97 do {
98 cpu_relax();
99 } while (((ws = *piows) & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != zeroval);
100 return (ws & SH_PIO_WRITE_STATUS_WRITE_DEADLOCK_MASK) != 0;
101 }
103 #ifndef XEN /* No idea if Xen will ever support this */
104 /**
105 * sn_migrate - SN-specific task migration actions
106 * @task: Task being migrated to new CPU
107 *
108 * SN2 PIO writes from separate CPUs are not guaranteed to arrive in order.
109 * Context switching user threads which have memory-mapped MMIO may cause
110 * PIOs to issue from seperate CPUs, thus the PIO writes must be drained
111 * from the previous CPU's Shub before execution resumes on the new CPU.
112 */
113 void sn_migrate(struct task_struct *task)
114 {
115 pda_t *last_pda = pdacpu(task_thread_info(task)->last_cpu);
116 volatile unsigned long *adr = last_pda->pio_write_status_addr;
117 unsigned long val = last_pda->pio_write_status_val;
119 /* Drain PIO writes from old CPU's Shub */
120 while (unlikely((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK)
121 != val))
122 cpu_relax();
123 }
125 void sn_tlb_migrate_finish(struct mm_struct *mm)
126 {
127 /* flush_tlb_mm is inefficient if more than 1 users of mm */
128 #ifndef XEN
129 if (mm == current->mm && mm && atomic_read(&mm->mm_users) == 1)
130 #else
131 if (mm == &current->arch.mm && mm && atomic_read(&mm->mm_users) == 1)
132 #endif
133 flush_tlb_mm(mm);
134 }
135 #endif
137 /**
138 * sn2_global_tlb_purge - globally purge translation cache of virtual address range
139 * @mm: mm_struct containing virtual address range
140 * @start: start of virtual address range
141 * @end: end of virtual address range
142 * @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc))
143 *
144 * Purges the translation caches of all processors of the given virtual address
145 * range.
146 *
147 * Note:
148 * - cpu_vm_mask is a bit mask that indicates which cpus have loaded the context.
149 * - cpu_vm_mask is converted into a nodemask of the nodes containing the
150 * cpus in cpu_vm_mask.
151 * - if only one bit is set in cpu_vm_mask & it is the current cpu & the
152 * process is purging its own virtual address range, then only the
153 * local TLB needs to be flushed. This flushing can be done using
154 * ptc.l. This is the common case & avoids the global spinlock.
155 * - if multiple cpus have loaded the context, then flushing has to be
156 * done with ptc.g/MMRs under protection of the global ptc_lock.
157 */
159 #ifdef XEN /* Xen is soooooooo stupid! */
160 // static cpumask_t mask_all = CPU_MASK_ALL;
161 #endif
163 #ifdef XEN
164 static DEFINE_SPINLOCK(sn2_ptcg_lock);
166 struct sn_flush_struct {
167 unsigned long start;
168 unsigned long end;
169 unsigned long nbits;
170 };
172 static void sn_flush_ptcga_cpu(void *ptr)
173 {
174 struct sn_flush_struct *sn_flush = ptr;
175 unsigned long start, end, nbits;
177 start = sn_flush->start;
178 end = sn_flush->end;
179 nbits = sn_flush->nbits;
181 /*
182 * Contention me harder!!!
183 */
184 /* HW requires global serialization of ptc.ga. */
185 spin_lock(&sn2_ptcg_lock);
186 {
187 do {
188 /*
189 * Flush ALAT entries also.
190 */
191 ia64_ptcga(start, (nbits<<2));
192 ia64_srlz_i();
193 start += (1UL << nbits);
194 } while (start < end);
195 }
196 spin_unlock(&sn2_ptcg_lock);
197 }
199 void
200 sn2_global_tlb_purge(unsigned long start,
201 unsigned long end, unsigned long nbits)
202 {
203 nodemask_t nodes_flushed;
204 cpumask_t selected_cpus;
205 int cpu, cnode, i;
206 static DEFINE_SPINLOCK(sn2_ptcg_lock2);
208 nodes_clear(nodes_flushed);
209 cpus_clear(selected_cpus);
211 spin_lock(&sn2_ptcg_lock2);
212 node_set(cpu_to_node(smp_processor_id()), nodes_flushed);
213 i = 0;
214 for_each_cpu(cpu) {
215 cnode = cpu_to_node(cpu);
216 if (!node_isset(cnode, nodes_flushed)) {
217 cpu_set(cpu, selected_cpus);
218 i++;
219 }
220 node_set(cnode, nodes_flushed);
221 }
223 /* HW requires global serialization of ptc.ga. */
224 spin_lock(&sn2_ptcg_lock);
225 {
226 do {
227 /*
228 * Flush ALAT entries also.
229 */
230 ia64_ptcga(start, (nbits<<2));
231 ia64_srlz_i();
232 start += (1UL << nbits);
233 } while (start < end);
234 }
235 spin_unlock(&sn2_ptcg_lock);
237 if (i) {
238 struct sn_flush_struct flush_data;
239 flush_data.start = start;
240 flush_data.end = end;
241 flush_data.nbits = nbits;
242 on_selected_cpus(selected_cpus, sn_flush_ptcga_cpu,
243 &flush_data, 1, 1);
244 }
245 spin_unlock(&sn2_ptcg_lock2);
246 }
247 #else
248 void
249 sn2_global_tlb_purge(struct mm_struct *mm, unsigned long start,
250 unsigned long end, unsigned long nbits)
251 {
252 int i, ibegin, shub1, cnode, mynasid, cpu, lcpu = 0, nasid;
253 int mymm = (mm == current->active_mm && mm == current->mm);
254 int use_cpu_ptcga;
255 volatile unsigned long *ptc0, *ptc1;
256 unsigned long itc, itc2, flags, data0 = 0, data1 = 0, rr_value, old_rr = 0;
257 short nasids[MAX_NUMNODES], nix;
258 nodemask_t nodes_flushed;
259 int active, max_active, deadlock;
261 nodes_clear(nodes_flushed);
262 i = 0;
264 #ifndef XEN /* One day Xen will grow up! */
265 for_each_cpu_mask(cpu, mm->cpu_vm_mask) {
266 cnode = cpu_to_node(cpu);
267 node_set(cnode, nodes_flushed);
268 lcpu = cpu;
269 i++;
270 }
271 #else
272 for_each_cpu(cpu) {
273 cnode = cpu_to_node(cpu);
274 node_set(cnode, nodes_flushed);
275 lcpu = cpu;
276 i++;
277 }
278 #endif
280 if (i == 0)
281 return;
283 preempt_disable();
285 #ifndef XEN
286 if (likely(i == 1 && lcpu == smp_processor_id() && mymm)) {
287 do {
288 ia64_ptcl(start, nbits << 2);
289 start += (1UL << nbits);
290 } while (start < end);
291 ia64_srlz_i();
292 __get_cpu_var(ptcstats).ptc_l++;
293 preempt_enable();
294 return;
295 }
297 if (atomic_read(&mm->mm_users) == 1 && mymm) {
298 flush_tlb_mm(mm);
299 __get_cpu_var(ptcstats).change_rid++;
300 preempt_enable();
301 return;
302 }
303 #endif
305 itc = ia64_get_itc();
306 nix = 0;
307 for_each_node_mask(cnode, nodes_flushed)
308 nasids[nix++] = cnodeid_to_nasid(cnode);
310 #ifndef XEN
311 rr_value = (mm->context << 3) | REGION_NUMBER(start);
312 #else
313 rr_value = REGION_NUMBER(start);
314 #endif
316 shub1 = is_shub1();
317 if (shub1) {
318 data0 = (1UL << SH1_PTC_0_A_SHFT) |
319 (nbits << SH1_PTC_0_PS_SHFT) |
320 (rr_value << SH1_PTC_0_RID_SHFT) |
321 (1UL << SH1_PTC_0_START_SHFT);
322 #ifndef XEN
323 ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_0);
324 ptc1 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_1);
325 #else
326 ptc0 = (unsigned long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_0);
327 ptc1 = (unsigned long *)GLOBAL_MMR_PHYS_ADDR(0, SH1_PTC_1);
328 #endif
329 } else {
330 data0 = (1UL << SH2_PTC_A_SHFT) |
331 (nbits << SH2_PTC_PS_SHFT) |
332 (1UL << SH2_PTC_START_SHFT);
333 #ifndef XEN
334 ptc0 = (long *)GLOBAL_MMR_PHYS_ADDR(0, SH2_PTC +
335 #else
336 ptc0 = (unsigned long *)GLOBAL_MMR_PHYS_ADDR(0, SH2_PTC +
337 #endif
338 (rr_value << SH2_PTC_RID_SHFT));
339 ptc1 = NULL;
340 }
343 mynasid = get_nasid();
344 use_cpu_ptcga = local_node_uses_ptc_ga(shub1);
345 max_active = max_active_pio(shub1);
347 itc = ia64_get_itc();
348 spin_lock_irqsave(PTC_LOCK(shub1), flags);
349 itc2 = ia64_get_itc();
351 __get_cpu_var(ptcstats).lock_itc_clocks += itc2 - itc;
352 __get_cpu_var(ptcstats).shub_ptc_flushes++;
353 __get_cpu_var(ptcstats).nodes_flushed += nix;
354 if (!mymm)
355 __get_cpu_var(ptcstats).shub_ptc_flushes_not_my_mm++;
357 if (use_cpu_ptcga && !mymm) {
358 old_rr = ia64_get_rr(start);
359 ia64_set_rr(start, (old_rr & 0xff) | (rr_value << 8));
360 ia64_srlz_d();
361 }
363 wait_piowc();
364 do {
365 if (shub1)
366 data1 = start | (1UL << SH1_PTC_1_START_SHFT);
367 else
368 data0 = (data0 & ~SH2_PTC_ADDR_MASK) | (start & SH2_PTC_ADDR_MASK);
369 deadlock = 0;
370 active = 0;
371 for (ibegin = 0, i = 0; i < nix; i++) {
372 nasid = nasids[i];
373 if (use_cpu_ptcga && unlikely(nasid == mynasid)) {
374 ia64_ptcga(start, nbits << 2);
375 ia64_srlz_i();
376 } else {
377 ptc0 = CHANGE_NASID(nasid, ptc0);
378 if (ptc1)
379 ptc1 = CHANGE_NASID(nasid, ptc1);
380 pio_atomic_phys_write_mmrs(ptc0, data0, ptc1, data1);
381 active++;
382 }
383 if (active >= max_active || i == (nix - 1)) {
384 if ((deadlock = wait_piowc())) {
385 sn2_ptc_deadlock_recovery(nasids, ibegin, i, mynasid, ptc0, data0, ptc1, data1);
386 if (reset_max_active_on_deadlock())
387 max_active = 1;
388 }
389 active = 0;
390 ibegin = i + 1;
391 }
392 }
393 start += (1UL << nbits);
394 } while (start < end);
396 itc2 = ia64_get_itc() - itc2;
397 __get_cpu_var(ptcstats).shub_itc_clocks += itc2;
398 if (itc2 > __get_cpu_var(ptcstats).shub_itc_clocks_max)
399 __get_cpu_var(ptcstats).shub_itc_clocks_max = itc2;
401 if (old_rr) {
402 ia64_set_rr(start, old_rr);
403 ia64_srlz_d();
404 }
406 spin_unlock_irqrestore(PTC_LOCK(shub1), flags);
408 preempt_enable();
409 }
410 #endif
412 /*
413 * sn2_ptc_deadlock_recovery
414 *
415 * Recover from PTC deadlocks conditions. Recovery requires stepping thru each
416 * TLB flush transaction. The recovery sequence is somewhat tricky & is
417 * coded in assembly language.
418 */
420 void
421 sn2_ptc_deadlock_recovery(short *nasids, short ib, short ie, int mynasid,
422 volatile unsigned long *ptc0, unsigned long data0,
423 volatile unsigned long *ptc1, unsigned long data1)
424 {
425 short nasid, i;
426 unsigned long *piows, zeroval, n;
428 __get_cpu_var(ptcstats).deadlocks++;
430 piows = (unsigned long *) pda->pio_write_status_addr;
431 zeroval = pda->pio_write_status_val;
434 for (i=ib; i <= ie; i++) {
435 nasid = nasids[i];
436 if (local_node_uses_ptc_ga(is_shub1()) && nasid == mynasid)
437 continue;
438 ptc0 = CHANGE_NASID(nasid, ptc0);
439 if (ptc1)
440 ptc1 = CHANGE_NASID(nasid, ptc1);
442 n = sn2_ptc_deadlock_recovery_core(ptc0, data0, ptc1, data1, piows, zeroval);
443 __get_cpu_var(ptcstats).deadlocks2 += n;
444 }
446 }
448 /**
449 * sn_send_IPI_phys - send an IPI to a Nasid and slice
450 * @nasid: nasid to receive the interrupt (may be outside partition)
451 * @physid: physical cpuid to receive the interrupt.
452 * @vector: command to send
453 * @delivery_mode: delivery mechanism
454 *
455 * Sends an IPI (interprocessor interrupt) to the processor specified by
456 * @physid
457 *
458 * @delivery_mode can be one of the following
459 *
460 * %IA64_IPI_DM_INT - pend an interrupt
461 * %IA64_IPI_DM_PMI - pend a PMI
462 * %IA64_IPI_DM_NMI - pend an NMI
463 * %IA64_IPI_DM_INIT - pend an INIT interrupt
464 */
465 void sn_send_IPI_phys(int nasid, long physid, int vector, int delivery_mode)
466 {
467 long val;
468 unsigned long flags = 0;
469 volatile long *p;
471 p = (long *)GLOBAL_MMR_PHYS_ADDR(nasid, SH_IPI_INT);
472 val = (1UL << SH_IPI_INT_SEND_SHFT) |
473 (physid << SH_IPI_INT_PID_SHFT) |
474 ((long)delivery_mode << SH_IPI_INT_TYPE_SHFT) |
475 ((long)vector << SH_IPI_INT_IDX_SHFT) |
476 (0x000feeUL << SH_IPI_INT_BASE_SHFT);
478 mb();
479 if (enable_shub_wars_1_1()) {
480 spin_lock_irqsave(&sn2_global_ptc_lock, flags);
481 }
482 pio_phys_write_mmr(p, val);
483 if (enable_shub_wars_1_1()) {
484 wait_piowc();
485 spin_unlock_irqrestore(&sn2_global_ptc_lock, flags);
486 }
488 }
490 EXPORT_SYMBOL(sn_send_IPI_phys);
492 /**
493 * sn2_send_IPI - send an IPI to a processor
494 * @cpuid: target of the IPI
495 * @vector: command to send
496 * @delivery_mode: delivery mechanism
497 * @redirect: redirect the IPI?
498 *
499 * Sends an IPI (InterProcessor Interrupt) to the processor specified by
500 * @cpuid. @vector specifies the command to send, while @delivery_mode can
501 * be one of the following
502 *
503 * %IA64_IPI_DM_INT - pend an interrupt
504 * %IA64_IPI_DM_PMI - pend a PMI
505 * %IA64_IPI_DM_NMI - pend an NMI
506 * %IA64_IPI_DM_INIT - pend an INIT interrupt
507 */
508 void sn2_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
509 {
510 long physid;
511 int nasid;
513 physid = cpu_physical_id(cpuid);
514 #ifdef XEN
515 if (!sn_nodepda) {
516 ia64_sn_get_sapic_info(physid, &nasid, NULL, NULL);
517 } else
518 #endif
519 nasid = cpuid_to_nasid(cpuid);
521 /* the following is used only when starting cpus at boot time */
522 if (unlikely(nasid == -1))
523 ia64_sn_get_sapic_info(physid, &nasid, NULL, NULL);
525 sn_send_IPI_phys(nasid, physid, vector, delivery_mode);
526 }
528 #ifdef CONFIG_PROC_FS
530 #define PTC_BASENAME "sgi_sn/ptc_statistics"
532 static void *sn2_ptc_seq_start(struct seq_file *file, loff_t * offset)
533 {
534 if (*offset < NR_CPUS)
535 return offset;
536 return NULL;
537 }
539 static void *sn2_ptc_seq_next(struct seq_file *file, void *data, loff_t * offset)
540 {
541 (*offset)++;
542 if (*offset < NR_CPUS)
543 return offset;
544 return NULL;
545 }
547 static void sn2_ptc_seq_stop(struct seq_file *file, void *data)
548 {
549 }
551 static int sn2_ptc_seq_show(struct seq_file *file, void *data)
552 {
553 struct ptc_stats *stat;
554 int cpu;
556 cpu = *(loff_t *) data;
558 if (!cpu) {
559 seq_printf(file,
560 "# cpu ptc_l newrid ptc_flushes nodes_flushed deadlocks lock_nsec shub_nsec shub_nsec_max not_my_mm deadlock2\n");
561 seq_printf(file, "# ptctest %d\n", sn2_ptctest);
562 }
564 if (cpu < NR_CPUS && cpu_online(cpu)) {
565 stat = &per_cpu(ptcstats, cpu);
566 seq_printf(file, "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n", cpu, stat->ptc_l,
567 stat->change_rid, stat->shub_ptc_flushes, stat->nodes_flushed,
568 stat->deadlocks,
569 1000 * stat->lock_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec,
570 1000 * stat->shub_itc_clocks / per_cpu(cpu_info, cpu).cyc_per_usec,
571 1000 * stat->shub_itc_clocks_max / per_cpu(cpu_info, cpu).cyc_per_usec,
572 stat->shub_ptc_flushes_not_my_mm,
573 stat->deadlocks2);
574 }
575 return 0;
576 }
578 static struct seq_operations sn2_ptc_seq_ops = {
579 .start = sn2_ptc_seq_start,
580 .next = sn2_ptc_seq_next,
581 .stop = sn2_ptc_seq_stop,
582 .show = sn2_ptc_seq_show
583 };
585 static int sn2_ptc_proc_open(struct inode *inode, struct file *file)
586 {
587 return seq_open(file, &sn2_ptc_seq_ops);
588 }
590 static struct file_operations proc_sn2_ptc_operations = {
591 .open = sn2_ptc_proc_open,
592 .read = seq_read,
593 .llseek = seq_lseek,
594 .release = seq_release,
595 };
597 static struct proc_dir_entry *proc_sn2_ptc;
599 static int __init sn2_ptc_init(void)
600 {
601 if (!ia64_platform_is("sn2"))
602 return 0;
604 if (!(proc_sn2_ptc = create_proc_entry(PTC_BASENAME, 0444, NULL))) {
605 printk(KERN_ERR "unable to create %s proc entry", PTC_BASENAME);
606 return -EINVAL;
607 }
608 proc_sn2_ptc->proc_fops = &proc_sn2_ptc_operations;
609 spin_lock_init(&sn2_global_ptc_lock);
610 return 0;
611 }
613 static void __exit sn2_ptc_exit(void)
614 {
615 remove_proc_entry(PTC_BASENAME, NULL);
616 }
618 module_init(sn2_ptc_init);
619 module_exit(sn2_ptc_exit);
620 #endif /* CONFIG_PROC_FS */