debuggers.hg

view xen/arch/x86/cpu/mcheck/p6.c @ 0:7d21f7218375

Exact replica of unstable on 051908 + README-this
author Mukesh Rathor
date Mon May 19 15:34:57 2008 -0700 (2008-05-19)
parents
children 415a69b41397
line source
1 /*
2 * P6 specific Machine Check Exception Reporting
3 * (C) Copyright 2002 Alan Cox <alan@redhat.com>
4 */
6 #include <xen/init.h>
7 #include <xen/types.h>
8 #include <xen/kernel.h>
9 #include <xen/smp.h>
11 #include <asm/processor.h>
12 #include <asm/system.h>
13 #include <asm/msr.h>
15 #include "mce.h"
17 /* Machine Check Handler For PII/PIII */
18 static fastcall void intel_machine_check(struct cpu_user_regs * regs, long error_code)
19 {
20 int recover=1;
21 u32 alow, ahigh, high, low;
22 u32 mcgstl, mcgsth;
23 int i;
25 rdmsr (MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
26 if (mcgstl & (1<<0)) /* Recoverable ? */
27 recover=0;
29 printk (KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
30 smp_processor_id(), mcgsth, mcgstl);
32 for (i=0; i<nr_mce_banks; i++) {
33 rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high);
34 if (high & (1<<31)) {
35 if (high & (1<<29))
36 recover |= 1;
37 if (high & (1<<25))
38 recover |= 2;
39 printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
40 high &= ~(1<<31);
41 if (high & (1<<27)) {
42 rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
43 printk ("[%08x%08x]", ahigh, alow);
44 }
45 if (high & (1<<26)) {
46 rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
47 printk (" at %08x%08x", ahigh, alow);
48 }
49 printk ("\n");
50 }
51 }
53 if (recover & 2)
54 panic ("CPU context corrupt");
55 if (recover & 1)
56 panic ("Unable to continue");
58 printk (KERN_EMERG "Attempting to continue.\n");
59 /*
60 * Do not clear the MSR_IA32_MCi_STATUS if the error is not
61 * recoverable/continuable.This will allow BIOS to look at the MSRs
62 * for errors if the OS could not log the error.
63 */
64 for (i=0; i<nr_mce_banks; i++) {
65 unsigned int msr;
66 msr = MSR_IA32_MC0_STATUS+i*4;
67 rdmsr (msr,low, high);
68 if (high & (1<<31)) {
69 /* Clear it */
70 wrmsr (msr, 0UL, 0UL);
71 /* Serialize */
72 wmb();
73 add_taint(TAINT_MACHINE_CHECK);
74 }
75 }
76 mcgstl &= ~(1<<2);
77 wrmsr (MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
78 }
80 /* Set up machine check reporting for processors with Intel style MCE */
81 void intel_p6_mcheck_init(struct cpuinfo_x86 *c)
82 {
83 u32 l, h;
84 int i;
86 /* Check for MCE support */
87 if (!cpu_has(c, X86_FEATURE_MCE))
88 return;
90 /* Check for PPro style MCA */
91 if (!cpu_has(c, X86_FEATURE_MCA))
92 return;
94 /* Ok machine check is available */
95 machine_check_vector = intel_machine_check;
96 wmb();
98 printk (KERN_INFO "Intel machine check architecture supported.\n");
99 rdmsr (MSR_IA32_MCG_CAP, l, h);
100 if (l & (1<<8)) /* Control register present ? */
101 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
102 nr_mce_banks = l & 0xff;
104 /*
105 * Following the example in IA-32 SDM Vol 3:
106 * - MC0_CTL should not be written
107 * - Status registers on all banks should be cleared on reset
108 */
109 for (i=1; i<nr_mce_banks; i++)
110 wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
112 for (i=0; i<nr_mce_banks; i++)
113 wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
115 set_in_cr4 (X86_CR4_MCE);
116 printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
117 smp_processor_id());
118 }