debuggers.hg

view xen/drivers/passthrough/vtd/iommu.h @ 0:7d21f7218375

Exact replica of unstable on 051908 + README-this
author Mukesh Rathor
date Mon May 19 15:34:57 2008 -0700 (2008-05-19)
parents
children 5c0bf00e371d
line source
1 /*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
17 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
18 */
20 #ifndef _INTEL_IOMMU_H_
21 #define _INTEL_IOMMU_H_
23 #include <xen/types.h>
25 /*
26 * Intel IOMMU register specification per version 1.0 public spec.
27 */
29 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
30 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
31 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
32 #define DMAR_GCMD_REG 0x18 /* Global command register */
33 #define DMAR_GSTS_REG 0x1c /* Global status register */
34 #define DMAR_RTADDR_REG 0x20 /* Root entry table */
35 #define DMAR_CCMD_REG 0x28 /* Context command reg */
36 #define DMAR_FSTS_REG 0x34 /* Fault Status register */
37 #define DMAR_FECTL_REG 0x38 /* Fault control register */
38 #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
39 #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
40 #define DMAR_FEUADDR_REG 0x44 /* Upper address register */
41 #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
42 #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
43 #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
44 #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
45 #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
46 #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
47 #define DMAR_IQH_REG 0x80 /* invalidation queue head */
48 #define DMAR_IQT_REG 0x88 /* invalidation queue tail */
49 #define DMAR_IQA_REG 0x90 /* invalidation queue addr */
50 #define DMAR_IRTA_REG 0xB8 /* intr remap */
52 #define OFFSET_STRIDE (9)
53 #define dmar_readl(dmar, reg) readl(dmar + reg)
54 #define dmar_writel(dmar, reg, val) writel(val, dmar + reg)
55 #define dmar_readq(dmar, reg) ({ \
56 u32 lo, hi; \
57 lo = dmar_readl(dmar, reg); \
58 hi = dmar_readl(dmar, reg + 4); \
59 (((u64) hi) << 32) + lo; })
60 #define dmar_writeq(dmar, reg, val) do {\
61 dmar_writel(dmar, reg, (u32)val); \
62 dmar_writel(dmar, reg + 4, (u32)((u64) val >> 32)); \
63 } while (0)
65 #define VER_MAJOR(v) (((v) & 0xf0) >> 4)
66 #define VER_MINOR(v) ((v) & 0x0f)
68 /*
69 * Decoding Capability Register
70 */
71 #define cap_read_drain(c) (((c) >> 55) & 1)
72 #define cap_write_drain(c) (((c) >> 54) & 1)
73 #define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
74 #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
75 #define cap_pgsel_inv(c) (((c) >> 39) & 1)
77 #define cap_super_page_val(c) (((c) >> 34) & 0xf)
78 #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
79 * OFFSET_STRIDE) + 21)
81 #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
83 #define cap_isoch(c) (((c) >> 23) & 1)
84 #define cap_qos(c) (((c) >> 22) & 1)
85 #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
86 #define cap_sagaw(c) (((c) >> 8) & 0x1f)
87 #define cap_caching_mode(c) (((c) >> 7) & 1)
88 #define cap_phmr(c) (((c) >> 6) & 1)
89 #define cap_plmr(c) (((c) >> 5) & 1)
90 #define cap_rwbf(c) (((c) >> 4) & 1)
91 #define cap_afl(c) (((c) >> 3) & 1)
92 #define cap_ndoms(c) (1 << (4 + 2 * ((c) & 0x7)))
94 /*
95 * Extended Capability Register
96 */
98 #define ecap_niotlb_iunits(e) ((((e) >> 24) & 0xff) + 1)
99 #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
100 #define ecap_coherent(e) ((e >> 0) & 0x1)
101 #define ecap_queued_inval(e) ((e >> 1) & 0x1)
102 #define ecap_dev_iotlb(e) ((e >> 2) & 0x1)
103 #define ecap_intr_remap(e) ((e >> 3) & 0x1)
104 #define ecap_ext_intr(e) ((e >> 4) & 0x1)
105 #define ecap_cache_hints(e) ((e >> 5) & 0x1)
106 #define ecap_pass_thru(e) ((e >> 6) & 0x1)
108 /* IOTLB_REG */
109 #define DMA_TLB_FLUSH_GRANU_OFFSET 60
110 #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
111 #define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
112 #define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
113 #define DMA_TLB_IIRG(x) (((x) >> 60) & 7)
114 #define DMA_TLB_IAIG(val) (((val) >> 57) & 7)
115 #define DMA_TLB_DID(x) (((u64)(x & 0xffff)) << 32)
117 #define DMA_TLB_READ_DRAIN (((u64)1) << 49)
118 #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
119 #define DMA_TLB_IVT (((u64)1) << 63)
121 #define DMA_TLB_IVA_ADDR(x) ((((u64)x) >> 12) << 12)
122 #define DMA_TLB_IVA_HINT(x) ((((u64)x) & 1) << 6)
124 /* GCMD_REG */
125 #define DMA_GCMD_TE (((u64)1) << 31)
126 #define DMA_GCMD_SRTP (((u64)1) << 30)
127 #define DMA_GCMD_SFL (((u64)1) << 29)
128 #define DMA_GCMD_EAFL (((u64)1) << 28)
129 #define DMA_GCMD_WBF (((u64)1) << 27)
130 #define DMA_GCMD_QIE (((u64)1) << 26)
131 #define DMA_GCMD_IRE (((u64)1) << 25)
132 #define DMA_GCMD_SIRTP (((u64)1) << 24)
133 #define DMA_GCMD_CFI (((u64)1) << 23)
135 /* GSTS_REG */
136 #define DMA_GSTS_TES (((u64)1) << 31)
137 #define DMA_GSTS_RTPS (((u64)1) << 30)
138 #define DMA_GSTS_FLS (((u64)1) << 29)
139 #define DMA_GSTS_AFLS (((u64)1) << 28)
140 #define DMA_GSTS_WBFS (((u64)1) << 27)
141 #define DMA_GSTS_QIES (((u64)1) <<26)
142 #define DMA_GSTS_IRES (((u64)1) <<25)
143 #define DMA_GSTS_SIRTPS (((u64)1) << 24)
144 #define DMA_GSTS_CFIS (((u64)1) <<23)
146 /* PMEN_REG */
147 #define DMA_PMEN_EPM (((u32)1) << 31)
148 #define DMA_PMEN_PRS (((u32)1) << 0)
150 /* CCMD_REG */
151 #define DMA_CCMD_INVL_GRANU_OFFSET 61
152 #define DMA_CCMD_ICC (((u64)1) << 63)
153 #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
154 #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
155 #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
156 #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
157 #define DMA_CCMD_CIRG(x) ((((u64)3) << 61) & x)
158 #define DMA_CCMD_MASK_NOBIT 0
159 #define DMA_CCMD_MASK_1BIT 1
160 #define DMA_CCMD_MASK_2BIT 2
161 #define DMA_CCMD_MASK_3BIT 3
162 #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
163 #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
165 #define DMA_CCMD_CAIG_MASK(x) (((u64)x) & ((u64) 0x3 << 59))
167 /* FECTL_REG */
168 #define DMA_FECTL_IM (((u64)1) << 31)
170 /* FSTS_REG */
171 #define DMA_FSTS_PFO ((u64)1 << 0)
172 #define DMA_FSTS_PPF ((u64)1 << 1)
173 #define DMA_FSTS_AFO ((u64)1 << 2)
174 #define DMA_FSTS_APF ((u64)1 << 3)
175 #define DMA_FSTS_IQE ((u64)1 << 4)
176 #define DMA_FSTS_ICE ((u64)1 << 5)
177 #define DMA_FSTS_ITE ((u64)1 << 6)
178 #define DMA_FSTS_FAULTS DMA_FSTS_PFO | DMA_FSTS_PPF | DMA_FSTS_AFO | DMA_FSTS_APF | DMA_FSTS_IQE | DMA_FSTS_ICE | DMA_FSTS_ITE
179 #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
181 /* FRCD_REG, 32 bits access */
182 #define DMA_FRCD_F (((u64)1) << 31)
183 #define dma_frcd_type(d) ((d >> 30) & 1)
184 #define dma_frcd_fault_reason(c) (c & 0xff)
185 #define dma_frcd_source_id(c) (c & 0xffff)
186 #define dma_frcd_page_addr(d) (d & (((u64)-1) << 12)) /* low 64 bit */
188 /*
189 * 0: Present
190 * 1-11: Reserved
191 * 12-63: Context Ptr (12 - (haw-1))
192 * 64-127: Reserved
193 */
194 struct root_entry {
195 u64 val;
196 u64 rsvd1;
197 };
198 #define root_present(root) ((root).val & 1)
199 #define set_root_present(root) do {(root).val |= 1;} while(0)
200 #define get_context_addr(root) ((root).val & PAGE_MASK_4K)
201 #define set_root_value(root, value) \
202 do {(root).val |= ((value) & PAGE_MASK_4K);} while(0)
204 struct context_entry {
205 u64 lo;
206 u64 hi;
207 };
208 #define ROOT_ENTRY_NR (PAGE_SIZE_4K/sizeof(struct root_entry))
209 #define context_present(c) ((c).lo & 1)
210 #define context_fault_disable(c) (((c).lo >> 1) & 1)
211 #define context_translation_type(c) (((c).lo >> 2) & 3)
212 #define context_address_root(c) ((c).lo & PAGE_MASK_4K)
213 #define context_address_width(c) ((c).hi & 7)
214 #define context_domain_id(c) (((c).hi >> 8) & ((1 << 16) - 1))
216 #define context_set_present(c) do {(c).lo |= 1;} while(0)
217 #define context_clear_present(c) do {(c).lo &= ~1;} while(0)
218 #define context_set_fault_enable(c) \
219 do {(c).lo &= (((u64)-1) << 2) | 1;} while(0)
221 #define context_set_translation_type(c, val) do { \
222 (c).lo &= (((u64)-1) << 4) | 3; \
223 (c).lo |= (val & 3) << 2; \
224 } while(0)
225 #define CONTEXT_TT_MULTI_LEVEL 0
226 #define CONTEXT_TT_DEV_IOTLB 1
227 #define CONTEXT_TT_PASS_THRU 2
229 #define context_set_address_root(c, val) \
230 do {(c).lo &= 0xfff; (c).lo |= (val) & PAGE_MASK_4K ;} while(0)
231 #define context_set_address_width(c, val) \
232 do {(c).hi &= 0xfffffff8; (c).hi |= (val) & 7;} while(0)
233 #define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while(0)
235 /* page table handling */
236 #define LEVEL_STRIDE (9)
237 #define LEVEL_MASK ((1 << LEVEL_STRIDE) - 1)
238 #define PTE_NUM (1 << LEVEL_STRIDE)
239 #define agaw_to_level(val) ((val) + 2)
240 #define agaw_to_width(val) (30 + val * LEVEL_STRIDE)
241 #define width_to_agaw(w) ((w - 30)/LEVEL_STRIDE)
242 #define level_to_offset_bits(l) (12 + (l - 1) * LEVEL_STRIDE)
243 #define address_level_offset(addr, level) \
244 ((addr >> level_to_offset_bits(level)) & LEVEL_MASK)
245 #define level_mask(l) (((u64)(-1)) << level_to_offset_bits(l))
246 #define level_size(l) (1 << level_to_offset_bits(l))
247 #define align_to_level(addr, l) ((addr + level_size(l) - 1) & level_mask(l))
249 /*
250 * 0: readable
251 * 1: writable
252 * 2-6: reserved
253 * 7: super page
254 * 8-11: available
255 * 12-63: Host physcial address
256 */
257 struct dma_pte {
258 u64 val;
259 };
260 #define dma_clear_pte(p) do {(p).val = 0;} while(0)
261 #define dma_set_pte_readable(p) do {(p).val |= 1;} while(0)
262 #define dma_set_pte_writable(p) do {(p).val |= 2;} while(0)
263 #define dma_set_pte_superpage(p) do {(p).val |= 8;} while(0)
264 #define dma_set_pte_prot(p, prot) do { (p).val = (((p).val >> 2) << 2) | ((prot) & 3);} while (0)
265 #define dma_pte_addr(p) ((p).val & PAGE_MASK_4K)
266 #define dma_set_pte_addr(p, addr) do {(p).val |= ((addr) >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K;} while(0)
267 #define DMA_PTE_READ (1)
268 #define DMA_PTE_WRITE (2)
269 #define dma_pte_present(p) (((p).val & 3) != 0)
271 /* interrupt remap entry */
272 struct iremap_entry {
273 union {
274 u64 lo_val;
275 struct {
276 u64 p : 1,
277 fpd : 1,
278 dm : 1,
279 rh : 1,
280 tm : 1,
281 dlm : 3,
282 avail : 4,
283 res_1 : 4,
284 vector : 8,
285 res_2 : 8,
286 dst : 32;
287 }lo;
288 };
289 union {
290 u64 hi_val;
291 struct {
292 u64 sid : 16,
293 sq : 2,
294 svt : 2,
295 res_1 : 44;
296 }hi;
297 };
298 };
299 #define IREMAP_ENTRY_NR (PAGE_SIZE_4K/sizeof(struct iremap_entry))
300 #define iremap_present(v) ((v).lo & 1)
301 #define iremap_fault_disable(v) (((v).lo >> 1) & 1)
303 #define iremap_set_present(v) do {(v).lo |= 1;} while(0)
304 #define iremap_clear_present(v) do {(v).lo &= ~1;} while(0)
306 /* queue invalidation entry */
307 struct qinval_entry {
308 union {
309 struct {
310 struct {
311 u64 type : 4,
312 granu : 2,
313 res_1 : 10,
314 did : 16,
315 sid : 16,
316 fm : 2,
317 res_2 : 14;
318 }lo;
319 struct {
320 u64 res;
321 }hi;
322 }cc_inv_dsc;
323 struct {
324 struct {
325 u64 type : 4,
326 granu : 2,
327 dw : 1,
328 dr : 1,
329 res_1 : 8,
330 did : 16,
331 res_2 : 32;
332 }lo;
333 struct {
334 u64 am : 6,
335 ih : 1,
336 res_1 : 5,
337 addr : 52;
338 }hi;
339 }iotlb_inv_dsc;
340 struct {
341 struct {
342 u64 type : 4,
343 res_1 : 12,
344 max_invs_pend: 5,
345 res_2 : 11,
346 sid : 16,
347 res_3 : 16;
348 }lo;
349 struct {
350 u64 size : 1,
351 res_1 : 11,
352 addr : 52;
353 }hi;
354 }dev_iotlb_inv_dsc;
355 struct {
356 struct {
357 u64 type : 4,
358 granu : 1,
359 res_1 : 22,
360 im : 5,
361 iidx : 16,
362 res_2 : 16;
363 }lo;
364 struct {
365 u64 res;
366 }hi;
367 }iec_inv_dsc;
368 struct {
369 struct {
370 u64 type : 4,
371 iflag : 1,
372 sw : 1,
373 fn : 1,
374 res_1 : 25,
375 sdata : 32;
376 }lo;
377 struct {
378 u64 res_1 : 2,
379 saddr : 62;
380 }hi;
381 }inv_wait_dsc;
382 }q;
383 };
385 struct poll_info {
386 u64 saddr;
387 u32 udata;
388 };
390 #define QINVAL_ENTRY_NR (PAGE_SIZE_4K/sizeof(struct qinval_entry))
391 #define qinval_present(v) ((v).lo & 1)
392 #define qinval_fault_disable(v) (((v).lo >> 1) & 1)
394 #define qinval_set_present(v) do {(v).lo |= 1;} while(0)
395 #define qinval_clear_present(v) do {(v).lo &= ~1;} while(0)
397 #define RESERVED_VAL 0
399 #define TYPE_INVAL_CONTEXT 0x1
400 #define TYPE_INVAL_IOTLB 0x2
401 #define TYPE_INVAL_DEVICE_IOTLB 0x3
402 #define TYPE_INVAL_IEC 0x4
403 #define TYPE_INVAL_WAIT 0x5
405 #define NOTIFY_TYPE_POLL 1
406 #define NOTIFY_TYPE_INTR 1
407 #define INTERRUTP_FLAG 1
408 #define STATUS_WRITE 1
409 #define FENCE_FLAG 1
411 #define IEC_GLOBAL_INVL 0
412 #define IEC_INDEX_INVL 1
413 #define IRTA_REG_EIME_SHIFT 11
414 #define IRTA_REG_TABLE_SIZE 7 // 4k page = 256 * 16 byte entries
415 // 2^^(IRTA_REG_TABLE_SIZE + 1) = 256
416 // IRTA_REG_TABLE_SIZE = 7
418 #define VTD_PAGE_TABLE_LEVEL_3 3
419 #define VTD_PAGE_TABLE_LEVEL_4 4
421 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
422 #define MAX_IOMMU_REGS 0xc0
424 extern struct list_head acpi_drhd_units;
425 extern struct list_head acpi_rmrr_units;
426 extern struct list_head acpi_ioapic_units;
428 struct qi_ctrl {
429 u64 qinval_maddr; /* queue invalidation page machine address */
430 int qinval_index; /* queue invalidation index */
431 spinlock_t qinval_lock; /* lock for queue invalidation page */
432 spinlock_t qinval_poll_lock; /* lock for queue invalidation poll addr */
433 volatile u32 qinval_poll_status; /* used by poll methord to sync */
434 };
436 struct ir_ctrl {
437 u64 iremap_maddr; /* interrupt remap table machine address */
438 int iremap_index; /* interrupt remap index */
439 spinlock_t iremap_lock; /* lock for irq remappping table */
440 };
442 struct iommu_flush {
443 int (*context)(void *iommu, u16 did, u16 source_id,
444 u8 function_mask, u64 type, int non_present_entry_flush);
445 int (*iotlb)(void *iommu, u16 did, u64 addr, unsigned int size_order,
446 u64 type, int non_present_entry_flush);
447 };
449 struct intel_iommu {
450 struct qi_ctrl qi_ctrl;
451 struct ir_ctrl ir_ctrl;
452 struct iommu_flush flush;
453 };
455 #endif