debuggers.hg

view xen/include/asm-x86/config.h @ 20966:83a6621b91bf

x86: move trampoline location

A partner of ours is reporting boot failures (Xen not even emitting a
single message) over iSCSI on new (UEFI based) systems. After
pointing at their BIOS initially I finally remembered to take a look
at the memory map a native kernel booted this way see - and voila, the
BIOS reports memory starting at 0x8d000 as reserved. Xen, however,
places about 12k of (trampoline) data at 0x8c000.

For now, move the trampolien down by 4kB to 0x88000. Later we may
choose the location dynamically based on E820 information, if this
proves to be an ongoing problem.

One thing this patch enforces in any case is a single point of
definition for the hard coded location, so that at least adjusting it
won't require more than a single line change in the future.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Feb 10 09:20:56 2010 +0000 (2010-02-10)
parents 059c01d69a08
children ef845a385014
line source
1 /******************************************************************************
2 * config.h
3 *
4 * A Linux-style configuration list.
5 */
7 #ifndef __X86_CONFIG_H__
8 #define __X86_CONFIG_H__
10 #if defined(__x86_64__)
11 # define CONFIG_PAGING_LEVELS 4
12 #else
13 # define CONFIG_PAGING_LEVELS 3
14 #endif
16 #define CONFIG_X86 1
17 #define CONFIG_X86_HT 1
18 #define CONFIG_PAGING_ASSISTANCE 1
19 #define CONFIG_SMP 1
20 #define CONFIG_X86_LOCAL_APIC 1
21 #define CONFIG_X86_GOOD_APIC 1
22 #define CONFIG_X86_IO_APIC 1
23 #define CONFIG_X86_PM_TIMER 1
24 #define CONFIG_HPET_TIMER 1
25 #define CONFIG_X86_MCE_THERMAL 1
26 #define CONFIG_NUMA 1
27 #define CONFIG_DISCONTIGMEM 1
28 #define CONFIG_NUMA_EMU 1
30 /* Intel P4 currently has largest cache line (L2 line size is 128 bytes). */
31 #define CONFIG_X86_L1_CACHE_SHIFT 7
33 #define CONFIG_ACPI 1
34 #define CONFIG_ACPI_BOOT 1
35 #define CONFIG_ACPI_SLEEP 1
36 #define CONFIG_ACPI_NUMA 1
37 #define CONFIG_ACPI_SRAT 1
38 #define CONFIG_ACPI_CSTATE 1
40 #define CONFIG_VGA 1
42 #define CONFIG_HOTPLUG 1
43 #define CONFIG_HOTPLUG_CPU 1
45 #define HZ 100
47 #define OPT_CONSOLE_STR "vga"
49 #ifdef MAX_PHYS_CPUS
50 #define NR_CPUS MAX_PHYS_CPUS
51 #else
52 #define NR_CPUS 64
53 #endif
55 #ifdef __i386__
56 /* Maximum number of virtual CPUs in multi-processor guests. */
57 #define MAX_VIRT_CPUS XEN_LEGACY_MAX_VCPUS
58 #endif
60 /* Maximum we can support with current vLAPIC ID mapping. */
61 #define MAX_HVM_VCPUS 128
63 #ifdef CONFIG_X86_SUPERVISOR_MODE_KERNEL
64 # define supervisor_mode_kernel (1)
65 #else
66 # define supervisor_mode_kernel (0)
67 #endif
69 /* Linkage for x86 */
70 #define __ALIGN .align 16,0x90
71 #define __ALIGN_STR ".align 16,0x90"
72 #ifdef __ASSEMBLY__
73 #define ALIGN __ALIGN
74 #define ALIGN_STR __ALIGN_STR
75 #define ENTRY(name) \
76 .globl name; \
77 ALIGN; \
78 name:
79 #endif
81 #define NR_hypercalls 64
83 #ifndef NDEBUG
84 #define MEMORY_GUARD
85 #endif
87 #ifdef __i386__
88 #define STACK_ORDER 2
89 #else
90 #define STACK_ORDER 3
91 #endif
92 #define STACK_SIZE (PAGE_SIZE << STACK_ORDER)
94 /* Primary stack is restricted to 8kB by guard pages. */
95 #define PRIMARY_STACK_SIZE 8192
97 #define BOOT_TRAMPOLINE 0x88000
98 #define bootsym_phys(sym) \
99 (((unsigned long)&(sym)-(unsigned long)&trampoline_start)+BOOT_TRAMPOLINE)
100 #define bootsym(sym) \
101 (*RELOC_HIDE((typeof(&(sym)))__va(__pa(&(sym))), \
102 BOOT_TRAMPOLINE-__pa(trampoline_start)))
103 #ifndef __ASSEMBLY__
104 extern char trampoline_start[], trampoline_end[];
105 extern char trampoline_realmode_entry[];
106 extern unsigned int trampoline_xen_phys_start;
107 extern unsigned char trampoline_cpu_started;
108 extern char wakeup_start[];
109 extern unsigned int video_mode, video_flags;
110 #endif
112 #if defined(__x86_64__)
114 #define CONFIG_X86_64 1
115 #define CONFIG_COMPAT 1
117 #define asmlinkage
119 #define PML4_ENTRY_BITS 39
120 #ifndef __ASSEMBLY__
121 #define PML4_ENTRY_BYTES (1UL << PML4_ENTRY_BITS)
122 #define PML4_ADDR(_slot) \
123 ((((_slot ## UL) >> 8) * 0xffff000000000000UL) | \
124 (_slot ## UL << PML4_ENTRY_BITS))
125 #define GB(_gb) (_gb ## UL << 30)
126 #else
127 #define PML4_ENTRY_BYTES (1 << PML4_ENTRY_BITS)
128 #define PML4_ADDR(_slot) \
129 (((_slot >> 8) * 0xffff000000000000) | (_slot << PML4_ENTRY_BITS))
130 #define GB(_gb) (_gb << 30)
131 #endif
133 /*
134 * Memory layout:
135 * 0x0000000000000000 - 0x00007fffffffffff [128TB, 2^47 bytes, PML4:0-255]
136 * Guest-defined use (see below for compatibility mode guests).
137 * 0x0000800000000000 - 0xffff7fffffffffff [16EB]
138 * Inaccessible: current arch only supports 48-bit sign-extended VAs.
139 * 0xffff800000000000 - 0xffff803fffffffff [256GB, 2^38 bytes, PML4:256]
140 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
141 * 0xffff804000000000 - 0xffff807fffffffff [256GB, 2^38 bytes, PML4:256]
142 * Reserved for future shared info with the guest OS (GUEST ACCESSIBLE).
143 * 0xffff808000000000 - 0xffff80ffffffffff [512GB, 2^39 bytes, PML4:257]
144 * ioremap for PCI mmconfig space
145 * 0xffff810000000000 - 0xffff817fffffffff [512GB, 2^39 bytes, PML4:258]
146 * Guest linear page table.
147 * 0xffff818000000000 - 0xffff81ffffffffff [512GB, 2^39 bytes, PML4:259]
148 * Shadow linear page table.
149 * 0xffff820000000000 - 0xffff827fffffffff [512GB, 2^39 bytes, PML4:260]
150 * Per-domain mappings (e.g., GDT, LDT).
151 * 0xffff828000000000 - 0xffff82bfffffffff [256GB, 2^38 bytes, PML4:261]
152 * Machine-to-phys translation table.
153 * 0xffff82c000000000 - 0xffff82c3ffffffff [16GB, 2^34 bytes, PML4:261]
154 * ioremap()/fixmap area.
155 * 0xffff82c400000000 - 0xffff82c43fffffff [1GB, 2^30 bytes, PML4:261]
156 * Compatibility machine-to-phys translation table.
157 * 0xffff82c440000000 - 0xffff82c47fffffff [1GB, 2^30 bytes, PML4:261]
158 * High read-only compatibility machine-to-phys translation table.
159 * 0xffff82c480000000 - 0xffff82c4bfffffff [1GB, 2^30 bytes, PML4:261]
160 * Xen text, static data, bss.
161 * 0xffff82c4c0000000 - 0xffff82f5ffffffff [197GB, PML4:261]
162 * Reserved for future use.
163 * 0xffff82f600000000 - 0xffff82ffffffffff [40GB, 2^38 bytes, PML4:261]
164 * Page-frame information array.
165 * 0xffff830000000000 - 0xffff87ffffffffff [5TB, 5*2^40 bytes, PML4:262-271]
166 * 1:1 direct mapping of all physical memory.
167 * 0xffff880000000000 - 0xffffffffffffffff [120TB, PML4:272-511]
168 * Guest-defined use.
169 *
170 * Compatibility guest area layout:
171 * 0x0000000000000000 - 0x00000000f57fffff [3928MB, PML4:0]
172 * Guest-defined use.
173 * 0x00000000f5800000 - 0x00000000ffffffff [168MB, PML4:0]
174 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
175 * 0x0000000100000000 - 0x0000007fffffffff [508GB, PML4:0]
176 * Unused.
177 * 0x0000008000000000 - 0x000000ffffffffff [512GB, 2^39 bytes, PML4:1]
178 * Hypercall argument translation area.
179 * 0x0000010000000000 - 0x00007fffffffffff [127TB, 2^46 bytes, PML4:2-255]
180 * Reserved for future use.
181 */
184 #define ROOT_PAGETABLE_FIRST_XEN_SLOT 256
185 #define ROOT_PAGETABLE_LAST_XEN_SLOT 271
186 #define ROOT_PAGETABLE_XEN_SLOTS \
187 (ROOT_PAGETABLE_LAST_XEN_SLOT - ROOT_PAGETABLE_FIRST_XEN_SLOT + 1)
189 /* Hypervisor reserves PML4 slots 256 to 271 inclusive. */
190 #define HYPERVISOR_VIRT_START (PML4_ADDR(256))
191 #define HYPERVISOR_VIRT_END (HYPERVISOR_VIRT_START + PML4_ENTRY_BYTES*16)
192 /* Slot 256: read-only guest-accessible machine-to-phys translation table. */
193 #define RO_MPT_VIRT_START (PML4_ADDR(256))
194 #define MPT_VIRT_SIZE (PML4_ENTRY_BYTES / 2)
195 #define RO_MPT_VIRT_END (RO_MPT_VIRT_START + MPT_VIRT_SIZE)
196 /* Slot 257: ioremap for PCI mmconfig space for 2048 segments (512GB)
197 * - full 16-bit segment support needs 44 bits
198 * - since PML4 slot has 39 bits, we limit segments to 2048 (11-bits)
199 */
200 #define PCI_MCFG_VIRT_START (PML4_ADDR(257))
201 #define PCI_MCFG_VIRT_END (PCI_MCFG_VIRT_START + PML4_ENTRY_BYTES)
202 /* Slot 258: linear page table (guest table). */
203 #define LINEAR_PT_VIRT_START (PML4_ADDR(258))
204 #define LINEAR_PT_VIRT_END (LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
205 /* Slot 259: linear page table (shadow table). */
206 #define SH_LINEAR_PT_VIRT_START (PML4_ADDR(259))
207 #define SH_LINEAR_PT_VIRT_END (SH_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
208 /* Slot 260: per-domain mappings. */
209 #define PERDOMAIN_VIRT_START (PML4_ADDR(260))
210 #define PERDOMAIN_VIRT_END (PERDOMAIN_VIRT_START + (PERDOMAIN_MBYTES<<20))
211 #define PERDOMAIN_MBYTES (PML4_ENTRY_BYTES >> (20 + PAGETABLE_ORDER))
212 /* Slot 261: machine-to-phys conversion table (256GB). */
213 #define RDWR_MPT_VIRT_START (PML4_ADDR(261))
214 #define RDWR_MPT_VIRT_END (RDWR_MPT_VIRT_START + MPT_VIRT_SIZE)
215 /* Slot 261: ioremap()/fixmap area (16GB). */
216 #define IOREMAP_VIRT_START RDWR_MPT_VIRT_END
217 #define IOREMAP_VIRT_END (IOREMAP_VIRT_START + GB(16))
218 /* Slot 261: compatibility machine-to-phys conversion table (1GB). */
219 #define RDWR_COMPAT_MPT_VIRT_START IOREMAP_VIRT_END
220 #define RDWR_COMPAT_MPT_VIRT_END (RDWR_COMPAT_MPT_VIRT_START + GB(1))
221 /* Slot 261: high read-only compat machine-to-phys conversion table (1GB). */
222 #define HIRO_COMPAT_MPT_VIRT_START RDWR_COMPAT_MPT_VIRT_END
223 #define HIRO_COMPAT_MPT_VIRT_END (HIRO_COMPAT_MPT_VIRT_START + GB(1))
224 /* Slot 261: xen text, static data and bss (1GB). */
225 #define XEN_VIRT_START (HIRO_COMPAT_MPT_VIRT_END)
226 #define XEN_VIRT_END (XEN_VIRT_START + GB(1))
227 /* Slot 261: page-frame information array (40GB). */
228 #define FRAMETABLE_VIRT_END DIRECTMAP_VIRT_START
229 #define FRAMETABLE_SIZE ((DIRECTMAP_SIZE >> PAGE_SHIFT) * \
230 sizeof(struct page_info))
231 #define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - FRAMETABLE_SIZE)
232 /* Slot 262-271: A direct 1:1 mapping of all of physical memory. */
233 #define DIRECTMAP_VIRT_START (PML4_ADDR(262))
234 #define DIRECTMAP_SIZE (PML4_ENTRY_BYTES*10)
235 #define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + DIRECTMAP_SIZE)
237 #ifndef __ASSEMBLY__
239 /* This is not a fixed value, just a lower limit. */
240 #define __HYPERVISOR_COMPAT_VIRT_START 0xF5800000
241 #define HYPERVISOR_COMPAT_VIRT_START(d) ((d)->arch.hv_compat_vstart)
242 #define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START
243 #define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000
244 #define MACH2PHYS_COMPAT_NR_ENTRIES(d) \
245 ((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2)
247 #define COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) \
248 l2_table_offset(HYPERVISOR_COMPAT_VIRT_START(d))
249 #define COMPAT_L2_PAGETABLE_LAST_XEN_SLOT l2_table_offset(~0U)
250 #define COMPAT_L2_PAGETABLE_XEN_SLOTS(d) \
251 (COMPAT_L2_PAGETABLE_LAST_XEN_SLOT - COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) + 1)
253 #define COMPAT_LEGACY_MAX_VCPUS XEN_LEGACY_MAX_VCPUS
255 #endif
257 #define PGT_base_page_table PGT_l4_page_table
259 #define __HYPERVISOR_CS64 0xe008
260 #define __HYPERVISOR_CS32 0xe038
261 #define __HYPERVISOR_CS __HYPERVISOR_CS64
262 #define __HYPERVISOR_DS64 0x0000
263 #define __HYPERVISOR_DS32 0xe010
264 #define __HYPERVISOR_DS __HYPERVISOR_DS64
266 #define SYMBOLS_ORIGIN XEN_VIRT_START
268 /* For generic assembly code: use macros to define operation/operand sizes. */
269 #define __OS "q" /* Operation Suffix */
270 #define __OP "r" /* Operand Prefix */
271 #define __FIXUP_ALIGN ".align 8"
272 #define __FIXUP_WORD ".quad"
274 #elif defined(__i386__)
276 #define CONFIG_X86_32 1
277 #define CONFIG_DOMAIN_PAGE 1
279 #define asmlinkage __attribute__((regparm(0)))
281 /*
282 * Memory layout (high to low): PAE-SIZE
283 * ------
284 * I/O remapping area ( 4MB)
285 * Direct-map (1:1) area [Xen code/data/heap] (12MB)
286 * Per-domain mappings (inc. 4MB map_domain_page cache) ( 8MB)
287 * Shadow linear pagetable ( 8MB)
288 * Guest linear pagetable ( 8MB)
289 * Machine-to-physical translation table [writable] (16MB)
290 * Frame-info table (96MB)
291 * * Start of guest inaccessible area
292 * Machine-to-physical translation table [read-only] (16MB)
293 * * Start of guest unmodifiable area
294 */
296 #define IOREMAP_MBYTES 4
297 #define DIRECTMAP_MBYTES 12
298 #define MAPCACHE_MBYTES 4
299 #define PERDOMAIN_MBYTES 8
301 #define LINEARPT_MBYTES 8
302 #define MACHPHYS_MBYTES 16 /* 1 MB needed per 1 GB memory */
303 #define FRAMETABLE_MBYTES (MACHPHYS_MBYTES * 6)
305 #define IOREMAP_VIRT_END 0UL
306 #define IOREMAP_VIRT_START (IOREMAP_VIRT_END - (IOREMAP_MBYTES<<20))
307 #define DIRECTMAP_VIRT_END IOREMAP_VIRT_START
308 #define DIRECTMAP_VIRT_START (DIRECTMAP_VIRT_END - (DIRECTMAP_MBYTES<<20))
309 #define MAPCACHE_VIRT_END DIRECTMAP_VIRT_START
310 #define MAPCACHE_VIRT_START (MAPCACHE_VIRT_END - (MAPCACHE_MBYTES<<20))
311 #define PERDOMAIN_VIRT_END DIRECTMAP_VIRT_START
312 #define PERDOMAIN_VIRT_START (PERDOMAIN_VIRT_END - (PERDOMAIN_MBYTES<<20))
313 #define SH_LINEAR_PT_VIRT_END PERDOMAIN_VIRT_START
314 #define SH_LINEAR_PT_VIRT_START (SH_LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
315 #define LINEAR_PT_VIRT_END SH_LINEAR_PT_VIRT_START
316 #define LINEAR_PT_VIRT_START (LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
317 #define RDWR_MPT_VIRT_END LINEAR_PT_VIRT_START
318 #define RDWR_MPT_VIRT_START (RDWR_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
319 #define FRAMETABLE_VIRT_END RDWR_MPT_VIRT_START
320 #define FRAMETABLE_SIZE (FRAMETABLE_MBYTES<<20)
321 #define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - FRAMETABLE_SIZE)
322 #define RO_MPT_VIRT_END FRAMETABLE_VIRT_START
323 #define RO_MPT_VIRT_START (RO_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
325 #define DIRECTMAP_PHYS_END (DIRECTMAP_MBYTES<<20)
327 /* Maximum linear address accessible via guest memory segments. */
328 #define GUEST_SEGMENT_MAX_ADDR RO_MPT_VIRT_END
330 /* Hypervisor owns top 168MB of virtual address space. */
331 #define HYPERVISOR_VIRT_START mk_unsigned_long(0xF5800000)
333 #define L2_PAGETABLE_FIRST_XEN_SLOT \
334 (HYPERVISOR_VIRT_START >> L2_PAGETABLE_SHIFT)
335 #define L2_PAGETABLE_LAST_XEN_SLOT \
336 (~0UL >> L2_PAGETABLE_SHIFT)
337 #define L2_PAGETABLE_XEN_SLOTS \
338 (L2_PAGETABLE_LAST_XEN_SLOT - L2_PAGETABLE_FIRST_XEN_SLOT + 1)
340 #define PGT_base_page_table PGT_l3_page_table
342 #define __HYPERVISOR_CS 0xe008
343 #define __HYPERVISOR_DS 0xe010
345 /* For generic assembly code: use macros to define operation/operand sizes. */
346 #define __OS "l" /* Operation Suffix */
347 #define __OP "e" /* Operand Prefix */
348 #define __FIXUP_ALIGN ".align 4"
349 #define __FIXUP_WORD ".long"
351 #endif /* __i386__ */
353 #ifndef __ASSEMBLY__
354 extern unsigned long xen_phys_start;
355 #if defined(__i386__)
356 extern unsigned long xenheap_phys_end;
357 #endif
358 #endif
360 /* GDT/LDT shadow mapping area. The first per-domain-mapping sub-area. */
361 #define GDT_LDT_VCPU_SHIFT 5
362 #define GDT_LDT_VCPU_VA_SHIFT (GDT_LDT_VCPU_SHIFT + PAGE_SHIFT)
363 #ifdef MAX_VIRT_CPUS
364 #define GDT_LDT_MBYTES (MAX_VIRT_CPUS >> (20-GDT_LDT_VCPU_VA_SHIFT))
365 #else
366 #define GDT_LDT_MBYTES PERDOMAIN_MBYTES
367 #define MAX_VIRT_CPUS (GDT_LDT_MBYTES << (20-GDT_LDT_VCPU_VA_SHIFT))
368 #endif
369 #define GDT_LDT_VIRT_START PERDOMAIN_VIRT_START
370 #define GDT_LDT_VIRT_END (GDT_LDT_VIRT_START + (GDT_LDT_MBYTES << 20))
372 /* The address of a particular VCPU's GDT or LDT. */
373 #define GDT_VIRT_START(v) \
374 (PERDOMAIN_VIRT_START + ((v)->vcpu_id << GDT_LDT_VCPU_VA_SHIFT))
375 #define LDT_VIRT_START(v) \
376 (GDT_VIRT_START(v) + (64*1024))
378 #define PDPT_L1_ENTRIES \
379 ((PERDOMAIN_VIRT_END - PERDOMAIN_VIRT_START) >> PAGE_SHIFT)
380 #define PDPT_L2_ENTRIES \
381 ((PDPT_L1_ENTRIES + (1 << PAGETABLE_ORDER) - 1) >> PAGETABLE_ORDER)
383 #if defined(__x86_64__)
384 #define ELFSIZE 64
385 #else
386 #define ELFSIZE 32
387 #endif
389 #define ARCH_CRASH_SAVE_VMCOREINFO
391 #endif /* __X86_CONFIG_H__ */