debuggers.hg

view xen/drivers/char/ns16550.c @ 21015:8cb6e7eff2ba

x86: Generalise BUGFRAME_dump mechanism to allow polled UART irq to
get proper regs argument.

Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Feb 24 10:44:30 2010 +0000 (2010-02-24)
parents 12fc55dffb6b
children 81d9132ce00d
line source
1 /******************************************************************************
2 * ns16550.c
3 *
4 * Driver for 16550-series UARTs. This driver is to be kept within Xen as
5 * it permits debugging of seriously-toasted machines (e.g., in situations
6 * where a device driver within a guest OS would be inaccessible).
7 *
8 * Copyright (c) 2003-2005, K A Fraser
9 */
11 #include <xen/config.h>
12 #include <xen/console.h>
13 #include <xen/init.h>
14 #include <xen/irq.h>
15 #include <xen/sched.h>
16 #include <xen/serial.h>
17 #include <xen/iocap.h>
18 #include <asm/io.h>
20 /*
21 * Configure serial port with a string:
22 * <baud>[/<clock_hz>][,DPS[,<io-base>[,<irq>]]].
23 * The tail of the string can be omitted if platform defaults are sufficient.
24 * If the baud rate is pre-configured, perhaps by a bootloader, then 'auto'
25 * can be specified in place of a numeric baud rate. Polled mode is specified
26 * by requesting irq 0.
27 */
28 static char __initdata opt_com1[30] = "";
29 static char __initdata opt_com2[30] = "";
30 string_param("com1", opt_com1);
31 string_param("com2", opt_com2);
33 static struct ns16550 {
34 int baud, clock_hz, data_bits, parity, stop_bits, irq;
35 unsigned long io_base; /* I/O port or memory-mapped I/O address. */
36 char *remapped_io_base; /* Remapped virtual address of mmap I/O. */
37 /* UART with IRQ line: interrupt-driven I/O. */
38 struct irqaction irqaction;
39 /* UART with no IRQ line: periodically-polled I/O. */
40 struct timer timer;
41 unsigned int timeout_ms;
42 int probing, intr_works;
43 } ns16550_com[2] = { { 0 } };
45 /* Register offsets */
46 #define RBR 0x00 /* receive buffer */
47 #define THR 0x00 /* transmit holding */
48 #define IER 0x01 /* interrupt enable */
49 #define IIR 0x02 /* interrupt identity */
50 #define FCR 0x02 /* FIFO control */
51 #define LCR 0x03 /* line control */
52 #define MCR 0x04 /* Modem control */
53 #define LSR 0x05 /* line status */
54 #define MSR 0x06 /* Modem status */
55 #define DLL 0x00 /* divisor latch (ls) (DLAB=1) */
56 #define DLM 0x01 /* divisor latch (ms) (DLAB=1) */
58 /* Interrupt Enable Register */
59 #define IER_ERDAI 0x01 /* rx data recv'd */
60 #define IER_ETHREI 0x02 /* tx reg. empty */
61 #define IER_ELSI 0x04 /* rx line status */
62 #define IER_EMSI 0x08 /* MODEM status */
64 /* Interrupt Identification Register */
65 #define IIR_NOINT 0x01 /* no interrupt pending */
66 #define IIR_IMASK 0x06 /* interrupt identity: */
67 #define IIR_LSI 0x06 /* - rx line status */
68 #define IIR_RDAI 0x04 /* - rx data recv'd */
69 #define IIR_THREI 0x02 /* - tx reg. empty */
70 #define IIR_MSI 0x00 /* - MODEM status */
72 /* FIFO Control Register */
73 #define FCR_ENABLE 0x01 /* enable FIFO */
74 #define FCR_CLRX 0x02 /* clear Rx FIFO */
75 #define FCR_CLTX 0x04 /* clear Tx FIFO */
76 #define FCR_DMA 0x10 /* enter DMA mode */
77 #define FCR_TRG1 0x00 /* Rx FIFO trig lev 1 */
78 #define FCR_TRG4 0x40 /* Rx FIFO trig lev 4 */
79 #define FCR_TRG8 0x80 /* Rx FIFO trig lev 8 */
80 #define FCR_TRG14 0xc0 /* Rx FIFO trig lev 14 */
82 /* Line Control Register */
83 #define LCR_DLAB 0x80 /* Divisor Latch Access */
85 /* Modem Control Register */
86 #define MCR_DTR 0x01 /* Data Terminal Ready */
87 #define MCR_RTS 0x02 /* Request to Send */
88 #define MCR_OUT2 0x08 /* OUT2: interrupt mask */
89 #define MCR_LOOP 0x10 /* Enable loopback test mode */
91 /* Line Status Register */
92 #define LSR_DR 0x01 /* Data ready */
93 #define LSR_OE 0x02 /* Overrun */
94 #define LSR_PE 0x04 /* Parity error */
95 #define LSR_FE 0x08 /* Framing error */
96 #define LSR_BI 0x10 /* Break */
97 #define LSR_THRE 0x20 /* Xmit hold reg empty */
98 #define LSR_TEMT 0x40 /* Xmitter empty */
99 #define LSR_ERR 0x80 /* Error */
101 /* These parity settings can be ORed directly into the LCR. */
102 #define PARITY_NONE (0<<3)
103 #define PARITY_ODD (1<<3)
104 #define PARITY_EVEN (3<<3)
105 #define PARITY_MARK (5<<3)
106 #define PARITY_SPACE (7<<3)
108 /* Frequency of external clock source. This definition assumes PC platform. */
109 #define UART_CLOCK_HZ 1843200
111 static char ns_read_reg(struct ns16550 *uart, int reg)
112 {
113 if ( uart->remapped_io_base == NULL )
114 return inb(uart->io_base + reg);
115 return readb(uart->remapped_io_base + reg);
116 }
118 static void ns_write_reg(struct ns16550 *uart, int reg, char c)
119 {
120 if ( uart->remapped_io_base == NULL )
121 return outb(c, uart->io_base + reg);
122 writeb(c, uart->remapped_io_base + reg);
123 }
125 static void ns16550_interrupt(
126 int irq, void *dev_id, struct cpu_user_regs *regs)
127 {
128 struct serial_port *port = dev_id;
129 struct ns16550 *uart = port->uart;
131 if (uart->intr_works == 0)
132 {
133 uart->probing = 0;
134 uart->intr_works = 1;
135 stop_timer(&uart->timer);
136 }
138 while ( !(ns_read_reg(uart, IIR) & IIR_NOINT) )
139 {
140 char lsr = ns_read_reg(uart, LSR);
141 if ( lsr & LSR_THRE )
142 serial_tx_interrupt(port, regs);
143 if ( lsr & LSR_DR )
144 serial_rx_interrupt(port, regs);
145 }
146 }
148 /* Safe: ns16550_poll() runs in softirq context so not reentrant on a given CPU. */
149 static DEFINE_PER_CPU(struct serial_port *, poll_port);
151 static void __ns16550_poll(struct cpu_user_regs *regs)
152 {
153 struct serial_port *port = this_cpu(poll_port);
154 struct ns16550 *uart = port->uart;
156 if ( uart->intr_works )
157 return; /* Interrupts work - no more polling */
159 if ( uart->probing ) {
160 uart->probing = 0;
161 if ( (ns_read_reg(uart, LSR) & 0xff) == 0xff )
162 return; /* All bits set - probably no UART present */
163 }
165 while ( ns_read_reg(uart, LSR) & LSR_DR )
166 serial_rx_interrupt(port, regs);
168 if ( ns_read_reg(uart, LSR) & LSR_THRE )
169 serial_tx_interrupt(port, regs);
171 set_timer(&uart->timer, NOW() + MILLISECS(uart->timeout_ms));
172 }
174 static void ns16550_poll(void *data)
175 {
176 this_cpu(poll_port) = data;
177 #ifdef run_in_exception_handler
178 run_in_exception_handler(__ns16550_poll);
179 #else
180 __ns16550_poll(guest_cpu_user_regs());
181 #endif
182 }
184 static int ns16550_tx_empty(struct serial_port *port)
185 {
186 struct ns16550 *uart = port->uart;
187 return !!(ns_read_reg(uart, LSR) & LSR_THRE);
188 }
190 static void ns16550_putc(struct serial_port *port, char c)
191 {
192 struct ns16550 *uart = port->uart;
193 ns_write_reg(uart, THR, c);
194 }
196 static int ns16550_getc(struct serial_port *port, char *pc)
197 {
198 struct ns16550 *uart = port->uart;
200 if ( !(ns_read_reg(uart, LSR) & LSR_DR) )
201 return 0;
203 *pc = ns_read_reg(uart, RBR);
204 return 1;
205 }
207 static void __devinit ns16550_init_preirq(struct serial_port *port)
208 {
209 struct ns16550 *uart = port->uart;
210 unsigned char lcr;
211 unsigned int divisor;
213 /* I/O ports are distinguished by their size (16 bits). */
214 if ( uart->io_base >= 0x10000 )
215 uart->remapped_io_base = (char *)ioremap(uart->io_base, 8);
217 lcr = (uart->data_bits - 5) | ((uart->stop_bits - 1) << 2) | uart->parity;
219 /* No interrupts. */
220 ns_write_reg(uart, IER, 0);
222 /* Line control and baud-rate generator. */
223 ns_write_reg(uart, LCR, lcr | LCR_DLAB);
224 if ( uart->baud != BAUD_AUTO )
225 {
226 /* Baud rate specified: program it into the divisor latch. */
227 divisor = uart->clock_hz / (uart->baud << 4);
228 ns_write_reg(uart, DLL, (char)divisor);
229 ns_write_reg(uart, DLM, (char)(divisor >> 8));
230 }
231 else
232 {
233 /* Baud rate already set: read it out from the divisor latch. */
234 divisor = ns_read_reg(uart, DLL);
235 divisor |= ns_read_reg(uart, DLM) << 8;
236 uart->baud = uart->clock_hz / (divisor << 4);
237 }
238 ns_write_reg(uart, LCR, lcr);
240 /* No flow ctrl: DTR and RTS are both wedged high to keep remote happy. */
241 ns_write_reg(uart, MCR, MCR_DTR | MCR_RTS);
243 /* Enable and clear the FIFOs. Set a large trigger threshold. */
244 ns_write_reg(uart, FCR, FCR_ENABLE | FCR_CLRX | FCR_CLTX | FCR_TRG14);
246 /* Check this really is a 16550+. Otherwise we have no FIFOs. */
247 if ( ((ns_read_reg(uart, IIR) & 0xc0) == 0xc0) &&
248 ((ns_read_reg(uart, FCR) & FCR_TRG14) == FCR_TRG14) )
249 port->tx_fifo_size = 16;
250 }
252 static void __devinit ns16550_init_postirq(struct serial_port *port)
253 {
254 struct ns16550 *uart = port->uart;
255 int rc, bits;
257 if ( uart->irq < 0 )
258 return;
260 serial_async_transmit(port);
262 init_timer(&uart->timer, ns16550_poll, port, 0);
263 /* Calculate time to fill RX FIFO and/or empty TX FIFO for polling. */
264 bits = uart->data_bits + uart->stop_bits + !!uart->parity;
265 uart->timeout_ms = max_t(
266 unsigned int, 1, (bits * port->tx_fifo_size * 1000) / uart->baud);
268 if ( uart->irq == 0 )
269 set_timer(&uart->timer, NOW() + MILLISECS(uart->timeout_ms));
270 else
271 {
272 uart->irqaction.handler = ns16550_interrupt;
273 uart->irqaction.name = "ns16550";
274 uart->irqaction.dev_id = port;
275 if ( (rc = setup_irq(uart->irq, &uart->irqaction)) != 0 )
276 printk("ERROR: Failed to allocate ns16550 IRQ %d\n", uart->irq);
278 /* Master interrupt enable; also keep DTR/RTS asserted. */
279 ns_write_reg(uart, MCR, MCR_OUT2 | MCR_DTR | MCR_RTS);
281 /* Enable receive and transmit interrupts. */
282 ns_write_reg(uart, IER, IER_ERDAI | IER_ETHREI);
284 /* Do a timed write to make sure we are getting interrupts. */
285 uart->probing = 1;
286 uart->intr_works = 0;
287 ns_write_reg(uart, THR, 0xff);
288 set_timer(&uart->timer, NOW() + MILLISECS(uart->timeout_ms));
289 }
290 }
292 #ifdef CONFIG_X86
293 static void __init ns16550_endboot(struct serial_port *port)
294 {
295 struct ns16550 *uart = port->uart;
296 if ( ioports_deny_access(dom0, uart->io_base, uart->io_base + 7) != 0 )
297 BUG();
298 }
299 #else
300 #define ns16550_endboot NULL
301 #endif
303 static int ns16550_irq(struct serial_port *port)
304 {
305 struct ns16550 *uart = port->uart;
306 return ((uart->irq > 0) ? uart->irq : -1);
307 }
309 static struct uart_driver __read_mostly ns16550_driver = {
310 .init_preirq = ns16550_init_preirq,
311 .init_postirq = ns16550_init_postirq,
312 .endboot = ns16550_endboot,
313 .tx_empty = ns16550_tx_empty,
314 .putc = ns16550_putc,
315 .getc = ns16550_getc,
316 .irq = ns16550_irq
317 };
319 static int __init parse_parity_char(int c)
320 {
321 switch ( c )
322 {
323 case 'n':
324 return PARITY_NONE;
325 case 'o':
326 return PARITY_ODD;
327 case 'e':
328 return PARITY_EVEN;
329 case 'm':
330 return PARITY_MARK;
331 case 's':
332 return PARITY_SPACE;
333 }
334 return 0;
335 }
337 static int __init check_existence(struct ns16550 *uart)
338 {
339 unsigned char status, scratch, scratch2, scratch3;
341 /*
342 * We can't poke MMIO UARTs until they get I/O remapped later. Assume that
343 * if we're getting MMIO UARTs, the arch code knows what it's doing.
344 */
345 if ( uart->io_base >= 0x10000 )
346 return 1;
348 /*
349 * Do a simple existence test first; if we fail this,
350 * there's no point trying anything else.
351 */
352 scratch = ns_read_reg(uart, IER);
353 ns_write_reg(uart, IER, 0);
355 /*
356 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
357 * 16C754B) allow only to modify them if an EFR bit is set.
358 */
359 scratch2 = ns_read_reg(uart, IER) & 0x0f;
360 ns_write_reg(uart, IER, 0x0F);
361 scratch3 = ns_read_reg(uart, IER) & 0x0f;
362 ns_write_reg(uart, IER, scratch);
363 if ( (scratch2 != 0) || (scratch3 != 0x0F) )
364 return 0;
366 /*
367 * Check to see if a UART is really there.
368 * Use loopback test mode.
369 */
370 ns_write_reg(uart, MCR, MCR_LOOP | 0x0A);
371 status = ns_read_reg(uart, MSR) & 0xF0;
372 return (status == 0x90);
373 }
375 #define PARSE_ERR(_f, _a...) \
376 do { \
377 printk( "ERROR: " _f "\n" , ## _a ); \
378 return; \
379 } while ( 0 )
381 static void __init ns16550_parse_port_config(
382 struct ns16550 *uart, const char *conf)
383 {
384 int baud;
386 /* No user-specified configuration? */
387 if ( (conf == NULL) || (*conf == '\0') )
388 {
389 /* Some platforms may automatically probe the UART configuartion. */
390 if ( uart->baud != 0 )
391 goto config_parsed;
392 return;
393 }
395 if ( strncmp(conf, "auto", 4) == 0 )
396 {
397 uart->baud = BAUD_AUTO;
398 conf += 4;
399 }
400 else if ( (baud = simple_strtoul(conf, &conf, 10)) != 0 )
401 uart->baud = baud;
403 if ( *conf == '/')
404 {
405 conf++;
406 uart->clock_hz = simple_strtoul(conf, &conf, 0) << 4;
407 }
409 if ( *conf != ',' )
410 goto config_parsed;
411 conf++;
413 uart->data_bits = simple_strtoul(conf, &conf, 10);
415 uart->parity = parse_parity_char(*conf);
416 conf++;
418 uart->stop_bits = simple_strtoul(conf, &conf, 10);
420 if ( *conf == ',' )
421 {
422 conf++;
423 uart->io_base = simple_strtoul(conf, &conf, 0);
425 if ( *conf == ',' )
426 {
427 conf++;
428 uart->irq = simple_strtoul(conf, &conf, 10);
429 }
430 }
432 config_parsed:
433 /* Sanity checks. */
434 if ( (uart->baud != BAUD_AUTO) &&
435 ((uart->baud < 1200) || (uart->baud > 115200)) )
436 PARSE_ERR("Baud rate %d outside supported range.", uart->baud);
437 if ( (uart->data_bits < 5) || (uart->data_bits > 8) )
438 PARSE_ERR("%d data bits are unsupported.", uart->data_bits);
439 if ( (uart->stop_bits < 1) || (uart->stop_bits > 2) )
440 PARSE_ERR("%d stop bits are unsupported.", uart->stop_bits);
441 if ( uart->io_base == 0 )
442 PARSE_ERR("I/O base address must be specified.");
443 if ( !check_existence(uart) )
444 PARSE_ERR("16550-compatible serial UART not present");
446 /* Register with generic serial driver. */
447 serial_register_uart(uart - ns16550_com, &ns16550_driver, uart);
448 }
450 void __init ns16550_init(int index, struct ns16550_defaults *defaults)
451 {
452 struct ns16550 *uart;
454 if ( (index < 0) || (index > 1) )
455 return;
457 uart = &ns16550_com[index];
459 uart->baud = (defaults->baud ? :
460 console_has((index == 0) ? "com1" : "com2")
461 ? BAUD_AUTO : 0);
462 uart->clock_hz = UART_CLOCK_HZ;
463 uart->data_bits = defaults->data_bits;
464 uart->parity = parse_parity_char(defaults->parity);
465 uart->stop_bits = defaults->stop_bits;
466 uart->irq = defaults->irq;
467 uart->io_base = defaults->io_base;
469 ns16550_parse_port_config(uart, (index == 0) ? opt_com1 : opt_com2);
470 }
472 /*
473 * Local variables:
474 * mode: C
475 * c-set-style: "BSD"
476 * c-basic-offset: 4
477 * tab-width: 4
478 * indent-tabs-mode: nil
479 * End:
480 */