debuggers.hg

view xen/include/asm-x86/processor.h @ 21015:8cb6e7eff2ba

x86: Generalise BUGFRAME_dump mechanism to allow polled UART irq to
get proper regs argument.

Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Feb 24 10:44:30 2010 +0000 (2010-02-24)
parents 7c47306f59bf
children 6384675aa29a
line source
2 /* Portions are: Copyright (c) 1994 Linus Torvalds */
4 #ifndef __ASM_X86_PROCESSOR_H
5 #define __ASM_X86_PROCESSOR_H
7 #ifndef __ASSEMBLY__
8 #include <xen/config.h>
9 #include <xen/cache.h>
10 #include <xen/types.h>
11 #include <xen/smp.h>
12 #include <xen/percpu.h>
13 #include <public/xen.h>
14 #include <asm/types.h>
15 #include <asm/cpufeature.h>
16 #include <asm/desc.h>
17 #endif
19 /*
20 * CPU vendor IDs
21 */
22 #define X86_VENDOR_INTEL 0
23 #define X86_VENDOR_CYRIX 1
24 #define X86_VENDOR_AMD 2
25 #define X86_VENDOR_UMC 3
26 #define X86_VENDOR_NEXGEN 4
27 #define X86_VENDOR_CENTAUR 5
28 #define X86_VENDOR_RISE 6
29 #define X86_VENDOR_TRANSMETA 7
30 #define X86_VENDOR_NSC 8
31 #define X86_VENDOR_NUM 9
32 #define X86_VENDOR_UNKNOWN 0xff
34 /*
35 * EFLAGS bits
36 */
37 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
38 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
39 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
40 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
41 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
42 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
43 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
44 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
45 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
46 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
47 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
48 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
49 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
50 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
51 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
52 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
53 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
55 /*
56 * Intel CPU flags in CR0
57 */
58 #define X86_CR0_PE 0x00000001 /* Enable Protected Mode (RW) */
59 #define X86_CR0_MP 0x00000002 /* Monitor Coprocessor (RW) */
60 #define X86_CR0_EM 0x00000004 /* Require FPU Emulation (RO) */
61 #define X86_CR0_TS 0x00000008 /* Task Switched (RW) */
62 #define X86_CR0_ET 0x00000010 /* Extension type (RO) */
63 #define X86_CR0_NE 0x00000020 /* Numeric Error Reporting (RW) */
64 #define X86_CR0_WP 0x00010000 /* Supervisor Write Protect (RW) */
65 #define X86_CR0_AM 0x00040000 /* Alignment Checking (RW) */
66 #define X86_CR0_NW 0x20000000 /* Not Write-Through (RW) */
67 #define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */
68 #define X86_CR0_PG 0x80000000 /* Paging (RW) */
70 /*
71 * Intel CPU features in CR4
72 */
73 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
74 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
75 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
76 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
77 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
78 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
79 #define X86_CR4_MCE 0x0040 /* Machine check enable */
80 #define X86_CR4_PGE 0x0080 /* enable global pages */
81 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
82 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
83 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
84 #define X86_CR4_VMXE 0x2000 /* enable VMX */
85 #define X86_CR4_SMXE 0x4000 /* enable SMX */
86 #define X86_CR4_OSXSAVE 0x40000 /* enable XSAVE/XRSTOR */
88 /*
89 * Trap/fault mnemonics.
90 */
91 #define TRAP_divide_error 0
92 #define TRAP_debug 1
93 #define TRAP_nmi 2
94 #define TRAP_int3 3
95 #define TRAP_overflow 4
96 #define TRAP_bounds 5
97 #define TRAP_invalid_op 6
98 #define TRAP_no_device 7
99 #define TRAP_double_fault 8
100 #define TRAP_copro_seg 9
101 #define TRAP_invalid_tss 10
102 #define TRAP_no_segment 11
103 #define TRAP_stack_error 12
104 #define TRAP_gp_fault 13
105 #define TRAP_page_fault 14
106 #define TRAP_spurious_int 15
107 #define TRAP_copro_error 16
108 #define TRAP_alignment_check 17
109 #define TRAP_machine_check 18
110 #define TRAP_simd_error 19
112 /* Set for entry via SYSCALL. Informs return code to use SYSRETQ not IRETQ. */
113 /* NB. Same as VGCF_in_syscall. No bits in common with any other TRAP_ defn. */
114 #define TRAP_syscall 256
116 /* Boolean return code: the reason for a fault has been fixed. */
117 #define EXCRET_fault_fixed 1
119 /* 'trap_bounce' flags values */
120 #define TBF_EXCEPTION 1
121 #define TBF_EXCEPTION_ERRCODE 2
122 #define TBF_INTERRUPT 8
123 #define TBF_FAILSAFE 16
125 /* 'arch_vcpu' flags values */
126 #define _TF_kernel_mode 0
127 #define TF_kernel_mode (1<<_TF_kernel_mode)
129 /* #PF error code values. */
130 #define PFEC_page_present (1U<<0)
131 #define PFEC_write_access (1U<<1)
132 #define PFEC_user_mode (1U<<2)
133 #define PFEC_reserved_bit (1U<<3)
134 #define PFEC_insn_fetch (1U<<4)
135 #define PFEC_page_paged (1U<<5)
136 #define PFEC_page_shared (1U<<6)
138 #ifndef __ASSEMBLY__
140 struct domain;
141 struct vcpu;
143 /*
144 * Default implementation of macro that returns current
145 * instruction pointer ("program counter").
146 */
147 #ifdef __x86_64__
148 #define current_text_addr() ({ \
149 void *pc; \
150 asm ( "leaq 1f(%%rip),%0\n1:" : "=r" (pc) ); \
151 pc; \
152 })
153 #else
154 #define current_text_addr() ({ \
155 void *pc; \
156 asm ( "movl $1f,%0\n1:" : "=g" (pc) ); \
157 pc; \
158 })
159 #endif
161 struct cpuinfo_x86 {
162 __u8 x86; /* CPU family */
163 __u8 x86_vendor; /* CPU vendor */
164 __u8 x86_model;
165 __u8 x86_mask;
166 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
167 unsigned int x86_capability[NCAPINTS];
168 char x86_vendor_id[16];
169 char x86_model_id[64];
170 int x86_cache_size; /* in KB - valid for CPUS which support this call */
171 int x86_cache_alignment; /* In bytes */
172 int x86_power;
173 __u32 x86_max_cores; /* cpuid returned max cores value */
174 __u32 booted_cores; /* number of cores as seen by OS */
175 __u32 x86_num_siblings; /* cpuid logical cpus per chip value */
176 __u32 apicid;
177 unsigned short x86_clflush_size;
178 } __cacheline_aligned;
180 /*
181 * capabilities of CPUs
182 */
184 extern struct cpuinfo_x86 boot_cpu_data;
186 #ifdef CONFIG_SMP
187 extern struct cpuinfo_x86 cpu_data[];
188 #define current_cpu_data cpu_data[smp_processor_id()]
189 #else
190 #define cpu_data (&boot_cpu_data)
191 #define current_cpu_data boot_cpu_data
192 #endif
194 extern u64 host_pat;
195 extern int phys_proc_id[NR_CPUS];
196 extern int cpu_core_id[NR_CPUS];
198 extern void identify_cpu(struct cpuinfo_x86 *);
199 extern void setup_clear_cpu_cap(unsigned int);
200 extern void print_cpu_info(struct cpuinfo_x86 *);
201 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
202 extern void dodgy_tsc(void);
204 #ifdef CONFIG_X86_HT
205 extern void detect_ht(struct cpuinfo_x86 *c);
206 #else
207 static always_inline void detect_ht(struct cpuinfo_x86 *c) {}
208 #endif
210 #define cpu_to_core(_cpu) (cpu_core_id[_cpu])
211 #define cpu_to_socket(_cpu) (phys_proc_id[_cpu])
213 /*
214 * Generic CPUID function
215 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
216 * resulting in stale register contents being returned.
217 */
218 #define cpuid(_op,_eax,_ebx,_ecx,_edx) \
219 asm ( "cpuid" \
220 : "=a" (*(int *)(_eax)), \
221 "=b" (*(int *)(_ebx)), \
222 "=c" (*(int *)(_ecx)), \
223 "=d" (*(int *)(_edx)) \
224 : "0" (_op), "2" (0) )
226 /* Some CPUID calls want 'count' to be placed in ecx */
227 static inline void cpuid_count(
228 int op,
229 int count,
230 unsigned int *eax,
231 unsigned int *ebx,
232 unsigned int *ecx,
233 unsigned int *edx)
234 {
235 asm ( "cpuid"
236 : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
237 : "0" (op), "c" (count) );
238 }
240 /*
241 * CPUID functions returning a single datum
242 */
243 static always_inline unsigned int cpuid_eax(unsigned int op)
244 {
245 unsigned int eax;
247 asm ( "cpuid"
248 : "=a" (eax)
249 : "0" (op)
250 : "bx", "cx", "dx" );
251 return eax;
252 }
254 static always_inline unsigned int cpuid_ebx(unsigned int op)
255 {
256 unsigned int eax, ebx;
258 asm ( "cpuid"
259 : "=a" (eax), "=b" (ebx)
260 : "0" (op)
261 : "cx", "dx" );
262 return ebx;
263 }
265 static always_inline unsigned int cpuid_ecx(unsigned int op)
266 {
267 unsigned int eax, ecx;
269 asm ( "cpuid"
270 : "=a" (eax), "=c" (ecx)
271 : "0" (op)
272 : "bx", "dx" );
273 return ecx;
274 }
276 static always_inline unsigned int cpuid_edx(unsigned int op)
277 {
278 unsigned int eax, edx;
280 asm ( "cpuid"
281 : "=a" (eax), "=d" (edx)
282 : "0" (op)
283 : "bx", "cx" );
284 return edx;
285 }
287 static inline unsigned long read_cr0(void)
288 {
289 unsigned long cr0;
290 asm volatile ( "mov %%cr0,%0\n\t" : "=r" (cr0) );
291 return cr0;
292 }
294 static inline void write_cr0(unsigned long val)
295 {
296 asm volatile ( "mov %0,%%cr0" : : "r" ((unsigned long)val) );
297 }
299 static inline unsigned long read_cr2(void)
300 {
301 unsigned long cr2;
302 asm volatile ( "mov %%cr2,%0\n\t" : "=r" (cr2) );
303 return cr2;
304 }
306 DECLARE_PER_CPU(unsigned long, cr4);
308 static inline unsigned long read_cr4(void)
309 {
310 return this_cpu(cr4);
311 }
313 static inline void write_cr4(unsigned long val)
314 {
315 this_cpu(cr4) = val;
316 asm volatile ( "mov %0,%%cr4" : : "r" (val) );
317 }
319 /* Clear and set 'TS' bit respectively */
320 static inline void clts(void)
321 {
322 asm volatile ( "clts" );
323 }
325 static inline void stts(void)
326 {
327 write_cr0(X86_CR0_TS|read_cr0());
328 }
330 /*
331 * Save the cr4 feature set we're using (ie
332 * Pentium 4MB enable and PPro Global page
333 * enable), so that any CPU's that boot up
334 * after us can get the correct flags.
335 */
336 extern unsigned long mmu_cr4_features;
338 static always_inline void set_in_cr4 (unsigned long mask)
339 {
340 mmu_cr4_features |= mask;
341 write_cr4(read_cr4() | mask);
342 }
344 static always_inline void clear_in_cr4 (unsigned long mask)
345 {
346 mmu_cr4_features &= ~mask;
347 write_cr4(read_cr4() & ~mask);
348 }
350 /*
351 * NSC/Cyrix CPU configuration register indexes
352 */
354 #define CX86_PCR0 0x20
355 #define CX86_GCR 0xb8
356 #define CX86_CCR0 0xc0
357 #define CX86_CCR1 0xc1
358 #define CX86_CCR2 0xc2
359 #define CX86_CCR3 0xc3
360 #define CX86_CCR4 0xe8
361 #define CX86_CCR5 0xe9
362 #define CX86_CCR6 0xea
363 #define CX86_CCR7 0xeb
364 #define CX86_PCR1 0xf0
365 #define CX86_DIR0 0xfe
366 #define CX86_DIR1 0xff
367 #define CX86_ARR_BASE 0xc4
368 #define CX86_RCR_BASE 0xdc
370 /*
371 * NSC/Cyrix CPU indexed register access macros
372 */
374 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
376 #define setCx86(reg, data) do { \
377 outb((reg), 0x22); \
378 outb((data), 0x23); \
379 } while (0)
381 /* Stop speculative execution */
382 static inline void sync_core(void)
383 {
384 int tmp;
385 asm volatile (
386 "cpuid"
387 : "=a" (tmp)
388 : "0" (1)
389 : "ebx","ecx","edx","memory" );
390 }
392 static always_inline void __monitor(const void *eax, unsigned long ecx,
393 unsigned long edx)
394 {
395 /* "monitor %eax,%ecx,%edx;" */
396 asm volatile (
397 ".byte 0x0f,0x01,0xc8;"
398 : : "a" (eax), "c" (ecx), "d"(edx) );
399 }
401 static always_inline void __mwait(unsigned long eax, unsigned long ecx)
402 {
403 /* "mwait %eax,%ecx;" */
404 asm volatile (
405 ".byte 0x0f,0x01,0xc9;"
406 : : "a" (eax), "c" (ecx) );
407 }
409 #define IOBMP_BYTES 8192
410 #define IOBMP_INVALID_OFFSET 0x8000
412 struct tss_struct {
413 unsigned short back_link,__blh;
414 #ifdef __x86_64__
415 union { u64 rsp0, esp0; };
416 union { u64 rsp1, esp1; };
417 union { u64 rsp2, esp2; };
418 u64 reserved1;
419 u64 ist[7];
420 u64 reserved2;
421 u16 reserved3;
422 #else
423 u32 esp0;
424 u16 ss0,__ss0h;
425 u32 esp1;
426 u16 ss1,__ss1h;
427 u32 esp2;
428 u16 ss2,__ss2h;
429 u32 __cr3;
430 u32 eip;
431 u32 eflags;
432 u32 eax,ecx,edx,ebx;
433 u32 esp;
434 u32 ebp;
435 u32 esi;
436 u32 edi;
437 u16 es, __esh;
438 u16 cs, __csh;
439 u16 ss, __ssh;
440 u16 ds, __dsh;
441 u16 fs, __fsh;
442 u16 gs, __gsh;
443 u16 ldt, __ldth;
444 u16 trace;
445 #endif
446 u16 bitmap;
447 /* Pads the TSS to be cacheline-aligned (total size is 0x80). */
448 u8 __cacheline_filler[24];
449 } __cacheline_aligned __attribute__((packed));
451 #ifdef __x86_64__
452 # define IST_DF 1UL
453 # define IST_NMI 2UL
454 # define IST_MCE 3UL
455 # define IST_MAX 3UL
456 #endif
458 #define IDT_ENTRIES 256
459 extern idt_entry_t idt_table[];
460 extern idt_entry_t *idt_tables[];
462 DECLARE_PER_CPU(struct tss_struct, init_tss);
464 extern void init_int80_direct_trap(struct vcpu *v);
466 #if defined(CONFIG_X86_32)
468 #define set_int80_direct_trap(_ed) \
469 (memcpy(idt_tables[(_ed)->processor] + 0x80, \
470 &((_ed)->arch.int80_desc), 8))
472 #else
474 #define set_int80_direct_trap(_ed) ((void)0)
476 #endif
478 extern int gpf_emulate_4gb(struct cpu_user_regs *regs);
480 extern void write_ptbase(struct vcpu *v);
482 void destroy_gdt(struct vcpu *d);
483 long set_gdt(struct vcpu *d,
484 unsigned long *frames,
485 unsigned int entries);
487 #define write_debugreg(reg, val) do { \
488 unsigned long __val = val; \
489 asm volatile ( "mov %0,%%db" #reg : : "r" (__val) ); \
490 } while (0)
491 #define read_debugreg(reg) ({ \
492 unsigned long __val; \
493 asm volatile ( "mov %%db" #reg ",%0" : "=r" (__val) ); \
494 __val; \
495 })
496 long set_debugreg(struct vcpu *p, int reg, unsigned long value);
498 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
499 static always_inline void rep_nop(void)
500 {
501 asm volatile ( "rep;nop" : : : "memory" );
502 }
504 #define cpu_relax() rep_nop()
506 /* Prefetch instructions for Pentium III and AMD Athlon */
507 #ifdef CONFIG_MPENTIUMIII
509 #define ARCH_HAS_PREFETCH
510 extern always_inline void prefetch(const void *x)
511 {
512 asm volatile ( "prefetchnta (%0)" : : "r"(x) );
513 }
515 #elif CONFIG_X86_USE_3DNOW
517 #define ARCH_HAS_PREFETCH
518 #define ARCH_HAS_PREFETCHW
519 #define ARCH_HAS_SPINLOCK_PREFETCH
521 extern always_inline void prefetch(const void *x)
522 {
523 asm volatile ( "prefetch (%0)" : : "r"(x) );
524 }
526 extern always_inline void prefetchw(const void *x)
527 {
528 asm volatile ( "prefetchw (%0)" : : "r"(x) );
529 }
530 #define spin_lock_prefetch(x) prefetchw(x)
532 #endif
534 void show_stack(struct cpu_user_regs *regs);
535 void show_stack_overflow(unsigned int cpu, unsigned long esp);
536 void show_registers(struct cpu_user_regs *regs);
537 void show_execution_state(struct cpu_user_regs *regs);
538 #define dump_execution_state() run_in_exception_handler(show_execution_state)
539 void show_page_walk(unsigned long addr);
540 asmlinkage void fatal_trap(int trapnr, struct cpu_user_regs *regs);
542 #ifdef CONFIG_COMPAT
543 void compat_show_guest_stack(struct vcpu *, struct cpu_user_regs *, int lines);
544 #else
545 #define compat_show_guest_stack(vcpu, regs, lines) ((void)0)
546 #endif
548 extern void mtrr_ap_init(void);
549 extern void mtrr_bp_init(void);
551 void mcheck_init(struct cpuinfo_x86 *c);
552 asmlinkage void do_machine_check(struct cpu_user_regs *regs);
553 void cpu_mcheck_distribute_cmci(void);
554 void cpu_mcheck_disable(void);
556 int cpuid_hypervisor_leaves( uint32_t idx, uint32_t sub_idx,
557 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
558 int rdmsr_hypervisor_regs(uint32_t idx, uint64_t *val);
559 int wrmsr_hypervisor_regs(uint32_t idx, uint64_t val);
561 int microcode_update(XEN_GUEST_HANDLE(const_void), unsigned long len);
562 int microcode_resume_cpu(int cpu);
564 #endif /* !__ASSEMBLY__ */
566 #endif /* __ASM_X86_PROCESSOR_H */
568 /*
569 * Local variables:
570 * mode: C
571 * c-set-style: "BSD"
572 * c-basic-offset: 4
573 * tab-width: 4
574 * indent-tabs-mode: nil
575 * End:
576 */