debuggers.hg

view linux-2.6.10-rc2-xen-sparse/arch/xen/i386/kernel/cpu/common.c @ 3289:a169836882cb

bitkeeper revision 1.1159.170.59 (41b4c2fdJ2gj_BWy27Vj3ptayZp_yg)

sync w/ head.
author cl349@arcadians.cl.cam.ac.uk
date Mon Dec 06 20:37:17 2004 +0000 (2004-12-06)
parents 13728122c78d
children
line source
1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
4 #include <linux/smp.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <asm/semaphore.h>
8 #include <asm/processor.h>
9 #include <asm/i387.h>
10 #include <asm/msr.h>
11 #include <asm/io.h>
12 #include <asm/mmu_context.h>
13 #include <asm-xen/hypervisor.h>
15 #include "cpu.h"
17 DEFINE_PER_CPU(struct desc_struct, cpu_gdt_table[GDT_ENTRIES]);
18 EXPORT_PER_CPU_SYMBOL(cpu_gdt_table);
20 static int cachesize_override __initdata = -1;
21 static int disable_x86_fxsr __initdata = 0;
22 static int disable_x86_serial_nr __initdata = 1;
24 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
26 extern void mcheck_init(struct cpuinfo_x86 *c);
28 extern void machine_specific_modify_cpu_capabilities(struct cpuinfo_x86 *c);
30 extern int disable_pse;
32 static void default_init(struct cpuinfo_x86 * c)
33 {
34 /* Not much we can do here... */
35 /* Check if at least it has cpuid */
36 if (c->cpuid_level == -1) {
37 /* No cpuid. It must be an ancient CPU */
38 if (c->x86 == 4)
39 strcpy(c->x86_model_id, "486");
40 else if (c->x86 == 3)
41 strcpy(c->x86_model_id, "386");
42 }
43 }
45 static struct cpu_dev default_cpu = {
46 .c_init = default_init,
47 };
48 static struct cpu_dev * this_cpu = &default_cpu;
50 static int __init cachesize_setup(char *str)
51 {
52 get_option (&str, &cachesize_override);
53 return 1;
54 }
55 __setup("cachesize=", cachesize_setup);
57 int __init get_model_name(struct cpuinfo_x86 *c)
58 {
59 unsigned int *v;
60 char *p, *q;
62 if (cpuid_eax(0x80000000) < 0x80000004)
63 return 0;
65 v = (unsigned int *) c->x86_model_id;
66 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
67 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
68 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
69 c->x86_model_id[48] = 0;
71 /* Intel chips right-justify this string for some dumb reason;
72 undo that brain damage */
73 p = q = &c->x86_model_id[0];
74 while ( *p == ' ' )
75 p++;
76 if ( p != q ) {
77 while ( *p )
78 *q++ = *p++;
79 while ( q <= &c->x86_model_id[48] )
80 *q++ = '\0'; /* Zero-pad the rest */
81 }
83 return 1;
84 }
87 void __init display_cacheinfo(struct cpuinfo_x86 *c)
88 {
89 unsigned int n, dummy, ecx, edx, l2size;
91 n = cpuid_eax(0x80000000);
93 if (n >= 0x80000005) {
94 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
95 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
96 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
97 c->x86_cache_size=(ecx>>24)+(edx>>24);
98 }
100 if (n < 0x80000006) /* Some chips just has a large L1. */
101 return;
103 ecx = cpuid_ecx(0x80000006);
104 l2size = ecx >> 16;
106 /* do processor-specific cache resizing */
107 if (this_cpu->c_size_cache)
108 l2size = this_cpu->c_size_cache(c,l2size);
110 /* Allow user to override all this if necessary. */
111 if (cachesize_override != -1)
112 l2size = cachesize_override;
114 if ( l2size == 0 )
115 return; /* Again, no L2 cache is possible */
117 c->x86_cache_size = l2size;
119 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
120 l2size, ecx & 0xFF);
121 }
123 /* Naming convention should be: <Name> [(<Codename>)] */
124 /* This table only is used unless init_<vendor>() below doesn't set it; */
125 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
127 /* Look up CPU names by table lookup. */
128 static char __init *table_lookup_model(struct cpuinfo_x86 *c)
129 {
130 struct cpu_model_info *info;
132 if ( c->x86_model >= 16 )
133 return NULL; /* Range check */
135 if (!this_cpu)
136 return NULL;
138 info = this_cpu->c_models;
140 while (info && info->family) {
141 if (info->family == c->x86)
142 return info->model_names[c->x86_model];
143 info++;
144 }
145 return NULL; /* Not found */
146 }
149 void __init get_cpu_vendor(struct cpuinfo_x86 *c, int early)
150 {
151 char *v = c->x86_vendor_id;
152 int i;
154 for (i = 0; i < X86_VENDOR_NUM; i++) {
155 if (cpu_devs[i]) {
156 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
157 (cpu_devs[i]->c_ident[1] &&
158 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
159 c->x86_vendor = i;
160 if (!early)
161 this_cpu = cpu_devs[i];
162 break;
163 }
164 }
165 }
166 }
169 static int __init x86_fxsr_setup(char * s)
170 {
171 disable_x86_fxsr = 1;
172 return 1;
173 }
174 __setup("nofxsr", x86_fxsr_setup);
177 /* Standard macro to see if a specific flag is changeable */
178 static inline int flag_is_changeable_p(u32 flag)
179 {
180 u32 f1, f2;
182 asm("pushfl\n\t"
183 "pushfl\n\t"
184 "popl %0\n\t"
185 "movl %0,%1\n\t"
186 "xorl %2,%0\n\t"
187 "pushl %0\n\t"
188 "popfl\n\t"
189 "pushfl\n\t"
190 "popl %0\n\t"
191 "popfl\n\t"
192 : "=&r" (f1), "=&r" (f2)
193 : "ir" (flag));
195 return ((f1^f2) & flag) != 0;
196 }
199 /* Probe for the CPUID instruction */
200 int __init have_cpuid_p(void)
201 {
202 return flag_is_changeable_p(X86_EFLAGS_ID);
203 }
205 /* Do minimum CPU detection early.
206 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
207 The others are not touched to avoid unwanted side effects. */
208 void __init early_cpu_detect(void)
209 {
210 struct cpuinfo_x86 *c = &boot_cpu_data;
212 c->x86_cache_alignment = 32;
214 if (!have_cpuid_p())
215 return;
217 /* Get vendor name */
218 cpuid(0x00000000, &c->cpuid_level,
219 (int *)&c->x86_vendor_id[0],
220 (int *)&c->x86_vendor_id[8],
221 (int *)&c->x86_vendor_id[4]);
223 get_cpu_vendor(c, 1);
225 c->x86 = 4;
226 if (c->cpuid_level >= 0x00000001) {
227 u32 junk, tfms, cap0, misc;
228 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
229 c->x86 = (tfms >> 8) & 15;
230 c->x86_model = (tfms >> 4) & 15;
231 if (c->x86 == 0xf) {
232 c->x86 += (tfms >> 20) & 0xff;
233 c->x86_model += ((tfms >> 16) & 0xF) << 4;
234 }
235 c->x86_mask = tfms & 15;
236 if (cap0 & (1<<19))
237 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
238 }
240 early_intel_workaround(c);
241 }
243 void __init generic_identify(struct cpuinfo_x86 * c)
244 {
245 u32 tfms, xlvl;
246 int junk;
248 if (have_cpuid_p()) {
249 /* Get vendor name */
250 cpuid(0x00000000, &c->cpuid_level,
251 (int *)&c->x86_vendor_id[0],
252 (int *)&c->x86_vendor_id[8],
253 (int *)&c->x86_vendor_id[4]);
255 get_cpu_vendor(c, 0);
256 /* Initialize the standard set of capabilities */
257 /* Note that the vendor-specific code below might override */
259 /* Intel-defined flags: level 0x00000001 */
260 if ( c->cpuid_level >= 0x00000001 ) {
261 u32 capability, excap;
262 cpuid(0x00000001, &tfms, &junk, &excap, &capability);
263 c->x86_capability[0] = capability;
264 c->x86_capability[4] = excap;
265 c->x86 = (tfms >> 8) & 15;
266 c->x86_model = (tfms >> 4) & 15;
267 if (c->x86 == 0xf) {
268 c->x86 += (tfms >> 20) & 0xff;
269 c->x86_model += ((tfms >> 16) & 0xF) << 4;
270 }
271 c->x86_mask = tfms & 15;
272 } else {
273 /* Have CPUID level 0 only - unheard of */
274 c->x86 = 4;
275 }
277 /* AMD-defined flags: level 0x80000001 */
278 xlvl = cpuid_eax(0x80000000);
279 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
280 if ( xlvl >= 0x80000001 )
281 c->x86_capability[1] = cpuid_edx(0x80000001);
282 if ( xlvl >= 0x80000004 )
283 get_model_name(c); /* Default name */
284 }
285 }
286 }
288 static void __init squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
289 {
290 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
291 /* Disable processor serial number */
292 unsigned long lo,hi;
293 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
294 lo |= 0x200000;
295 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
296 printk(KERN_NOTICE "CPU serial number disabled.\n");
297 clear_bit(X86_FEATURE_PN, c->x86_capability);
299 /* Disabling the serial number may affect the cpuid level */
300 c->cpuid_level = cpuid_eax(0);
301 }
302 }
304 static int __init x86_serial_nr_setup(char *s)
305 {
306 disable_x86_serial_nr = 0;
307 return 1;
308 }
309 __setup("serialnumber", x86_serial_nr_setup);
313 /*
314 * This does the hard work of actually picking apart the CPU stuff...
315 */
316 void __init identify_cpu(struct cpuinfo_x86 *c)
317 {
318 int i;
320 c->loops_per_jiffy = loops_per_jiffy;
321 c->x86_cache_size = -1;
322 c->x86_vendor = X86_VENDOR_UNKNOWN;
323 c->cpuid_level = -1; /* CPUID not detected */
324 c->x86_model = c->x86_mask = 0; /* So far unknown... */
325 c->x86_vendor_id[0] = '\0'; /* Unset */
326 c->x86_model_id[0] = '\0'; /* Unset */
327 memset(&c->x86_capability, 0, sizeof c->x86_capability);
329 if (!have_cpuid_p()) {
330 /* First of all, decide if this is a 486 or higher */
331 /* It's a 486 if we can modify the AC flag */
332 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
333 c->x86 = 4;
334 else
335 c->x86 = 3;
336 }
338 generic_identify(c);
340 printk(KERN_DEBUG "CPU: After generic identify, caps: %08lx %08lx %08lx %08lx\n",
341 c->x86_capability[0],
342 c->x86_capability[1],
343 c->x86_capability[2],
344 c->x86_capability[3]);
346 if (this_cpu->c_identify) {
347 this_cpu->c_identify(c);
349 printk(KERN_DEBUG "CPU: After vendor identify, caps: %08lx %08lx %08lx %08lx\n",
350 c->x86_capability[0],
351 c->x86_capability[1],
352 c->x86_capability[2],
353 c->x86_capability[3]);
354 }
356 /*
357 * Vendor-specific initialization. In this section we
358 * canonicalize the feature flags, meaning if there are
359 * features a certain CPU supports which CPUID doesn't
360 * tell us, CPUID claiming incorrect flags, or other bugs,
361 * we handle them here.
362 *
363 * At the end of this section, c->x86_capability better
364 * indicate the features this CPU genuinely supports!
365 */
366 if (this_cpu->c_init)
367 this_cpu->c_init(c);
369 /* Disable the PN if appropriate */
370 squash_the_stupid_serial_number(c);
372 /*
373 * The vendor-specific functions might have changed features. Now
374 * we do "generic changes."
375 */
377 /* TSC disabled? */
378 if ( tsc_disable )
379 clear_bit(X86_FEATURE_TSC, c->x86_capability);
381 /* FXSR disabled? */
382 if (disable_x86_fxsr) {
383 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
384 clear_bit(X86_FEATURE_XMM, c->x86_capability);
385 }
387 if (disable_pse)
388 clear_bit(X86_FEATURE_PSE, c->x86_capability);
390 /* If the model name is still unset, do table lookup. */
391 if ( !c->x86_model_id[0] ) {
392 char *p;
393 p = table_lookup_model(c);
394 if ( p )
395 strcpy(c->x86_model_id, p);
396 else
397 /* Last resort... */
398 sprintf(c->x86_model_id, "%02x/%02x",
399 c->x86_vendor, c->x86_model);
400 }
402 machine_specific_modify_cpu_capabilities(c);
404 /* Now the feature flags better reflect actual CPU features! */
406 printk(KERN_DEBUG "CPU: After all inits, caps: %08lx %08lx %08lx %08lx\n",
407 c->x86_capability[0],
408 c->x86_capability[1],
409 c->x86_capability[2],
410 c->x86_capability[3]);
412 /*
413 * On SMP, boot_cpu_data holds the common feature set between
414 * all CPUs; so make sure that we indicate which features are
415 * common between the CPUs. The first time this routine gets
416 * executed, c == &boot_cpu_data.
417 */
418 if ( c != &boot_cpu_data ) {
419 /* AND the already accumulated flags with these */
420 for ( i = 0 ; i < NCAPINTS ; i++ )
421 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
422 }
424 /* Init Machine Check Exception if available. */
425 #ifdef CONFIG_X86_MCE
426 mcheck_init(c);
427 #endif
428 }
429 /*
430 * Perform early boot up checks for a valid TSC. See arch/i386/kernel/time.c
431 */
433 void __init dodgy_tsc(void)
434 {
435 if (( boot_cpu_data.x86_vendor == X86_VENDOR_CYRIX ) ||
436 ( boot_cpu_data.x86_vendor == X86_VENDOR_NSC ))
437 cpu_devs[X86_VENDOR_CYRIX]->c_init(&boot_cpu_data);
438 }
440 void __init print_cpu_info(struct cpuinfo_x86 *c)
441 {
442 char *vendor = NULL;
444 if (c->x86_vendor < X86_VENDOR_NUM)
445 vendor = this_cpu->c_vendor;
446 else if (c->cpuid_level >= 0)
447 vendor = c->x86_vendor_id;
449 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
450 printk("%s ", vendor);
452 if (!c->x86_model_id[0])
453 printk("%d86", c->x86);
454 else
455 printk("%s", c->x86_model_id);
457 if (c->x86_mask || c->cpuid_level >= 0)
458 printk(" stepping %02x\n", c->x86_mask);
459 else
460 printk("\n");
461 }
463 unsigned long cpu_initialized __initdata = 0;
465 /* This is hacky. :)
466 * We're emulating future behavior.
467 * In the future, the cpu-specific init functions will be called implicitly
468 * via the magic of initcalls.
469 * They will insert themselves into the cpu_devs structure.
470 * Then, when cpu_init() is called, we can just iterate over that array.
471 */
473 extern int intel_cpu_init(void);
474 extern int cyrix_init_cpu(void);
475 extern int nsc_init_cpu(void);
476 extern int amd_init_cpu(void);
477 extern int centaur_init_cpu(void);
478 extern int transmeta_init_cpu(void);
479 extern int rise_init_cpu(void);
480 extern int nexgen_init_cpu(void);
481 extern int umc_init_cpu(void);
482 void early_cpu_detect(void);
484 void __init early_cpu_init(void)
485 {
486 intel_cpu_init();
487 cyrix_init_cpu();
488 nsc_init_cpu();
489 amd_init_cpu();
490 centaur_init_cpu();
491 transmeta_init_cpu();
492 rise_init_cpu();
493 nexgen_init_cpu();
494 umc_init_cpu();
495 early_cpu_detect();
497 #ifdef CONFIG_DEBUG_PAGEALLOC
498 /* pse is not compatible with on-the-fly unmapping,
499 * disable it even if the cpus claim to support it.
500 */
501 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
502 disable_pse = 1;
503 #endif
504 }
506 void __init cpu_gdt_init(struct Xgt_desc_struct *gdt_descr)
507 {
508 unsigned long frames[gdt_descr->size >> PAGE_SHIFT];
509 unsigned long va;
510 int f;
512 for (va = gdt_descr->address, f = 0;
513 va < gdt_descr->address + gdt_descr->size;
514 va += PAGE_SIZE, f++) {
515 frames[f] = virt_to_machine(va) >> PAGE_SHIFT;
516 make_page_readonly((void *)va);
517 }
518 flush_page_update_queue();
519 if (HYPERVISOR_set_gdt(frames, gdt_descr->size / 8))
520 BUG();
521 lgdt_finish();
522 }
524 /*
525 * cpu_init() initializes state that is per-CPU. Some data is already
526 * initialized (naturally) in the bootstrap process, such as the GDT
527 * and IDT. We reload them nevertheless, this function acts as a
528 * 'CPU state barrier', nothing should get across.
529 */
530 void __init cpu_init (void)
531 {
532 int cpu = smp_processor_id();
533 struct tss_struct * t = &per_cpu(init_tss, cpu);
534 struct thread_struct *thread = &current->thread;
536 if (test_and_set_bit(cpu, &cpu_initialized)) {
537 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
538 for (;;) local_irq_enable();
539 }
540 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
542 if (cpu_has_vme || cpu_has_de)
543 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
544 if (tsc_disable && cpu_has_tsc) {
545 printk(KERN_NOTICE "Disabling TSC...\n");
546 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
547 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
548 set_in_cr4(X86_CR4_TSD);
549 }
551 /*
552 * Initialize the per-CPU GDT with the boot GDT,
553 * and set up the GDT descriptor:
554 */
555 if (cpu) {
556 cpu_gdt_descr[cpu].size = GDT_SIZE;
557 cpu_gdt_descr[cpu].address = 0; /* XXXcl alloc page */
558 BUG(); /* XXXcl SMP */
559 memcpy((void *)cpu_gdt_descr[cpu].address,
560 (void *)cpu_gdt_descr[0].address, GDT_SIZE);
561 }
562 /*
563 * Set up the per-thread TLS descriptor cache:
564 */
565 memcpy(thread->tls_array, &get_cpu_gdt_table(cpu)[GDT_ENTRY_TLS_MIN],
566 GDT_ENTRY_TLS_ENTRIES * 8);
568 cpu_gdt_init(&cpu_gdt_descr[cpu]);
570 /*
571 * Delete NT
572 */
573 __asm__("pushfl ; andl $0xffffbfff,(%esp) ; popfl");
575 /*
576 * Set up and load the per-CPU TSS and LDT
577 */
578 atomic_inc(&init_mm.mm_count);
579 current->active_mm = &init_mm;
580 if (current->mm)
581 BUG();
582 enter_lazy_tlb(&init_mm, current);
584 load_esp0(t, thread);
586 load_LDT(&init_mm.context);
587 flush_page_update_queue();
589 /* Clear %fs and %gs. */
590 asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
592 /* Clear all 6 debug registers: */
594 #define CD(register) HYPERVISOR_set_debugreg(register, 0)
596 CD(0); CD(1); CD(2); CD(3); /* no db4 and db5 */; CD(6); CD(7);
598 #undef CD
600 /*
601 * Force FPU initialization:
602 */
603 current_thread_info()->status = 0;
604 current->used_math = 0;
605 mxcsr_feature_mask_init();
606 }