debuggers.hg

view xen/include/asm-x86/processor.h @ 3657:a4b03d935138

bitkeeper revision 1.1159.238.7 (4200f09cegOci_6ijw2B4UT2y9odbA)

Enforce alignment of i387 data
Signed-off-by: ian.pratt@cl.cam.ac.uk
author iap10@labyrinth.cl.cam.ac.uk
date Wed Feb 02 15:24:12 2005 +0000 (2005-02-02)
parents ed902e5c4b49
children 0ef6e8e6e85d
line source
1 /*
2 * include/asm-x86/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
7 #ifndef __ASM_X86_PROCESSOR_H
8 #define __ASM_X86_PROCESSOR_H
10 #ifndef __ASSEMBLY__
11 #include <asm/page.h>
12 #include <asm/types.h>
13 #include <asm/cpufeature.h>
14 #include <asm/desc.h>
15 #include <asm/flushtlb.h>
16 #include <asm/pdb.h>
17 #include <xen/config.h>
18 #include <xen/spinlock.h>
19 #include <xen/cache.h>
20 #include <asm/vmx_vmcs.h>
21 #include <public/xen.h>
22 #endif
24 /*
25 * CPU vendor IDs
26 */
27 #define X86_VENDOR_INTEL 0
28 #define X86_VENDOR_CYRIX 1
29 #define X86_VENDOR_AMD 2
30 #define X86_VENDOR_UMC 3
31 #define X86_VENDOR_NEXGEN 4
32 #define X86_VENDOR_CENTAUR 5
33 #define X86_VENDOR_RISE 6
34 #define X86_VENDOR_TRANSMETA 7
35 #define X86_VENDOR_NSC 8
36 #define X86_VENDOR_SIS 9
37 #define X86_VENDOR_NUM 10
38 #define X86_VENDOR_UNKNOWN 0xff
40 /*
41 * EFLAGS bits
42 */
43 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
44 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
45 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
46 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
47 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
48 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
49 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
50 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
51 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
52 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
53 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
54 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
55 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
56 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
57 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
58 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
59 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
61 /*
62 * Intel CPU flags in CR0
63 */
64 #define X86_CR0_PE 0x00000001 /* Enable Protected Mode (RW) */
65 #define X86_CR0_MP 0x00000002 /* Monitor Coprocessor (RW) */
66 #define X86_CR0_EM 0x00000004 /* Require FPU Emulation (RO) */
67 #define X86_CR0_TS 0x00000008 /* Task Switched (RW) */
68 #define X86_CR0_NE 0x00000020 /* Numeric Error Reporting (RW) */
69 #define X86_CR0_WP 0x00010000 /* Supervisor Write Protect (RW) */
70 #define X86_CR0_AM 0x00040000 /* Alignment Checking (RW) */
71 #define X86_CR0_NW 0x20000000 /* Not Write-Through (RW) */
72 #define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */
73 #define X86_CR0_PG 0x80000000 /* Paging (RW) */
75 /*
76 * Intel CPU features in CR4
77 */
78 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
79 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
80 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
81 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
82 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
83 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
84 #define X86_CR4_MCE 0x0040 /* Machine check enable */
85 #define X86_CR4_PGE 0x0080 /* enable global pages */
86 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
87 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
88 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
89 #define X86_CR4_VMXE 0x2000 /* enable VMX */
91 /*
92 * Trap/fault mnemonics.
93 */
94 #define TRAP_divide_error 0
95 #define TRAP_debug 1
96 #define TRAP_nmi 2
97 #define TRAP_int3 3
98 #define TRAP_overflow 4
99 #define TRAP_bounds 5
100 #define TRAP_invalid_op 6
101 #define TRAP_no_device 7
102 #define TRAP_double_fault 8
103 #define TRAP_copro_seg 9
104 #define TRAP_invalid_tss 10
105 #define TRAP_no_segment 11
106 #define TRAP_stack_error 12
107 #define TRAP_gp_fault 13
108 #define TRAP_page_fault 14
109 #define TRAP_spurious_int 15
110 #define TRAP_copro_error 16
111 #define TRAP_alignment_check 17
112 #define TRAP_machine_check 18
113 #define TRAP_simd_error 19
114 #define TRAP_deferred_nmi 31
116 /*
117 * Non-fatal fault/trap handlers return an error code to the caller. If the
118 * code is non-zero, it means that either the exception was not due to a fault
119 * (i.e., it was a trap) or that the fault has been fixed up so the instruction
120 * replay ought to succeed.
121 */
122 #define EXCRET_not_a_fault 1 /* It was a trap. No instruction replay needed. */
123 #define EXCRET_fault_fixed 1 /* It was fault that we fixed: try a replay. */
125 /*
126 * 'trap_bounce' flags values.
127 */
128 #define TBF_EXCEPTION 1
129 #define TBF_EXCEPTION_ERRCODE 2
130 #define TBF_EXCEPTION_CR2 4
131 #define TBF_INTERRUPT 8
132 #define TBF_FAILSAFE 16
134 /*
135 * thread.flags values.
136 */
137 #define TF_failsafe_return 1
139 #ifndef __ASSEMBLY__
141 struct domain;
142 struct exec_domain;
144 /*
145 * Default implementation of macro that returns current
146 * instruction pointer ("program counter").
147 */
148 #ifdef __x86_64__
149 #define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })
150 #else
151 #define current_text_addr() \
152 ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
153 #endif
155 /*
156 * CPU type and hardware bug flags. Kept separately for each CPU.
157 * Members of this structure are referenced in head.S, so think twice
158 * before touching them. [mj]
159 */
161 struct cpuinfo_x86 {
162 __u8 x86; /* CPU family */
163 __u8 x86_vendor; /* CPU vendor */
164 __u8 x86_model;
165 __u8 x86_mask;
166 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
167 __u32 x86_capability[NCAPINTS];
168 char x86_vendor_id[16];
169 int x86_cache_size; /* in KB - for CPUS that support this call */
170 int x86_clflush_size;
171 int x86_tlbsize; /* number of 4K pages in DTLB/ITLB combined */
172 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
174 /*
175 * capabilities of CPUs
176 */
178 extern struct cpuinfo_x86 boot_cpu_data;
179 extern struct tss_struct init_tss[NR_CPUS];
181 #ifdef CONFIG_SMP
182 extern struct cpuinfo_x86 cpu_data[];
183 #define current_cpu_data cpu_data[smp_processor_id()]
184 #else
185 #define cpu_data (&boot_cpu_data)
186 #define current_cpu_data boot_cpu_data
187 #endif
189 extern char ignore_irq13;
191 extern void identify_cpu(struct cpuinfo_x86 *);
192 extern void print_cpu_info(struct cpuinfo_x86 *);
193 extern void dodgy_tsc(void);
195 /*
196 * Generic CPUID function
197 */
198 static inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
199 {
200 __asm__("cpuid"
201 : "=a" (*eax),
202 "=b" (*ebx),
203 "=c" (*ecx),
204 "=d" (*edx)
205 : "0" (op));
206 }
208 /*
209 * CPUID functions returning a single datum
210 */
211 static inline unsigned int cpuid_eax(unsigned int op)
212 {
213 unsigned int eax;
215 __asm__("cpuid"
216 : "=a" (eax)
217 : "0" (op)
218 : "bx", "cx", "dx");
219 return eax;
220 }
221 static inline unsigned int cpuid_ebx(unsigned int op)
222 {
223 unsigned int eax, ebx;
225 __asm__("cpuid"
226 : "=a" (eax), "=b" (ebx)
227 : "0" (op)
228 : "cx", "dx" );
229 return ebx;
230 }
231 static inline unsigned int cpuid_ecx(unsigned int op)
232 {
233 unsigned int eax, ecx;
235 __asm__("cpuid"
236 : "=a" (eax), "=c" (ecx)
237 : "0" (op)
238 : "bx", "dx" );
239 return ecx;
240 }
241 static inline unsigned int cpuid_edx(unsigned int op)
242 {
243 unsigned int eax, edx;
245 __asm__("cpuid"
246 : "=a" (eax), "=d" (edx)
247 : "0" (op)
248 : "bx", "cx");
249 return edx;
250 }
253 #define read_cr0() ({ \
254 unsigned long __dummy; \
255 __asm__( \
256 "mov"__OS" %%cr0,%0\n\t" \
257 :"=r" (__dummy)); \
258 __dummy; \
259 })
261 #define write_cr0(x) \
262 __asm__("mov"__OS" %0,%%cr0": :"r" ((unsigned long)x));
264 #define read_cr4() ({ \
265 unsigned long __dummy; \
266 __asm__( \
267 "mov"__OS" %%cr4,%0\n\t" \
268 :"=r" (__dummy)); \
269 __dummy; \
270 })
272 #define write_cr4(x) \
273 __asm__("mov"__OS" %0,%%cr4": :"r" ((unsigned long)x));
275 /*
276 * Save the cr4 feature set we're using (ie
277 * Pentium 4MB enable and PPro Global page
278 * enable), so that any CPU's that boot up
279 * after us can get the correct flags.
280 */
281 extern unsigned long mmu_cr4_features;
283 static inline void set_in_cr4 (unsigned long mask)
284 {
285 mmu_cr4_features |= mask;
286 __asm__("mov"__OS" %%cr4,%%"__OP"ax\n\t"
287 "or"__OS" %0,%%"__OP"ax\n\t"
288 "mov"__OS" %%"__OP"ax,%%cr4\n"
289 : : "irg" (mask)
290 :"ax");
291 }
293 static inline void clear_in_cr4 (unsigned long mask)
294 {
295 mmu_cr4_features &= ~mask;
296 __asm__("mov"__OS" %%cr4,%%"__OP"ax\n\t"
297 "and"__OS" %0,%%"__OP"ax\n\t"
298 "mov"__OS" %%"__OP"ax,%%cr4\n"
299 : : "irg" (~mask)
300 :"ax");
301 }
303 /*
304 * NSC/Cyrix CPU configuration register indexes
305 */
307 #define CX86_PCR0 0x20
308 #define CX86_GCR 0xb8
309 #define CX86_CCR0 0xc0
310 #define CX86_CCR1 0xc1
311 #define CX86_CCR2 0xc2
312 #define CX86_CCR3 0xc3
313 #define CX86_CCR4 0xe8
314 #define CX86_CCR5 0xe9
315 #define CX86_CCR6 0xea
316 #define CX86_CCR7 0xeb
317 #define CX86_PCR1 0xf0
318 #define CX86_DIR0 0xfe
319 #define CX86_DIR1 0xff
320 #define CX86_ARR_BASE 0xc4
321 #define CX86_RCR_BASE 0xdc
323 /*
324 * NSC/Cyrix CPU indexed register access macros
325 */
327 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
329 #define setCx86(reg, data) do { \
330 outb((reg), 0x22); \
331 outb((data), 0x23); \
332 } while (0)
334 #define IOBMP_BYTES 8192
335 #define IOBMP_BYTES_PER_SELBIT (IOBMP_BYTES / 64)
336 #define IOBMP_BITS_PER_SELBIT (IOBMP_BYTES_PER_SELBIT * 8)
337 #define IOBMP_OFFSET offsetof(struct tss_struct, io_bitmap)
338 #define IOBMP_INVALID_OFFSET 0x8000
340 struct i387_state {
341 u8 state[512]; /* big enough for FXSAVE */
342 } __attribute__ ((aligned (16)));
344 struct tss_struct {
345 unsigned short back_link,__blh;
346 #ifdef __x86_64__
347 u64 rsp0;
348 u64 rsp1;
349 u64 rsp2;
350 u64 reserved1;
351 u64 ist[7];
352 u64 reserved2;
353 u16 reserved3;
354 #else
355 u32 esp0;
356 u16 ss0,__ss0h;
357 u32 esp1;
358 u16 ss1,__ss1h;
359 u32 esp2;
360 u16 ss2,__ss2h;
361 u32 __cr3;
362 u32 eip;
363 u32 eflags;
364 u32 eax,ecx,edx,ebx;
365 u32 esp;
366 u32 ebp;
367 u32 esi;
368 u32 edi;
369 u16 es, __esh;
370 u16 cs, __csh;
371 u16 ss, __ssh;
372 u16 ds, __dsh;
373 u16 fs, __fsh;
374 u16 gs, __gsh;
375 u16 ldt, __ldth;
376 u16 trace;
377 #endif
378 u16 bitmap;
379 u8 io_bitmap[IOBMP_BYTES+1];
380 /* Pads the TSS to be cacheline-aligned (total size is 0x2080). */
381 u8 __cacheline_filler[23];
382 };
384 struct trap_bounce {
385 unsigned long error_code;
386 unsigned long cr2;
387 unsigned short flags; /* TBF_ */
388 unsigned short cs;
389 unsigned long eip;
390 };
392 struct thread_struct {
393 unsigned long guestos_sp;
394 unsigned long guestos_ss;
396 unsigned long flags; /* TF_ */
398 /* Hardware debugging registers */
399 unsigned long debugreg[8]; /* %%db0-7 debug registers */
401 /* floating point info */
402 struct i387_state i387;
404 /* general user-visible register state */
405 execution_context_t user_ctxt;
407 void (*schedule_tail) (struct exec_domain *);
409 /*
410 * Return vectors pushed to us by guest OS.
411 * The stack frame for events is exactly that of an x86 hardware interrupt.
412 * The stack frame for a failsafe callback is augmented with saved values
413 * for segment registers %ds, %es, %fs and %gs:
414 * %ds, %es, %fs, %gs, %eip, %cs, %eflags [, %oldesp, %oldss]
415 */
416 unsigned long event_selector; /* entry CS */
417 unsigned long event_address; /* entry EIP */
419 unsigned long failsafe_selector; /* entry CS */
420 unsigned long failsafe_address; /* entry EIP */
422 /* Bounce information for propagating an exception to guest OS. */
423 struct trap_bounce trap_bounce;
425 /* I/O-port access bitmap. */
426 u64 io_bitmap_sel; /* Selector to tell us which part of the IO bitmap are
427 * "interesting" (i.e. have clear bits) */
428 u8 *io_bitmap; /* Pointer to task's IO bitmap or NULL */
430 /* Trap info. */
431 #ifdef __i386__
432 int fast_trap_idx;
433 struct desc_struct fast_trap_desc;
434 #endif
435 trap_info_t traps[256];
436 #ifdef CONFIG_VMX
437 struct arch_vmx_struct arch_vmx; /* Virtual Machine Extensions */
438 #endif
439 } __cacheline_aligned;
441 #define IDT_ENTRIES 256
442 extern idt_entry_t idt_table[];
443 extern idt_entry_t *idt_tables[];
445 #if defined(__i386__)
447 #define SET_DEFAULT_FAST_TRAP(_p) \
448 (_p)->fast_trap_idx = 0x20; \
449 (_p)->fast_trap_desc.a = 0; \
450 (_p)->fast_trap_desc.b = 0;
452 #define CLEAR_FAST_TRAP(_p) \
453 (memset(idt_tables[smp_processor_id()] + (_p)->fast_trap_idx, \
454 0, 8))
456 #ifdef XEN_DEBUGGER
457 #define SET_FAST_TRAP(_p) \
458 (pdb_initialized ? (void *) 0 : \
459 (memcpy(idt_tables[smp_processor_id()] + (_p)->fast_trap_idx, \
460 &((_p)->fast_trap_desc), 8)))
461 #else
462 #define SET_FAST_TRAP(_p) \
463 (memcpy(idt_tables[smp_processor_id()] + (_p)->fast_trap_idx, \
464 &((_p)->fast_trap_desc), 8))
465 #endif
467 long set_fast_trap(struct exec_domain *p, int idx);
469 #endif
471 #define INIT_THREAD { 0 }
473 extern int gpf_emulate_4gb(struct xen_regs *regs);
475 struct mm_struct {
476 /*
477 * Every domain has a L1 pagetable of its own. Per-domain mappings
478 * are put in this table (eg. the current GDT is mapped here).
479 */
480 l1_pgentry_t *perdomain_ptes;
481 pagetable_t pagetable;
483 pagetable_t monitor_table;
484 l2_pgentry_t *vpagetable; /* virtual address of pagetable */
485 l2_pgentry_t *shadow_vtable; /* virtual address of shadow_table */
486 l2_pgentry_t *guest_pl2e_cache; /* guest page directory cache */
487 unsigned long min_pfn; /* min host physical */
488 unsigned long max_pfn; /* max host physical */
490 /* Virtual CR2 value. Can be read/written by guest. */
491 unsigned long guest_cr2;
493 /* shadow mode status and controls */
494 unsigned int shadow_mode; /* flags to control shadow table operation */
495 pagetable_t shadow_table;
496 spinlock_t shadow_lock;
497 unsigned int shadow_max_page_count; // currently unused
499 /* shadow hashtable */
500 struct shadow_status *shadow_ht;
501 struct shadow_status *shadow_ht_free;
502 struct shadow_status *shadow_ht_extras; /* extra allocation units */
503 unsigned int shadow_extras_count;
505 /* shadow dirty bitmap */
506 unsigned long *shadow_dirty_bitmap;
507 unsigned int shadow_dirty_bitmap_size; /* in pages, bit per page */
509 /* shadow mode stats */
510 unsigned int shadow_page_count;
511 unsigned int shadow_fault_count;
512 unsigned int shadow_dirty_count;
513 unsigned int shadow_dirty_net_count;
514 unsigned int shadow_dirty_block_count;
516 /* Current LDT details. */
517 unsigned long ldt_base, ldt_ents, shadow_ldt_mapcnt;
518 /* Next entry is passed to LGDT on domain switch. */
519 char gdt[10]; /* NB. 10 bytes needed for x86_64. Use 6 bytes for x86_32. */
520 };
522 #define SHM_full_32 (8) /* full virtualization for 32-bit */
524 static inline void write_ptbase(struct mm_struct *mm)
525 {
526 unsigned long pa;
528 #ifdef CONFIG_VMX
529 if ( unlikely(mm->shadow_mode) ) {
530 if (mm->shadow_mode == SHM_full_32)
531 pa = pagetable_val(mm->monitor_table);
532 else
533 pa = pagetable_val(mm->shadow_table);
534 }
535 #else
536 if ( unlikely(mm->shadow_mode) )
537 pa = pagetable_val(mm->shadow_table);
538 #endif
539 else
540 pa = pagetable_val(mm->pagetable);
542 write_cr3(pa);
543 }
545 #define IDLE0_MM \
546 { \
547 perdomain_ptes: 0, \
548 pagetable: mk_pagetable(__pa(idle_pg_table)) \
549 }
551 /* Convenient accessor for mm.gdt. */
552 #define SET_GDT_ENTRIES(_p, _e) ((*(u16 *)((_p)->mm.gdt + 0)) = (((_e)<<3)-1))
553 #define SET_GDT_ADDRESS(_p, _a) ((*(unsigned long *)((_p)->mm.gdt + 2)) = (_a))
554 #define GET_GDT_ENTRIES(_p) (((*(u16 *)((_p)->mm.gdt + 0))+1)>>3)
555 #define GET_GDT_ADDRESS(_p) (*(unsigned long *)((_p)->mm.gdt + 2))
557 void destroy_gdt(struct exec_domain *d);
558 long set_gdt(struct exec_domain *d,
559 unsigned long *frames,
560 unsigned int entries);
562 long set_debugreg(struct exec_domain *p, int reg, unsigned long value);
564 struct microcode_header {
565 unsigned int hdrver;
566 unsigned int rev;
567 unsigned int date;
568 unsigned int sig;
569 unsigned int cksum;
570 unsigned int ldrver;
571 unsigned int pf;
572 unsigned int datasize;
573 unsigned int totalsize;
574 unsigned int reserved[3];
575 };
577 struct microcode {
578 struct microcode_header hdr;
579 unsigned int bits[0];
580 };
582 typedef struct microcode microcode_t;
583 typedef struct microcode_header microcode_header_t;
585 /* microcode format is extended from prescott processors */
586 struct extended_signature {
587 unsigned int sig;
588 unsigned int pf;
589 unsigned int cksum;
590 };
592 struct extended_sigtable {
593 unsigned int count;
594 unsigned int cksum;
595 unsigned int reserved[3];
596 struct extended_signature sigs[0];
597 };
599 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
600 static inline void rep_nop(void)
601 {
602 __asm__ __volatile__("rep;nop");
603 }
605 #define cpu_relax() rep_nop()
607 /* Prefetch instructions for Pentium III and AMD Athlon */
608 #ifdef CONFIG_MPENTIUMIII
610 #define ARCH_HAS_PREFETCH
611 extern inline void prefetch(const void *x)
612 {
613 __asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x));
614 }
616 #elif CONFIG_X86_USE_3DNOW
618 #define ARCH_HAS_PREFETCH
619 #define ARCH_HAS_PREFETCHW
620 #define ARCH_HAS_SPINLOCK_PREFETCH
622 extern inline void prefetch(const void *x)
623 {
624 __asm__ __volatile__ ("prefetch (%0)" : : "r"(x));
625 }
627 extern inline void prefetchw(const void *x)
628 {
629 __asm__ __volatile__ ("prefetchw (%0)" : : "r"(x));
630 }
631 #define spin_lock_prefetch(x) prefetchw(x)
633 #endif
635 void show_guest_stack();
636 void show_trace(unsigned long *esp);
637 void show_stack(unsigned long *esp);
638 void show_registers(struct xen_regs *regs);
639 asmlinkage void fatal_trap(int trapnr, struct xen_regs *regs);
641 #endif /* !__ASSEMBLY__ */
643 #endif /* __ASM_X86_PROCESSOR_H */