debuggers.hg

view xen/arch/i386/nmi.c @ 665:a74ec9013abb

bitkeeper revision 1.349 (3f132695Orgv2nzuhXag1iNmNOy53Q)

Merge labyrinth.cl.cam.ac.uk:/auto/groups/xeno/BK/xeno.bk
into labyrinth.cl.cam.ac.uk:/auto/anfs/scratch/labyrinth/iap10/xeno-clone/xeno.bk
author iap10@labyrinth.cl.cam.ac.uk
date Mon Jul 14 21:54:29 2003 +0000 (2003-07-14)
parents c085fac641e2 384fbe1ed716
children 7fb9fbf0919c
line source
1 /*
2 * linux/arch/i386/nmi.c
3 *
4 * NMI watchdog support on APIC systems
5 *
6 * Started by Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes:
9 * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog.
10 * Mikael Pettersson : Power Management for local APIC NMI watchdog.
11 * Mikael Pettersson : Pentium 4 support for local APIC NMI watchdog.
12 */
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/lib.h>
17 #include <linux/mm.h>
18 #include <linux/irq.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
21 #include <linux/time.h>
22 #include <linux/timex.h>
23 #include <linux/sched.h>
25 #include <asm/mc146818rtc.h>
26 #include <asm/smp.h>
27 #include <asm/msr.h>
28 #include <asm/mpspec.h>
30 unsigned int nmi_watchdog = NMI_NONE;
31 static unsigned int nmi_hz = HZ;
32 unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */
33 extern void show_registers(struct pt_regs *regs);
35 #define K7_EVNTSEL_ENABLE (1 << 22)
36 #define K7_EVNTSEL_INT (1 << 20)
37 #define K7_EVNTSEL_OS (1 << 17)
38 #define K7_EVNTSEL_USR (1 << 16)
39 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
40 #define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
42 #define P6_EVNTSEL0_ENABLE (1 << 22)
43 #define P6_EVNTSEL_INT (1 << 20)
44 #define P6_EVNTSEL_OS (1 << 17)
45 #define P6_EVNTSEL_USR (1 << 16)
46 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED 0x79
47 #define P6_NMI_EVENT P6_EVENT_CPU_CLOCKS_NOT_HALTED
49 #define MSR_P4_MISC_ENABLE 0x1A0
50 #define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
51 #define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
52 #define MSR_P4_PERFCTR0 0x300
53 #define MSR_P4_CCCR0 0x360
54 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
55 #define P4_ESCR_OS (1<<3)
56 #define P4_ESCR_USR (1<<2)
57 #define P4_CCCR_OVF_PMI (1<<26)
58 #define P4_CCCR_THRESHOLD(N) ((N)<<20)
59 #define P4_CCCR_COMPLEMENT (1<<19)
60 #define P4_CCCR_COMPARE (1<<18)
61 #define P4_CCCR_REQUIRED (3<<16)
62 #define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
63 #define P4_CCCR_ENABLE (1<<12)
64 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
65 CRU_ESCR0 (with any non-null event selector) through a complemented
66 max threshold. [IA32-Vol3, Section 14.9.9] */
67 #define MSR_P4_IQ_COUNTER0 0x30C
68 #define MSR_P4_IQ_CCCR0 0x36C
69 #define MSR_P4_CRU_ESCR0 0x3B8
70 #define P4_NMI_CRU_ESCR0 (P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
71 #define P4_NMI_IQ_CCCR0 \
72 (P4_CCCR_OVF_PMI|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
73 P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
75 int __init check_nmi_watchdog (void)
76 {
77 unsigned int prev_nmi_count[NR_CPUS];
78 int j, cpu;
80 if (!nmi_watchdog)
81 return 0;
83 printk("testing NMI watchdog ---\n");
85 for (j = 0; j < smp_num_cpus; j++) {
86 cpu = cpu_logical_map(j);
87 prev_nmi_count[cpu] = irq_stat[cpu].__nmi_count;
88 }
89 sti();
90 mdelay((10*1000)/nmi_hz); /* wait 10 ticks */
92 for (j = 0; j < smp_num_cpus; j++) {
93 cpu = cpu_logical_map(j);
94 if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5)
95 printk("CPU#%d: NMI stuck? (Hyperthread secondary CPU?)\n", cpu);
96 else
97 printk("CPU#%d: NMI okay\n", cpu);
98 }
100 /* now that we know it works we can reduce NMI frequency to
101 something more reasonable; makes a difference in some configs */
102 if (nmi_watchdog == NMI_LOCAL_APIC)
103 nmi_hz = 1;
105 return 0;
106 }
108 static inline void nmi_pm_init(void) { }
109 #define __pminit __init
111 /*
112 * Activate the NMI watchdog via the local APIC.
113 * Original code written by Keith Owens.
114 */
116 static void __pminit clear_msr_range(unsigned int base, unsigned int n)
117 {
118 unsigned int i;
120 for(i = 0; i < n; ++i)
121 wrmsr(base+i, 0, 0);
122 }
124 static void __pminit setup_k7_watchdog(void)
125 {
126 unsigned int evntsel;
128 nmi_perfctr_msr = MSR_K7_PERFCTR0;
130 clear_msr_range(MSR_K7_EVNTSEL0, 4);
131 clear_msr_range(MSR_K7_PERFCTR0, 4);
133 evntsel = K7_EVNTSEL_INT
134 | K7_EVNTSEL_OS
135 | K7_EVNTSEL_USR
136 | K7_NMI_EVENT;
138 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
139 Dprintk("setting K7_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
140 wrmsr(MSR_K7_PERFCTR0, -(cpu_khz/nmi_hz*1000), -1);
141 apic_write(APIC_LVTPC, APIC_DM_NMI);
142 evntsel |= K7_EVNTSEL_ENABLE;
143 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
144 }
146 static void __pminit setup_p6_watchdog(void)
147 {
148 unsigned int evntsel;
150 nmi_perfctr_msr = MSR_P6_PERFCTR0;
152 clear_msr_range(MSR_P6_EVNTSEL0, 2);
153 clear_msr_range(MSR_P6_PERFCTR0, 2);
155 evntsel = P6_EVNTSEL_INT
156 | P6_EVNTSEL_OS
157 | P6_EVNTSEL_USR
158 | P6_NMI_EVENT;
160 wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
161 Dprintk("setting P6_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
162 wrmsr(MSR_P6_PERFCTR0, -(cpu_khz/nmi_hz*1000), 0);
163 apic_write(APIC_LVTPC, APIC_DM_NMI);
164 evntsel |= P6_EVNTSEL0_ENABLE;
165 wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
166 }
168 static int __pminit setup_p4_watchdog(void)
169 {
170 unsigned int misc_enable, dummy;
172 rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
173 if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
174 return 0;
176 nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
178 if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
179 clear_msr_range(0x3F1, 2);
180 /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
181 docs doesn't fully define it, so leave it alone for now. */
182 clear_msr_range(0x3A0, 31);
183 clear_msr_range(0x3C0, 6);
184 clear_msr_range(0x3C8, 6);
185 clear_msr_range(0x3E0, 2);
186 clear_msr_range(MSR_P4_CCCR0, 18);
187 clear_msr_range(MSR_P4_PERFCTR0, 18);
189 wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
190 wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
191 Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000));
192 wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1);
193 apic_write(APIC_LVTPC, APIC_DM_NMI);
194 wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0, 0);
195 return 1;
196 }
198 void __pminit setup_apic_nmi_watchdog (void)
199 {
200 if (!nmi_watchdog)
201 return;
203 switch (boot_cpu_data.x86_vendor) {
204 case X86_VENDOR_AMD:
205 if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
206 return;
207 setup_k7_watchdog();
208 break;
209 case X86_VENDOR_INTEL:
210 switch (boot_cpu_data.x86) {
211 case 6:
212 setup_p6_watchdog();
213 break;
214 case 15:
215 if (!setup_p4_watchdog())
216 return;
217 break;
218 default:
219 return;
220 }
221 break;
222 default:
223 return;
224 }
225 nmi_pm_init();
226 }
229 static unsigned int
230 last_irq_sums [NR_CPUS],
231 alert_counter [NR_CPUS];
233 void touch_nmi_watchdog (void)
234 {
235 int i;
236 for (i = 0; i < smp_num_cpus; i++)
237 alert_counter[i] = 0;
238 }
240 void nmi_watchdog_tick (struct pt_regs * regs)
241 {
242 extern spinlock_t console_lock;
243 extern void die(const char * str, struct pt_regs * regs, long err);
244 extern void putchar_serial(unsigned char c);
246 int sum, cpu = smp_processor_id();
248 sum = apic_timer_irqs[cpu];
250 if (last_irq_sums[cpu] == sum) {
251 /*
252 * Ayiee, looks like this CPU is stuck ... wait a few IRQs (5 seconds)
253 * before doing the oops ...
254 */
255 alert_counter[cpu]++;
256 if (alert_counter[cpu] == 5*nmi_hz) {
257 console_lock = SPIN_LOCK_UNLOCKED;
258 die("NMI Watchdog detected LOCKUP on CPU", regs, cpu);
259 }
260 } else {
261 last_irq_sums[cpu] = sum;
262 alert_counter[cpu] = 0;
263 }
265 if (nmi_perfctr_msr) {
266 if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
267 /*
268 * P4 quirks: - An overflown perfctr will assert its interrupt
269 * until the OVF flag in its CCCR is cleared. - LVTPC is masked
270 * on interrupt and must be
271 * unmasked by the LVTPC handler.
272 */
273 wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0, 0);
274 apic_write(APIC_LVTPC, APIC_DM_NMI);
275 }
276 wrmsr(nmi_perfctr_msr, -(cpu_khz/nmi_hz*1000), -1);
277 }
278 }