debuggers.hg

view xen/include/asm-powerpc/domain.h @ 16712:ad0f20f5590a

Rename uintN_t guest handles to uintN, to avoid nameclash with uintN_t
macros during the handle definitions.
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Dec 28 15:44:51 2007 +0000 (2007-12-28)
parents 3867217d3155
children
line source
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
15 *
16 * Copyright IBM Corp. 2005, 2007
17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
20 */
22 #ifndef _ASM_DOMAIN_H_
23 #define _ASM_DOMAIN_H_
25 #include <xen/cache.h>
26 #include <xen/sched.h>
27 #include <xen/list.h>
28 #include <xen/errno.h>
29 #include <xen/mm.h>
30 #include <public/arch-powerpc.h>
31 #include <asm/htab.h>
32 #include <asm/powerpc64/ppc970.h>
35 typedef struct {
36 ulong mmcr0;
37 ulong mmcr1;
38 ulong mmcra;
39 ulong pmc[NUM_PMCS];
40 } perf_sprs_t;
42 extern atomic_t perf_count_active;
43 extern perf_sprs_t perf_clear_sprs;
45 struct arch_domain {
46 struct domain_htab htab;
48 /* The Real Mode area is fixed to the domain and is accessible while the
49 * processor is in real mode */
50 struct page_info *rma_page;
51 uint rma_order;
53 uint foreign_mfn_count;
54 uint *foreign_mfns;
56 u32 *p2m; /* Array of 32-bit MFNs supports 44 bits of physical memory. */
57 ulong p2m_entries;
59 uint large_page_sizes;
60 uint large_page_order[4];
61 } __cacheline_aligned;
63 struct slb_entry {
64 ulong slb_vsid;
65 ulong slb_esid;
66 };
67 #define SLB_ESID_VALID (1ULL << (63 - 36))
68 #define SLB_ESID_CLASS (1ULL << (63 - 56))
69 #define SLB_ESID_MASK (~0ULL << (63 - 35))
70 #define SLBIE_CLASS_LOG (63-36)
71 #define SLBMTE_ENTRY_MASK ((0x1UL << (63 - 52 + 1)) - 1)
73 struct xencomm;
75 typedef struct {
76 u32 u[4];
77 } __attribute__((aligned(16))) vector128;
79 struct arch_vcpu {
80 cpu_user_regs_t ctxt; /* User-level CPU registers */
82 #ifdef HAS_FLOAT
83 double fprs[NUM_FPRS];
84 #endif
85 #ifdef HAS_VMX
86 vector128 vrs[32];
87 vector128 vscr;
88 u32 vrsave;
89 #endif
91 /* Special-Purpose Registers */
92 ulong sprg[4];
93 ulong timebase;
94 ulong dar;
95 ulong dsisr;
97 /* performance monitor sprs per vcpu */
98 int pmu_enabled;
99 int perf_sprs_stored;
100 perf_sprs_t perf_sprs;
102 /* Segment Lookaside Buffer */
103 struct slb_entry slb_entries[NUM_SLB_ENTRIES];
105 u32 dec;
106 struct cpu_vcpu cpu; /* CPU-specific bits */
107 struct xencomm *xencomm;
108 } __cacheline_aligned;
110 extern void full_resume(void);
112 extern void save_sprs(struct vcpu *);
113 extern void load_sprs(struct vcpu *);
114 extern void save_pmc_sprs(perf_sprs_t *p_sprs);
115 extern void load_pmc_sprs(perf_sprs_t *p_sprs);
116 extern void save_segments(struct vcpu *);
117 extern void load_segments(struct vcpu *);
118 extern void save_float(struct vcpu *);
119 extern void load_float(struct vcpu *);
121 #define rma_size(rma_order) (1UL << ((rma_order) + PAGE_SHIFT))
123 #endif