debuggers.hg

view tools/libxc/xc_cpufeature.h @ 21067:b4a1832a916f

Update Xen version to 4.0.0-rc6
author Keir Fraser <keir.fraser@citrix.com>
date Tue Mar 09 18:18:05 2010 +0000 (2010-03-09)
parents 9ed53e602119
children 3ffdb094c2c0
line source
1 #ifndef __LIBXC_CPUFEATURE_H
2 #define __LIBXC_CPUFEATURE_H
4 /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
5 #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
6 #define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */
7 #define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
8 #define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */
9 #define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
10 #define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
11 #define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
12 #define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */
13 #define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
14 #define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */
15 #define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */
16 #define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
17 #define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */
18 #define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
19 #define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
20 #define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
21 #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
22 #define X86_FEATURE_PN (0*32+18) /* Processor serial number */
23 #define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */
24 #define X86_FEATURE_DS (0*32+21) /* Debug Store */
25 #define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
26 #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
27 #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
28 /* of FPU context), and CR4.OSFXSR available */
29 #define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */
30 #define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */
31 #define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */
32 #define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */
33 #define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */
34 #define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */
35 #define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */
37 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
38 /* Don't duplicate feature flags which are redundant with Intel! */
39 #define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */
40 #define X86_FEATURE_MP (1*32+19) /* MP Capable. */
41 #define X86_FEATURE_NX (1*32+20) /* Execute Disable */
42 #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
43 #define X86_FEATURE_FFXSR (1*32+25) /* FFXSR instruction optimizations */
44 #define X86_FEATURE_PAGE1GB (1*32+26) /* 1Gb large page support */
45 #define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
46 #define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
47 #define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
48 #define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
50 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
51 #define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */
52 #define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */
53 #define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */
55 /* Other features, Linux-defined mapping, word 3 */
56 /* This range is used for feature bits which conflict or are synthesized */
57 #define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */
58 #define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */
59 #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
60 #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
61 /* cpu types for specific tunings: */
62 #define X86_FEATURE_K8 (3*32+ 4) /* Opteron, Athlon64 */
63 #define X86_FEATURE_K7 (3*32+ 5) /* Athlon */
64 #define X86_FEATURE_P3 (3*32+ 6) /* P3 */
65 #define X86_FEATURE_P4 (3*32+ 7) /* P4 */
66 #define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
68 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
69 #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
70 #define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */
71 #define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */
72 #define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */
73 #define X86_FEATURE_VMXE (4*32+ 5) /* Virtual Machine Extensions */
74 #define X86_FEATURE_SMXE (4*32+ 6) /* Safer Mode Extensions */
75 #define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */
76 #define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
77 #define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental Streaming SIMD Extensions-3 */
78 #define X86_FEATURE_CID (4*32+10) /* Context ID */
79 #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
80 #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
81 #define X86_FEATURE_PDCM (4*32+15) /* Perf/Debug Capability MSR */
82 #define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
83 #define X86_FEATURE_SSE4_1 (4*32+19) /* Streaming SIMD Extensions 4.1 */
84 #define X86_FEATURE_SSE4_2 (4*32+20) /* Streaming SIMD Extensions 4.2 */
85 #define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
86 #define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
87 #define X86_FEATURE_HYPERVISOR (4*32+31) /* Running under some hypervisor */
89 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
90 #define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */
91 #define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */
92 #define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */
93 #define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */
94 #define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */
95 #define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */
96 #define X86_FEATURE_PHE (5*32+ 10) /* PadLock Hash Engine */
97 #define X86_FEATURE_PHE_EN (5*32+ 11) /* PHE enabled */
98 #define X86_FEATURE_PMM (5*32+ 12) /* PadLock Montgomery Multiplier */
99 #define X86_FEATURE_PMM_EN (5*32+ 13) /* PMM enabled */
101 /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
102 #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
103 #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
104 #define X86_FEATURE_SVME (6*32+ 2) /* Secure Virtual Machine */
105 #define X86_FEATURE_EXTAPICSPACE (6*32+ 3) /* Extended APIC space */
106 #define X86_FEATURE_ALTMOVCR (6*32+ 4) /* LOCK MOV CR accesses CR+8 */
107 #define X86_FEATURE_ABM (6*32+ 5) /* Advanced Bit Manipulation */
108 #define X86_FEATURE_SSE4A (6*32+ 6) /* AMD Streaming SIMD Extensions-4a */
109 #define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE Access */
110 #define X86_FEATURE_3DNOWPF (6*32+ 8) /* 3DNow! Prefetch */
111 #define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */
112 #define X86_FEATURE_IBS (6*32+ 10) /* Instruction Based Sampling */
113 #define X86_FEATURE_SSE5 (6*32+ 11) /* AMD Streaming SIMD Extensions-5 */
114 #define X86_FEATURE_SKINIT (6*32+ 12) /* SKINIT, STGI/CLGI, DEV */
115 #define X86_FEATURE_WDT (6*32+ 13) /* Watchdog Timer */
117 #endif /* __LIBXC_CPUFEATURE_H */