debuggers.hg

view xen/include/asm-x86/smp.h @ 3685:bbe8541361dd

bitkeeper revision 1.1159.1.542 (42038a42_52IAalMZRKdTn0UbVN5fw)

Merge tempest.cl.cam.ac.uk:/auto/groups/xeno-xenod/BK/xeno.bk
into tempest.cl.cam.ac.uk:/local/scratch/smh22/xen-unstable.bk
author smh22@tempest.cl.cam.ac.uk
date Fri Feb 04 14:44:18 2005 +0000 (2005-02-04)
parents bd470dc06d31 bf2c38625b39
children 0a4b76b6b5a0
line source
1 #ifndef __ASM_SMP_H
2 #define __ASM_SMP_H
4 #ifndef __ASSEMBLY__
5 #include <xen/config.h>
6 #include <asm/fixmap.h>
7 #include <asm/mpspec.h>
8 #include <asm/io_apic.h>
9 #include <asm/apic.h>
10 #endif
12 #ifdef CONFIG_SMP
13 #ifndef __ASSEMBLY__
15 /*
16 * Private routines/data
17 */
19 extern void smp_alloc_memory(void);
20 extern unsigned long phys_cpu_present_map;
21 extern unsigned long cpu_online_map;
22 extern volatile unsigned long smp_invalidate_needed;
23 extern int pic_mode;
24 extern int smp_num_siblings;
25 extern int cpu_sibling_map[];
27 /*
28 * On x86 all CPUs are mapped 1:1 to the APIC space.
29 * This simplifies scheduling and IPI sending and
30 * compresses data structures.
31 */
32 static inline int cpu_logical_map(int cpu)
33 {
34 return cpu;
35 }
36 static inline int cpu_number_map(int cpu)
37 {
38 return cpu;
39 }
41 /*
42 * Some lowlevel functions might want to know about
43 * the real APIC ID <-> CPU # mapping.
44 */
45 #define MAX_APICID 256
46 extern volatile int cpu_to_physical_apicid[NR_CPUS];
47 extern volatile int physical_apicid_to_cpu[MAX_APICID];
48 extern volatile int cpu_to_logical_apicid[NR_CPUS];
49 extern volatile int logical_apicid_to_cpu[MAX_APICID];
51 /*
52 * General functions that each host system must provide.
53 */
55 /*extern void smp_boot_cpus(void);*/
56 extern void smp_store_cpu_info(int id); /* Store per CPU info (like the initial udelay numbers */
58 /*
59 * This function is needed by all SMP systems. It must _always_ be valid
60 * from the initial startup. We map APIC_BASE very early in page_setup(),
61 * so this is correct in the x86 case.
62 */
64 #define smp_processor_id() (current->processor)
66 static __inline int hard_smp_processor_id(void)
67 {
68 /* we don't want to mark this access volatile - bad code generation */
69 return GET_APIC_ID(*(unsigned *)(APIC_BASE+APIC_ID));
70 }
72 static __inline int logical_smp_processor_id(void)
73 {
74 /* we don't want to mark this access volatile - bad code generation */
75 return GET_APIC_LOGICAL_ID(*(unsigned *)(APIC_BASE+APIC_LDR));
76 }
78 #endif /* !__ASSEMBLY__ */
80 #define NO_PROC_ID 0xFF /* No processor magic marker */
82 /*
83 * This magic constant controls our willingness to transfer
84 * a process across CPUs. Such a transfer incurs misses on the L1
85 * cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
86 * gut feeling is this will vary by board in value. For a board
87 * with separate L2 cache it probably depends also on the RSS, and
88 * for a board with shared L2 cache it ought to decay fast as other
89 * processes are run.
90 */
92 #define PROC_CHANGE_PENALTY 15 /* Schedule penalty */
94 #endif
95 #endif