debuggers.hg

view xen/include/asm-x86/smp.h @ 2383:bd470dc06d31

bitkeeper revision 1.1159.1.104 (412cb2ee26F5kEIHPDh0Kj4pQScH6Q)

Merge labyrinth.cl.cam.ac.uk:/auto/groups/xeno/BK/xeno.bk
into labyrinth.cl.cam.ac.uk:/auto/groups/xeno/users/kaf24/xeno
author kaf24@labyrinth.cl.cam.ac.uk
date Wed Aug 25 15:40:30 2004 +0000 (2004-08-25)
parents 0e23f01219c6 22afa9c3be28
children bf2c38625b39 bbe8541361dd
line source
1 #ifndef __ASM_SMP_H
2 #define __ASM_SMP_H
4 #ifndef __ASSEMBLY__
5 #include <xen/config.h>
6 #include <asm/fixmap.h>
7 #include <asm/mpspec.h>
8 #include <asm/io_apic.h>
9 #include <asm/apic.h>
10 #endif
12 #ifdef CONFIG_SMP
13 #ifndef __ASSEMBLY__
15 /*
16 * Private routines/data
17 */
19 extern void smp_alloc_memory(void);
20 extern unsigned long phys_cpu_present_map;
21 extern unsigned long cpu_online_map;
22 extern volatile unsigned long smp_invalidate_needed;
23 extern int pic_mode;
24 extern int smp_num_siblings;
25 extern int cpu_sibling_map[];
27 /*
28 * On x86 all CPUs are mapped 1:1 to the APIC space.
29 * This simplifies scheduling and IPI sending and
30 * compresses data structures.
31 */
32 static inline int cpu_logical_map(int cpu)
33 {
34 return cpu;
35 }
36 static inline int cpu_number_map(int cpu)
37 {
38 return cpu;
39 }
41 /*
42 * Some lowlevel functions might want to know about
43 * the real APIC ID <-> CPU # mapping.
44 */
45 #define MAX_APICID 256
46 extern volatile int cpu_to_physical_apicid[NR_CPUS];
47 extern volatile int physical_apicid_to_cpu[MAX_APICID];
48 extern volatile int cpu_to_logical_apicid[NR_CPUS];
49 extern volatile int logical_apicid_to_cpu[MAX_APICID];
51 /*
52 * General functions that each host system must provide.
53 */
55 /*extern void smp_boot_cpus(void);*/
56 extern void smp_store_cpu_info(int id); /* Store per CPU info (like the initial udelay numbers */
58 /*
59 * This function is needed by all SMP systems. It must _always_ be valid
60 * from the initial startup. We map APIC_BASE very early in page_setup(),
61 * so this is correct in the x86 case.
62 */
64 #if defined(__i386__)
65 #define smp_processor_id() (current->processor)
66 #elif defined(__x86_64__)
67 #include <asm/pda.h>
68 #define smp_processor_id() read_pda(cpunumber)
69 #endif
71 static __inline int hard_smp_processor_id(void)
72 {
73 /* we don't want to mark this access volatile - bad code generation */
74 return GET_APIC_ID(*(unsigned *)(APIC_BASE+APIC_ID));
75 }
77 static __inline int logical_smp_processor_id(void)
78 {
79 /* we don't want to mark this access volatile - bad code generation */
80 return GET_APIC_LOGICAL_ID(*(unsigned *)(APIC_BASE+APIC_LDR));
81 }
83 #endif /* !__ASSEMBLY__ */
85 #define NO_PROC_ID 0xFF /* No processor magic marker */
87 /*
88 * This magic constant controls our willingness to transfer
89 * a process across CPUs. Such a transfer incurs misses on the L1
90 * cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
91 * gut feeling is this will vary by board in value. For a board
92 * with separate L2 cache it probably depends also on the RSS, and
93 * for a board with shared L2 cache it ought to decay fast as other
94 * processes are run.
95 */
97 #define PROC_CHANGE_PENALTY 15 /* Schedule penalty */
99 #endif
100 #endif