debuggers.hg

view xen/arch/x86/mtrr/main.c @ 3650:beb0887c54bc

bitkeeper revision 1.1159.238.1 (4200c8d8KsGlaM3w6o3y4GHhK1jKjg)

A typesafe allocator submitted by Rusty Russel with trivial renames by me.
Signed-off-by: Rusty Russel <rusty@rustcorp.com.au> (authored)
Signed-off-by: ian.pratt@cl.cam.ac.uk
author iap10@labyrinth.cl.cam.ac.uk
date Wed Feb 02 12:34:32 2005 +0000 (2005-02-02)
parents c23dd7ec1f54
children 0ef6e8e6e85d
line source
1 /* Generic MTRR (Memory Type Range Register) driver.
3 Copyright (C) 1997-2000 Richard Gooch
4 Copyright (c) 2002 Patrick Mochel
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Library General Public
8 License as published by the Free Software Foundation; either
9 version 2 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Library General Public License for more details.
16 You should have received a copy of the GNU Library General Public
17 License along with this library; if not, write to the Free
18 Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 Richard Gooch may be reached by email at rgooch@atnf.csiro.au
21 The postal address is:
22 Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
24 Source: "Pentium Pro Family Developer's Manual, Volume 3:
25 Operating System Writer's Guide" (Intel document number 242692),
26 section 11.11.7
28 This was cleaned and made readable by Patrick Mochel <mochel@osdl.org>
29 on 6-7 March 2002.
30 Source: Intel Architecture Software Developers Manual, Volume 3:
31 System Programming Guide; Section 9.11. (1997 edition - PPro).
32 */
34 #include <xen/config.h>
35 #include <xen/init.h>
36 #include <xen/pci.h>
37 #include <xen/smp.h>
38 #include <asm/mtrr.h>
39 #include <asm/uaccess.h>
40 #include <asm/processor.h>
41 #include <asm/msr.h>
42 #include "mtrr.h"
44 #define MTRR_VERSION "2.0 (20020519)"
46 /* No blocking mutexes in Xen. Spin instead. */
47 #define DECLARE_MUTEX(_m) spinlock_t _m = SPIN_LOCK_UNLOCKED
48 #define down(_m) spin_lock(_m)
49 #define up(_m) spin_unlock(_m)
51 #define num_booting_cpus() smp_num_cpus
53 u32 num_var_ranges = 0;
55 unsigned int *usage_table;
56 static DECLARE_MUTEX(main_lock);
58 u32 size_or_mask, size_and_mask;
60 static struct mtrr_ops * mtrr_ops[X86_VENDOR_NUM] = {};
62 struct mtrr_ops * mtrr_if = NULL;
64 __initdata char *mtrr_if_name[] = {
65 "none", "Intel", "AMD K6", "Cyrix ARR", "Centaur MCR"
66 };
68 static void set_mtrr(unsigned int reg, unsigned long base,
69 unsigned long size, mtrr_type type);
71 extern int arr3_protected;
73 static char *mtrr_strings[MTRR_NUM_TYPES] =
74 {
75 "uncachable", /* 0 */
76 "write-combining", /* 1 */
77 "?", /* 2 */
78 "?", /* 3 */
79 "write-through", /* 4 */
80 "write-protect", /* 5 */
81 "write-back", /* 6 */
82 };
84 char *mtrr_attrib_to_str(int x)
85 {
86 return (x <= 6) ? mtrr_strings[x] : "?";
87 }
89 void set_mtrr_ops(struct mtrr_ops * ops)
90 {
91 if (ops->vendor && ops->vendor < X86_VENDOR_NUM)
92 mtrr_ops[ops->vendor] = ops;
93 }
95 /* Returns non-zero if we have the write-combining memory type */
96 static int have_wrcomb(void)
97 {
98 struct pci_dev *dev;
100 if ((dev = pci_find_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) {
101 /* ServerWorks LE chipsets have problems with write-combining
102 Don't allow it and leave room for other chipsets to be tagged */
103 if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
104 dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) {
105 printk(KERN_INFO "mtrr: Serverworks LE detected. Write-combining disabled.\n");
106 return 0;
107 }
108 /* Intel 450NX errata # 23. Non ascending cachline evictions to
109 write combining memory may resulting in data corruption */
110 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
111 dev->device == PCI_DEVICE_ID_INTEL_82451NX)
112 {
113 printk(KERN_INFO "mtrr: Intel 450NX MMC detected. Write-combining disabled.\n");
114 return 0;
115 }
116 }
117 return (mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0);
118 }
120 /* This function returns the number of variable MTRRs */
121 void __init set_num_var_ranges(void)
122 {
123 unsigned long config = 0, dummy;
125 if (use_intel()) {
126 rdmsr(MTRRcap_MSR, config, dummy);
127 } else if (is_cpu(AMD))
128 config = 2;
129 else if (is_cpu(CYRIX) || is_cpu(CENTAUR))
130 config = 8;
131 num_var_ranges = config & 0xff;
132 }
134 static void __init init_table(void)
135 {
136 int i, max;
138 max = num_var_ranges;
139 if ((usage_table = xmalloc_array(unsigned int, max)) == NULL) {
140 printk(KERN_ERR "mtrr: could not allocate\n");
141 return;
142 }
143 for (i = 0; i < max; i++)
144 usage_table[i] = 1;
145 }
147 struct set_mtrr_data {
148 atomic_t count;
149 atomic_t gate;
150 unsigned long smp_base;
151 unsigned long smp_size;
152 unsigned int smp_reg;
153 mtrr_type smp_type;
154 };
156 #ifdef CONFIG_SMP
158 static void ipi_handler(void *info)
159 /* [SUMMARY] Synchronisation handler. Executed by "other" CPUs.
160 [RETURNS] Nothing.
161 */
162 {
163 struct set_mtrr_data *data = info;
164 unsigned long flags;
166 local_irq_save(flags);
168 atomic_dec(&data->count);
169 while(!atomic_read(&data->gate)) {
170 cpu_relax();
171 barrier();
172 }
174 /* The master has cleared me to execute */
175 if (data->smp_reg != ~0U)
176 mtrr_if->set(data->smp_reg, data->smp_base,
177 data->smp_size, data->smp_type);
178 else
179 mtrr_if->set_all();
181 atomic_dec(&data->count);
182 while(atomic_read(&data->gate)) {
183 cpu_relax();
184 barrier();
185 }
186 atomic_dec(&data->count);
187 local_irq_restore(flags);
188 }
190 #endif
192 /**
193 * set_mtrr - update mtrrs on all processors
194 * @reg: mtrr in question
195 * @base: mtrr base
196 * @size: mtrr size
197 * @type: mtrr type
198 *
199 * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly:
200 *
201 * 1. Send IPI to do the following:
202 * 2. Disable Interrupts
203 * 3. Wait for all procs to do so
204 * 4. Enter no-fill cache mode
205 * 5. Flush caches
206 * 6. Clear PGE bit
207 * 7. Flush all TLBs
208 * 8. Disable all range registers
209 * 9. Update the MTRRs
210 * 10. Enable all range registers
211 * 11. Flush all TLBs and caches again
212 * 12. Enter normal cache mode and reenable caching
213 * 13. Set PGE
214 * 14. Wait for buddies to catch up
215 * 15. Enable interrupts.
216 *
217 * What does that mean for us? Well, first we set data.count to the number
218 * of CPUs. As each CPU disables interrupts, it'll decrement it once. We wait
219 * until it hits 0 and proceed. We set the data.gate flag and reset data.count.
220 * Meanwhile, they are waiting for that flag to be set. Once it's set, each
221 * CPU goes through the transition of updating MTRRs. The CPU vendors may each do it
222 * differently, so we call mtrr_if->set() callback and let them take care of it.
223 * When they're done, they again decrement data->count and wait for data.gate to
224 * be reset.
225 * When we finish, we wait for data.count to hit 0 and toggle the data.gate flag.
226 * Everyone then enables interrupts and we all continue on.
227 *
228 * Note that the mechanism is the same for UP systems, too; all the SMP stuff
229 * becomes nops.
230 */
231 static void set_mtrr(unsigned int reg, unsigned long base,
232 unsigned long size, mtrr_type type)
233 {
234 struct set_mtrr_data data;
235 unsigned long flags;
237 data.smp_reg = reg;
238 data.smp_base = base;
239 data.smp_size = size;
240 data.smp_type = type;
241 atomic_set(&data.count, num_booting_cpus() - 1);
242 atomic_set(&data.gate,0);
244 /* Start the ball rolling on other CPUs */
245 if (smp_call_function(ipi_handler, &data, 1, 0) != 0)
246 panic("mtrr: timed out waiting for other CPUs\n");
248 local_irq_save(flags);
250 while(atomic_read(&data.count)) {
251 cpu_relax();
252 barrier();
253 }
254 /* ok, reset count and toggle gate */
255 atomic_set(&data.count, num_booting_cpus() - 1);
256 atomic_set(&data.gate,1);
258 /* do our MTRR business */
260 /* HACK!
261 * We use this same function to initialize the mtrrs on boot.
262 * The state of the boot cpu's mtrrs has been saved, and we want
263 * to replicate across all the APs.
264 * If we're doing that @reg is set to something special...
265 */
266 if (reg != ~0U)
267 mtrr_if->set(reg,base,size,type);
269 /* wait for the others */
270 while(atomic_read(&data.count)) {
271 cpu_relax();
272 barrier();
273 }
274 atomic_set(&data.count, num_booting_cpus() - 1);
275 atomic_set(&data.gate,0);
277 /*
278 * Wait here for everyone to have seen the gate change
279 * So we're the last ones to touch 'data'
280 */
281 while(atomic_read(&data.count)) {
282 cpu_relax();
283 barrier();
284 }
285 local_irq_restore(flags);
286 }
288 /**
289 * mtrr_add_page - Add a memory type region
290 * @base: Physical base address of region in pages (4 KB)
291 * @size: Physical size of region in pages (4 KB)
292 * @type: Type of MTRR desired
293 * @increment: If this is true do usage counting on the region
294 *
295 * Memory type region registers control the caching on newer Intel and
296 * non Intel processors. This function allows drivers to request an
297 * MTRR is added. The details and hardware specifics of each processor's
298 * implementation are hidden from the caller, but nevertheless the
299 * caller should expect to need to provide a power of two size on an
300 * equivalent power of two boundary.
301 *
302 * If the region cannot be added either because all regions are in use
303 * or the CPU cannot support it a negative value is returned. On success
304 * the register number for this entry is returned, but should be treated
305 * as a cookie only.
306 *
307 * On a multiprocessor machine the changes are made to all processors.
308 * This is required on x86 by the Intel processors.
309 *
310 * The available types are
311 *
312 * %MTRR_TYPE_UNCACHABLE - No caching
313 *
314 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
315 *
316 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
317 *
318 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
319 *
320 * BUGS: Needs a quiet flag for the cases where drivers do not mind
321 * failures and do not wish system log messages to be sent.
322 */
324 int mtrr_add_page(unsigned long base, unsigned long size,
325 unsigned int type, char increment)
326 {
327 int i;
328 mtrr_type ltype;
329 unsigned long lbase;
330 unsigned int lsize;
331 int error;
333 if (!mtrr_if)
334 return -ENXIO;
336 if ((error = mtrr_if->validate_add_page(base,size,type)))
337 return error;
339 if (type >= MTRR_NUM_TYPES) {
340 printk(KERN_WARNING "mtrr: type: %u invalid\n", type);
341 return -EINVAL;
342 }
344 /* If the type is WC, check that this processor supports it */
345 if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) {
346 printk(KERN_WARNING
347 "mtrr: your processor doesn't support write-combining\n");
348 return -ENOSYS;
349 }
351 if (base & size_or_mask || size & size_or_mask) {
352 printk(KERN_WARNING "mtrr: base or size exceeds the MTRR width\n");
353 return -EINVAL;
354 }
356 error = -EINVAL;
358 /* Search for existing MTRR */
359 down(&main_lock);
360 for (i = 0; i < num_var_ranges; ++i) {
361 mtrr_if->get(i, &lbase, &lsize, &ltype);
362 if (base >= lbase + lsize)
363 continue;
364 if ((base < lbase) && (base + size <= lbase))
365 continue;
366 /* At this point we know there is some kind of overlap/enclosure */
367 if ((base < lbase) || (base + size > lbase + lsize)) {
368 printk(KERN_WARNING
369 "mtrr: 0x%lx000,0x%lx000 overlaps existing"
370 " 0x%lx000,0x%x000\n", base, size, lbase,
371 lsize);
372 goto out;
373 }
374 /* New region is enclosed by an existing region */
375 if (ltype != type) {
376 if (type == MTRR_TYPE_UNCACHABLE)
377 continue;
378 printk (KERN_WARNING "mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n",
379 base, size, mtrr_attrib_to_str(ltype),
380 mtrr_attrib_to_str(type));
381 goto out;
382 }
383 if (increment)
384 ++usage_table[i];
385 error = i;
386 goto out;
387 }
388 /* Search for an empty MTRR */
389 i = mtrr_if->get_free_region(base, size);
390 if (i >= 0) {
391 set_mtrr(i, base, size, type);
392 usage_table[i] = 1;
393 } else
394 printk(KERN_INFO "mtrr: no more MTRRs available\n");
395 error = i;
396 out:
397 up(&main_lock);
398 return error;
399 }
401 /**
402 * mtrr_add - Add a memory type region
403 * @base: Physical base address of region
404 * @size: Physical size of region
405 * @type: Type of MTRR desired
406 * @increment: If this is true do usage counting on the region
407 *
408 * Memory type region registers control the caching on newer Intel and
409 * non Intel processors. This function allows drivers to request an
410 * MTRR is added. The details and hardware specifics of each processor's
411 * implementation are hidden from the caller, but nevertheless the
412 * caller should expect to need to provide a power of two size on an
413 * equivalent power of two boundary.
414 *
415 * If the region cannot be added either because all regions are in use
416 * or the CPU cannot support it a negative value is returned. On success
417 * the register number for this entry is returned, but should be treated
418 * as a cookie only.
419 *
420 * On a multiprocessor machine the changes are made to all processors.
421 * This is required on x86 by the Intel processors.
422 *
423 * The available types are
424 *
425 * %MTRR_TYPE_UNCACHABLE - No caching
426 *
427 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
428 *
429 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
430 *
431 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
432 *
433 * BUGS: Needs a quiet flag for the cases where drivers do not mind
434 * failures and do not wish system log messages to be sent.
435 */
437 int
438 mtrr_add(unsigned long base, unsigned long size, unsigned int type,
439 char increment)
440 {
441 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
442 printk(KERN_WARNING "mtrr: size and base must be multiples of 4 kiB\n");
443 printk(KERN_DEBUG "mtrr: size: 0x%lx base: 0x%lx\n", size, base);
444 return -EINVAL;
445 }
446 return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type,
447 increment);
448 }
450 /**
451 * mtrr_del_page - delete a memory type region
452 * @reg: Register returned by mtrr_add
453 * @base: Physical base address
454 * @size: Size of region
455 *
456 * If register is supplied then base and size are ignored. This is
457 * how drivers should call it.
458 *
459 * Releases an MTRR region. If the usage count drops to zero the
460 * register is freed and the region returns to default state.
461 * On success the register is returned, on failure a negative error
462 * code.
463 */
465 int mtrr_del_page(int reg, unsigned long base, unsigned long size)
466 {
467 int i, max;
468 mtrr_type ltype;
469 unsigned long lbase;
470 unsigned int lsize;
471 int error = -EINVAL;
473 if (!mtrr_if)
474 return -ENXIO;
476 max = num_var_ranges;
477 down(&main_lock);
478 if (reg < 0) {
479 /* Search for existing MTRR */
480 for (i = 0; i < max; ++i) {
481 mtrr_if->get(i, &lbase, &lsize, &ltype);
482 if (lbase == base && lsize == size) {
483 reg = i;
484 break;
485 }
486 }
487 if (reg < 0) {
488 printk(KERN_DEBUG "mtrr: no MTRR for %lx000,%lx000 found\n", base,
489 size);
490 goto out;
491 }
492 }
493 if (reg >= max) {
494 printk(KERN_WARNING "mtrr: register: %d too big\n", reg);
495 goto out;
496 }
497 if (is_cpu(CYRIX) && !use_intel()) {
498 if ((reg == 3) && arr3_protected) {
499 printk(KERN_WARNING "mtrr: ARR3 cannot be changed\n");
500 goto out;
501 }
502 }
503 mtrr_if->get(reg, &lbase, &lsize, &ltype);
504 if (lsize < 1) {
505 printk(KERN_WARNING "mtrr: MTRR %d not used\n", reg);
506 goto out;
507 }
508 if (usage_table[reg] < 1) {
509 printk(KERN_WARNING "mtrr: reg: %d has count=0\n", reg);
510 goto out;
511 }
512 if (--usage_table[reg] < 1)
513 set_mtrr(reg, 0, 0, 0);
514 error = reg;
515 out:
516 up(&main_lock);
517 return error;
518 }
519 /**
520 * mtrr_del - delete a memory type region
521 * @reg: Register returned by mtrr_add
522 * @base: Physical base address
523 * @size: Size of region
524 *
525 * If register is supplied then base and size are ignored. This is
526 * how drivers should call it.
527 *
528 * Releases an MTRR region. If the usage count drops to zero the
529 * register is freed and the region returns to default state.
530 * On success the register is returned, on failure a negative error
531 * code.
532 */
534 int
535 mtrr_del(int reg, unsigned long base, unsigned long size)
536 {
537 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
538 printk(KERN_INFO "mtrr: size and base must be multiples of 4 kiB\n");
539 printk(KERN_DEBUG "mtrr: size: 0x%lx base: 0x%lx\n", size, base);
540 return -EINVAL;
541 }
542 return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT);
543 }
545 EXPORT_SYMBOL(mtrr_add);
546 EXPORT_SYMBOL(mtrr_del);
548 /* HACK ALERT!
549 * These should be called implicitly, but we can't yet until all the initcall
550 * stuff is done...
551 */
552 extern void amd_init_mtrr(void);
553 extern void cyrix_init_mtrr(void);
554 extern void centaur_init_mtrr(void);
556 static void __init init_ifs(void)
557 {
558 amd_init_mtrr();
559 cyrix_init_mtrr();
560 centaur_init_mtrr();
561 }
563 static void __init init_other_cpus(void)
564 {
565 if (use_intel())
566 get_mtrr_state();
568 /* bring up the other processors */
569 set_mtrr(~0U,0,0,0);
571 if (use_intel()) {
572 finalize_mtrr_state();
573 mtrr_state_warn();
574 }
575 }
578 struct mtrr_value {
579 mtrr_type ltype;
580 unsigned long lbase;
581 unsigned int lsize;
582 };
584 /**
585 * mtrr_init - initialize mtrrs on the boot CPU
586 *
587 * This needs to be called early; before any of the other CPUs are
588 * initialized (i.e. before smp_init()).
589 *
590 */
591 static int __init mtrr_init(void)
592 {
593 init_ifs();
595 if (cpu_has_mtrr) {
596 mtrr_if = &generic_mtrr_ops;
597 size_or_mask = 0xff000000; /* 36 bits */
598 size_and_mask = 0x00f00000;
600 switch (boot_cpu_data.x86_vendor) {
601 case X86_VENDOR_AMD:
602 /* The original Athlon docs said that
603 total addressable memory is 44 bits wide.
604 It was not really clear whether its MTRRs
605 follow this or not. (Read: 44 or 36 bits).
606 However, "x86-64_overview.pdf" explicitly
607 states that "previous implementations support
608 36 bit MTRRs" and also provides a way to
609 query the width (in bits) of the physical
610 addressable memory on the Hammer family.
611 */
612 if (boot_cpu_data.x86 == 15
613 && (cpuid_eax(0x80000000) >= 0x80000008)) {
614 u32 phys_addr;
615 phys_addr = cpuid_eax(0x80000008) & 0xff;
616 size_or_mask =
617 ~((1 << (phys_addr - PAGE_SHIFT)) - 1);
618 size_and_mask = ~size_or_mask & 0xfff00000;
619 }
620 /* Athlon MTRRs use an Intel-compatible interface for
621 * getting and setting */
622 break;
623 case X86_VENDOR_CENTAUR:
624 if (boot_cpu_data.x86 == 6) {
625 /* VIA Cyrix family have Intel style MTRRs, but don't support PAE */
626 size_or_mask = 0xfff00000; /* 32 bits */
627 size_and_mask = 0;
628 }
629 break;
631 default:
632 break;
633 }
634 } else {
635 switch (boot_cpu_data.x86_vendor) {
636 case X86_VENDOR_AMD:
637 if (cpu_has_k6_mtrr) {
638 /* Pre-Athlon (K6) AMD CPU MTRRs */
639 mtrr_if = mtrr_ops[X86_VENDOR_AMD];
640 size_or_mask = 0xfff00000; /* 32 bits */
641 size_and_mask = 0;
642 }
643 break;
644 case X86_VENDOR_CENTAUR:
645 if (cpu_has_centaur_mcr) {
646 mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR];
647 size_or_mask = 0xfff00000; /* 32 bits */
648 size_and_mask = 0;
649 }
650 break;
651 case X86_VENDOR_CYRIX:
652 if (cpu_has_cyrix_arr) {
653 mtrr_if = mtrr_ops[X86_VENDOR_CYRIX];
654 size_or_mask = 0xfff00000; /* 32 bits */
655 size_and_mask = 0;
656 }
657 break;
658 default:
659 break;
660 }
661 }
662 printk(KERN_INFO "mtrr: v%s\n",MTRR_VERSION);
664 if (mtrr_if) {
665 set_num_var_ranges();
666 init_table();
667 init_other_cpus();
668 return 0;
669 }
670 return -ENXIO;
671 }
673 __initcall(mtrr_init);