debuggers.hg

view xen/drivers/pci/pci.c @ 3650:beb0887c54bc

bitkeeper revision 1.1159.238.1 (4200c8d8KsGlaM3w6o3y4GHhK1jKjg)

A typesafe allocator submitted by Rusty Russel with trivial renames by me.
Signed-off-by: Rusty Russel <rusty@rustcorp.com.au> (authored)
Signed-off-by: ian.pratt@cl.cam.ac.uk
author iap10@labyrinth.cl.cam.ac.uk
date Wed Feb 02 12:34:32 2005 +0000 (2005-02-02)
parents 51052c8b6456
children 0ef6e8e6e85d
line source
1 /*
2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
3 *
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 *
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * David Mosberger-Tang
8 *
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 */
12 #include <xen/config.h>
13 #include <xen/sched.h>
14 #include <xen/types.h>
15 #include <xen/pci.h>
16 #include <xen/init.h>
17 #include <xen/slab.h>
18 #include <xen/ioport.h>
19 #include <xen/spinlock.h>
20 #include <xen/delay.h>
21 #include <xen/cache.h>
22 #include <asm/page.h>
24 #undef DEBUG
26 #ifdef DEBUG
27 #define DBG(x...) printk(x)
28 #else
29 #define DBG(x...)
30 #endif
32 LIST_HEAD(pci_root_buses);
33 LIST_HEAD(pci_devices);
35 /**
36 * pci_find_slot - locate PCI device from a given PCI slot
37 * @bus: number of PCI bus on which desired PCI device resides
38 * @devfn: encodes number of PCI slot in which the desired PCI
39 * device resides and the logical device number within that slot
40 * in case of multi-function devices.
41 *
42 * Given a PCI bus and slot/function number, the desired PCI device
43 * is located in system global list of PCI devices. If the device
44 * is found, a pointer to its data structure is returned. If no
45 * device is found, %NULL is returned.
46 */
47 struct pci_dev *
48 pci_find_slot(unsigned int bus, unsigned int devfn)
49 {
50 struct pci_dev *dev;
52 pci_for_each_dev(dev) {
53 if (dev->bus->number == bus && dev->devfn == devfn)
54 return dev;
55 }
56 return NULL;
57 }
59 /**
60 * pci_find_subsys - begin or continue searching for a PCI device by vendor/subvendor/device/subdevice id
61 * @vendor: PCI vendor id to match, or %PCI_ANY_ID to match all vendor ids
62 * @device: PCI device id to match, or %PCI_ANY_ID to match all device ids
63 * @ss_vendor: PCI subsystem vendor id to match, or %PCI_ANY_ID to match all vendor ids
64 * @ss_device: PCI subsystem device id to match, or %PCI_ANY_ID to match all device ids
65 * @from: Previous PCI device found in search, or %NULL for new search.
66 *
67 * Iterates through the list of known PCI devices. If a PCI device is
68 * found with a matching @vendor, @device, @ss_vendor and @ss_device, a pointer to its
69 * device structure is returned. Otherwise, %NULL is returned.
70 * A new search is initiated by passing %NULL to the @from argument.
71 * Otherwise if @from is not %NULL, searches continue from next device on the global list.
72 */
73 struct pci_dev *
74 pci_find_subsys(unsigned int vendor, unsigned int device,
75 unsigned int ss_vendor, unsigned int ss_device,
76 const struct pci_dev *from)
77 {
78 struct list_head *n = from ? from->global_list.next : pci_devices.next;
80 while (n != &pci_devices) {
81 struct pci_dev *dev = pci_dev_g(n);
82 if ((vendor == PCI_ANY_ID || dev->vendor == vendor) &&
83 (device == PCI_ANY_ID || dev->device == device) &&
84 (ss_vendor == PCI_ANY_ID || dev->subsystem_vendor == ss_vendor) &&
85 (ss_device == PCI_ANY_ID || dev->subsystem_device == ss_device))
86 return dev;
87 n = n->next;
88 }
89 return NULL;
90 }
93 /**
94 * pci_find_device - begin or continue searching for a PCI device by vendor/device id
95 * @vendor: PCI vendor id to match, or %PCI_ANY_ID to match all vendor ids
96 * @device: PCI device id to match, or %PCI_ANY_ID to match all device ids
97 * @from: Previous PCI device found in search, or %NULL for new search.
98 *
99 * Iterates through the list of known PCI devices. If a PCI device is
100 * found with a matching @vendor and @device, a pointer to its device structure is
101 * returned. Otherwise, %NULL is returned.
102 * A new search is initiated by passing %NULL to the @from argument.
103 * Otherwise if @from is not %NULL, searches continue from next device on the global list.
104 */
105 struct pci_dev *
106 pci_find_device(unsigned int vendor, unsigned int device, const struct pci_dev *from)
107 {
108 return pci_find_subsys(vendor, device, PCI_ANY_ID, PCI_ANY_ID, from);
109 }
112 /**
113 * pci_find_class - begin or continue searching for a PCI device by class
114 * @class: search for a PCI device with this class designation
115 * @from: Previous PCI device found in search, or %NULL for new search.
116 *
117 * Iterates through the list of known PCI devices. If a PCI device is
118 * found with a matching @class, a pointer to its device structure is
119 * returned. Otherwise, %NULL is returned.
120 * A new search is initiated by passing %NULL to the @from argument.
121 * Otherwise if @from is not %NULL, searches continue from next device
122 * on the global list.
123 */
124 struct pci_dev *
125 pci_find_class(unsigned int class, const struct pci_dev *from)
126 {
127 struct list_head *n = from ? from->global_list.next : pci_devices.next;
129 while (n != &pci_devices) {
130 struct pci_dev *dev = pci_dev_g(n);
131 if (dev->class == class)
132 return dev;
133 n = n->next;
134 }
135 return NULL;
136 }
138 /**
139 * pci_find_capability - query for devices' capabilities
140 * @dev: PCI device to query
141 * @cap: capability code
142 *
143 * Tell if a device supports a given PCI capability.
144 * Returns the address of the requested capability structure within the
145 * device's PCI configuration space or 0 in case the device does not
146 * support it. Possible values for @cap:
147 *
148 * %PCI_CAP_ID_PM Power Management
149 *
150 * %PCI_CAP_ID_AGP Accelerated Graphics Port
151 *
152 * %PCI_CAP_ID_VPD Vital Product Data
153 *
154 * %PCI_CAP_ID_SLOTID Slot Identification
155 *
156 * %PCI_CAP_ID_MSI Message Signalled Interrupts
157 *
158 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
159 *
160 * %PCI_CAP_ID_PCIX PCI-X
161 */
162 int
163 pci_find_capability(struct pci_dev *dev, int cap)
164 {
165 u16 status;
166 u8 pos, id;
167 int ttl = 48;
169 pci_read_config_word(dev, PCI_STATUS, &status);
170 if (!(status & PCI_STATUS_CAP_LIST))
171 return 0;
172 switch (dev->hdr_type) {
173 case PCI_HEADER_TYPE_NORMAL:
174 case PCI_HEADER_TYPE_BRIDGE:
175 pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &pos);
176 break;
177 case PCI_HEADER_TYPE_CARDBUS:
178 pci_read_config_byte(dev, PCI_CB_CAPABILITY_LIST, &pos);
179 break;
180 default:
181 return 0;
182 }
183 while (ttl-- && pos >= 0x40) {
184 pos &= ~3;
185 pci_read_config_byte(dev, pos + PCI_CAP_LIST_ID, &id);
186 if (id == 0xff)
187 break;
188 if (id == cap)
189 return pos;
190 pci_read_config_byte(dev, pos + PCI_CAP_LIST_NEXT, &pos);
191 }
192 return 0;
193 }
196 /**
197 * pci_find_parent_resource - return resource region of parent bus of given region
198 * @dev: PCI device structure contains resources to be searched
199 * @res: child resource record for which parent is sought
200 *
201 * For given resource region of given device, return the resource
202 * region of parent bus the given region is contained in or where
203 * it should be allocated from.
204 */
205 struct resource *
206 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
207 {
208 const struct pci_bus *bus = dev->bus;
209 int i;
210 struct resource *best = NULL;
212 for(i=0; i<4; i++) {
213 struct resource *r = bus->resource[i];
214 if (!r)
215 continue;
216 if (res->start && !(res->start >= r->start && res->end <= r->end))
217 continue; /* Not contained */
218 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
219 continue; /* Wrong type */
220 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
221 return r; /* Exact match */
222 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
223 best = r; /* Approximating prefetchable by non-prefetchable */
224 }
225 return best;
226 }
228 /**
229 * pci_set_power_state - Set the power state of a PCI device
230 * @dev: PCI device to be suspended
231 * @state: Power state we're entering
232 *
233 * Transition a device to a new power state, using the Power Management
234 * Capabilities in the device's config space.
235 *
236 * RETURN VALUE:
237 * -EINVAL if trying to enter a lower state than we're already in.
238 * 0 if we're already in the requested state.
239 * -EIO if device does not support PCI PM.
240 * 0 if we can successfully change the power state.
241 */
243 int
244 pci_set_power_state(struct pci_dev *dev, int state)
245 {
246 int pm;
247 u16 pmcsr;
249 /* bound the state we're entering */
250 if (state > 3) state = 3;
252 /* Validate current state:
253 * Can enter D0 from any state, but if we can only go deeper
254 * to sleep if we're already in a low power state
255 */
256 if (state > 0 && dev->current_state > state)
257 return -EINVAL;
258 else if (dev->current_state == state)
259 return 0; /* we're already there */
261 /* find PCI PM capability in list */
262 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
264 /* abort if the device doesn't support PM capabilities */
265 if (!pm) return -EIO;
267 /* check if this device supports the desired state */
268 if (state == 1 || state == 2) {
269 u16 pmc;
270 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
271 if (state == 1 && !(pmc & PCI_PM_CAP_D1)) return -EIO;
272 else if (state == 2 && !(pmc & PCI_PM_CAP_D2)) return -EIO;
273 }
275 /* If we're in D3, force entire word to 0.
276 * This doesn't affect PME_Status, disables PME_En, and
277 * sets PowerState to 0.
278 */
279 if (dev->current_state >= 3)
280 pmcsr = 0;
281 else {
282 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
283 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
284 pmcsr |= state;
285 }
287 /* enter specified state */
288 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
290 /* Mandatory power management transition delays */
291 /* see PCI PM 1.1 5.6.1 table 18 */
292 if(state == 3 || dev->current_state == 3)
293 mdelay(10);
294 else if(state == 2 || dev->current_state == 2)
295 udelay(200);
296 dev->current_state = state;
298 return 0;
299 }
301 /**
302 * pci_save_state - save the PCI configuration space of a device before suspending
303 * @dev: - PCI device that we're dealing with
304 * @buffer: - buffer to hold config space context
305 *
306 * @buffer must be large enough to hold the entire PCI 2.2 config space
307 * (>= 64 bytes).
308 */
309 int
310 pci_save_state(struct pci_dev *dev, u32 *buffer)
311 {
312 int i;
313 if (buffer) {
314 /* XXX: 100% dword access ok here? */
315 for (i = 0; i < 16; i++)
316 pci_read_config_dword(dev, i * 4,&buffer[i]);
317 }
318 return 0;
319 }
321 /**
322 * pci_restore_state - Restore the saved state of a PCI device
323 * @dev: - PCI device that we're dealing with
324 * @buffer: - saved PCI config space
325 *
326 */
327 int
328 pci_restore_state(struct pci_dev *dev, u32 *buffer)
329 {
330 int i;
332 if (buffer) {
333 for (i = 0; i < 16; i++)
334 pci_write_config_dword(dev,i * 4, buffer[i]);
335 }
336 /*
337 * otherwise, write the context information we know from bootup.
338 * This works around a problem where warm-booting from Windows
339 * combined with a D3(hot)->D0 transition causes PCI config
340 * header data to be forgotten.
341 */
342 else {
343 for (i = 0; i < 6; i ++)
344 pci_write_config_dword(dev,
345 PCI_BASE_ADDRESS_0 + (i * 4),
346 dev->resource[i].start);
347 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
348 }
349 return 0;
350 }
352 /**
353 * pci_enable_device_bars - Initialize some of a device for use
354 * @dev: PCI device to be initialized
355 * @bars: bitmask of BAR's that must be configured
356 *
357 * Initialize device before it's used by a driver. Ask low-level code
358 * to enable selected I/O and memory resources. Wake up the device if it
359 * was suspended. Beware, this function can fail.
360 */
362 int
363 pci_enable_device_bars(struct pci_dev *dev, int bars)
364 {
365 int err;
367 pci_set_power_state(dev, 0);
368 if ((err = pcibios_enable_device(dev, bars)) < 0)
369 return err;
370 return 0;
371 }
373 /**
374 * pci_enable_device - Initialize device before it's used by a driver.
375 * @dev: PCI device to be initialized
376 *
377 * Initialize device before it's used by a driver. Ask low-level code
378 * to enable I/O and memory. Wake up the device if it was suspended.
379 * Beware, this function can fail.
380 */
381 int
382 pci_enable_device(struct pci_dev *dev)
383 {
384 return pci_enable_device_bars(dev, 0x3F);
385 }
387 /**
388 * pci_disable_device - Disable PCI device after use
389 * @dev: PCI device to be disabled
390 *
391 * Signal to the system that the PCI device is not in use by the system
392 * anymore. This only involves disabling PCI bus-mastering, if active.
393 */
394 void
395 pci_disable_device(struct pci_dev *dev)
396 {
397 u16 pci_command;
399 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
400 if (pci_command & PCI_COMMAND_MASTER) {
401 pci_command &= ~PCI_COMMAND_MASTER;
402 pci_write_config_word(dev, PCI_COMMAND, pci_command);
403 }
404 }
406 /**
407 * pci_enable_wake - enable device to generate PME# when suspended
408 * @dev: - PCI device to operate on
409 * @state: - Current state of device.
410 * @enable: - Flag to enable or disable generation
411 *
412 * Set the bits in the device's PM Capabilities to generate PME# when
413 * the system is suspended.
414 *
415 * -EIO is returned if device doesn't have PM Capabilities.
416 * -EINVAL is returned if device supports it, but can't generate wake events.
417 * 0 if operation is successful.
418 *
419 */
420 int pci_enable_wake(struct pci_dev *dev, u32 state, int enable)
421 {
422 int pm;
423 u16 value;
425 /* find PCI PM capability in list */
426 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
428 /* If device doesn't support PM Capabilities, but request is to disable
429 * wake events, it's a nop; otherwise fail */
430 if (!pm)
431 return enable ? -EIO : 0;
433 /* Check device's ability to generate PME# */
434 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
436 value &= PCI_PM_CAP_PME_MASK;
437 value >>= ffs(value); /* First bit of mask */
439 /* Check if it can generate PME# from requested state. */
440 if (!value || !(value & (1 << state)))
441 return enable ? -EINVAL : 0;
443 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
445 /* Clear PME_Status by writing 1 to it and enable PME# */
446 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
448 if (!enable)
449 value &= ~PCI_PM_CTRL_PME_ENABLE;
451 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
453 return 0;
454 }
456 int
457 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
458 {
459 u8 pin;
461 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
462 if (!pin)
463 return -1;
464 pin--;
465 while (dev->bus->self) {
466 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
467 dev = dev->bus->self;
468 }
469 *bridge = dev;
470 return pin;
471 }
473 /**
474 * pci_release_region - Release a PCI bar
475 * @pdev: PCI device whose resources were previously reserved by pci_request_region
476 * @bar: BAR to release
477 *
478 * Releases the PCI I/O and memory resources previously reserved by a
479 * successful call to pci_request_region. Call this function only
480 * after all use of the PCI regions has ceased.
481 */
482 void pci_release_region(struct pci_dev *pdev, int bar)
483 {
484 if (pci_resource_len(pdev, bar) == 0)
485 return;
486 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
487 release_region(pci_resource_start(pdev, bar),
488 pci_resource_len(pdev, bar));
489 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
490 release_mem_region(pci_resource_start(pdev, bar),
491 pci_resource_len(pdev, bar));
492 }
494 /**
495 * pci_request_region - Reserved PCI I/O and memory resource
496 * @pdev: PCI device whose resources are to be reserved
497 * @bar: BAR to be reserved
498 * @res_name: Name to be associated with resource.
499 *
500 * Mark the PCI region associated with PCI device @pdev BR @bar as
501 * being reserved by owner @res_name. Do not access any
502 * address inside the PCI regions unless this call returns
503 * successfully.
504 *
505 * Returns 0 on success, or %EBUSY on error. A warning
506 * message is also printed on failure.
507 */
508 int pci_request_region(struct pci_dev *pdev, int bar, char *res_name)
509 {
510 if (pci_resource_len(pdev, bar) == 0)
511 return 0;
513 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
514 if (!request_region(pci_resource_start(pdev, bar),
515 pci_resource_len(pdev, bar), res_name))
516 goto err_out;
517 }
518 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
519 if (!request_mem_region(pci_resource_start(pdev, bar),
520 pci_resource_len(pdev, bar), res_name))
521 goto err_out;
522 }
524 return 0;
526 err_out:
527 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
528 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
529 bar + 1, /* PCI BAR # */
530 pci_resource_len(pdev, bar), pci_resource_start(pdev, bar),
531 pdev->slot_name);
532 return -EBUSY;
533 }
536 /**
537 * pci_release_regions - Release reserved PCI I/O and memory resources
538 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
539 *
540 * Releases all PCI I/O and memory resources previously reserved by a
541 * successful call to pci_request_regions. Call this function only
542 * after all use of the PCI regions has ceased.
543 */
545 void pci_release_regions(struct pci_dev *pdev)
546 {
547 int i;
549 for (i = 0; i < 6; i++)
550 pci_release_region(pdev, i);
551 }
553 /**
554 * pci_request_regions - Reserved PCI I/O and memory resources
555 * @pdev: PCI device whose resources are to be reserved
556 * @res_name: Name to be associated with resource.
557 *
558 * Mark all PCI regions associated with PCI device @pdev as
559 * being reserved by owner @res_name. Do not access any
560 * address inside the PCI regions unless this call returns
561 * successfully.
562 *
563 * Returns 0 on success, or %EBUSY on error. A warning
564 * message is also printed on failure.
565 */
566 int pci_request_regions(struct pci_dev *pdev, char *res_name)
567 {
568 int i;
570 for (i = 0; i < 6; i++)
571 if(pci_request_region(pdev, i, res_name))
572 goto err_out;
573 return 0;
575 err_out:
576 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
577 pci_resource_flags(pdev, i) & IORESOURCE_IO ? "I/O" : "mem",
578 i + 1, /* PCI BAR # */
579 pci_resource_len(pdev, i), pci_resource_start(pdev, i),
580 pdev->slot_name);
581 while(--i >= 0)
582 pci_release_region(pdev, i);
584 return -EBUSY;
585 }
588 /*
589 * Registration of PCI drivers and handling of hot-pluggable devices.
590 */
592 static LIST_HEAD(pci_drivers);
594 /**
595 * pci_match_device - Tell if a PCI device structure has a matching PCI device id structure
596 * @ids: array of PCI device id structures to search in
597 * @dev: the PCI device structure to match against
598 *
599 * Used by a driver to check whether a PCI device present in the
600 * system is in its list of supported devices.Returns the matching
601 * pci_device_id structure or %NULL if there is no match.
602 */
603 const struct pci_device_id *
604 pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev)
605 {
606 while (ids->vendor || ids->subvendor || ids->class_mask) {
607 if ((ids->vendor == PCI_ANY_ID || ids->vendor == dev->vendor) &&
608 (ids->device == PCI_ANY_ID || ids->device == dev->device) &&
609 (ids->subvendor == PCI_ANY_ID || ids->subvendor == dev->subsystem_vendor) &&
610 (ids->subdevice == PCI_ANY_ID || ids->subdevice == dev->subsystem_device) &&
611 !((ids->class ^ dev->class) & ids->class_mask))
612 return ids;
613 ids++;
614 }
615 return NULL;
616 }
618 #if 0 /* NOT IN XEN */
619 static int pci_announce_device(struct pci_driver *drv, struct pci_dev *dev)
620 int pci_register_driver(struct pci_driver *drv)
621 void pci_unregister_driver(struct pci_driver *drv)
622 #endif
624 #ifdef CONFIG_HOTPLUG
626 #ifndef FALSE
627 #define FALSE (0)
628 #define TRUE (!FALSE)
629 #endif
631 static void
632 run_sbin_hotplug(struct pci_dev *pdev, int insert)
633 {
634 int i;
635 char *argv[3], *envp[8];
636 char id[20], sub_id[24], bus_id[24], class_id[20];
638 if (!hotplug_path[0])
639 return;
641 sprintf(class_id, "PCI_CLASS=%04X", pdev->class);
642 sprintf(id, "PCI_ID=%04X:%04X", pdev->vendor, pdev->device);
643 sprintf(sub_id, "PCI_SUBSYS_ID=%04X:%04X", pdev->subsystem_vendor, pdev->subsystem_device);
644 sprintf(bus_id, "PCI_SLOT_NAME=%s", pdev->slot_name);
646 i = 0;
647 argv[i++] = hotplug_path;
648 argv[i++] = "pci";
649 argv[i] = 0;
651 i = 0;
652 /* minimal command environment */
653 envp[i++] = "HOME=/";
654 envp[i++] = "PATH=/sbin:/bin:/usr/sbin:/usr/bin";
656 /* other stuff we want to pass to /sbin/hotplug */
657 envp[i++] = class_id;
658 envp[i++] = id;
659 envp[i++] = sub_id;
660 envp[i++] = bus_id;
661 if (insert)
662 envp[i++] = "ACTION=add";
663 else
664 envp[i++] = "ACTION=remove";
665 envp[i] = 0;
667 call_usermodehelper (argv [0], argv, envp);
668 }
670 /**
671 * pci_announce_device_to_drivers - tell the drivers a new device has appeared
672 * @dev: the device that has shown up
673 *
674 * Notifys the drivers that a new device has appeared, and also notifys
675 * userspace through /sbin/hotplug.
676 */
677 void
678 pci_announce_device_to_drivers(struct pci_dev *dev)
679 {
680 struct list_head *ln;
682 for(ln=pci_drivers.next; ln != &pci_drivers; ln=ln->next) {
683 struct pci_driver *drv = list_entry(ln, struct pci_driver, node);
684 if (drv->remove && pci_announce_device(drv, dev))
685 break;
686 }
688 /* notify userspace of new hotplug device */
689 run_sbin_hotplug(dev, TRUE);
690 }
692 /**
693 * pci_insert_device - insert a hotplug device
694 * @dev: the device to insert
695 * @bus: where to insert it
696 *
697 * Add a new device to the device lists and notify userspace (/sbin/hotplug).
698 */
699 void
700 pci_insert_device(struct pci_dev *dev, struct pci_bus *bus)
701 {
702 list_add_tail(&dev->bus_list, &bus->devices);
703 list_add_tail(&dev->global_list, &pci_devices);
704 #ifdef CONFIG_PROC_FS
705 pci_proc_attach_device(dev);
706 #endif
707 pci_announce_device_to_drivers(dev);
708 }
710 static void
711 pci_free_resources(struct pci_dev *dev)
712 {
713 int i;
715 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
716 struct resource *res = dev->resource + i;
717 if (res->parent)
718 release_resource(res);
719 }
720 }
722 /**
723 * pci_remove_device - remove a hotplug device
724 * @dev: the device to remove
725 *
726 * Delete the device structure from the device lists and
727 * notify userspace (/sbin/hotplug).
728 */
729 void
730 pci_remove_device(struct pci_dev *dev)
731 {
732 if (dev->driver) {
733 if (dev->driver->remove)
734 dev->driver->remove(dev);
735 dev->driver = NULL;
736 }
737 list_del(&dev->bus_list);
738 list_del(&dev->global_list);
739 pci_free_resources(dev);
740 #ifdef CONFIG_PROC_FS
741 pci_proc_detach_device(dev);
742 #endif
744 /* notify userspace of hotplug device removal */
745 run_sbin_hotplug(dev, FALSE);
746 }
748 #endif
750 static struct pci_driver pci_compat_driver = {
751 name: "compat"
752 };
754 /**
755 * pci_dev_driver - get the pci_driver of a device
756 * @dev: the device to query
757 *
758 * Returns the appropriate pci_driver structure or %NULL if there is no
759 * registered driver for the device.
760 */
761 struct pci_driver *
762 pci_dev_driver(const struct pci_dev *dev)
763 {
764 if (dev->driver)
765 return dev->driver;
766 else {
767 int i;
768 for(i=0; i<=PCI_ROM_RESOURCE; i++)
769 if (dev->resource[i].flags & IORESOURCE_BUSY)
770 return &pci_compat_driver;
771 }
772 return NULL;
773 }
776 /*
777 * This interrupt-safe spinlock protects all accesses to PCI
778 * configuration space.
779 */
781 static spinlock_t pci_lock = SPIN_LOCK_UNLOCKED;
783 /*
784 * Wrappers for all PCI configuration access functions. They just check
785 * alignment, do locking and call the low-level functions pointed to
786 * by pci_dev->ops.
787 */
789 #define PCI_byte_BAD 0
790 #define PCI_word_BAD (pos & 1)
791 #define PCI_dword_BAD (pos & 3)
793 #define PCI_OP(rw,size,type) \
794 int pci_##rw##_config_##size (struct pci_dev *dev, int pos, type value) \
795 { \
796 int res; \
797 unsigned long flags; \
798 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
799 spin_lock_irqsave(&pci_lock, flags); \
800 res = dev->bus->ops->rw##_##size(dev, pos, value); \
801 spin_unlock_irqrestore(&pci_lock, flags); \
802 return res; \
803 }
805 PCI_OP(read, byte, u8 *)
806 PCI_OP(read, word, u16 *)
807 PCI_OP(read, dword, u32 *)
808 PCI_OP(write, byte, u8)
809 PCI_OP(write, word, u16)
810 PCI_OP(write, dword, u32)
812 /**
813 * pci_set_master - enables bus-mastering for device dev
814 * @dev: the PCI device to enable
815 *
816 * Enables bus-mastering on the device and calls pcibios_set_master()
817 * to do the needed arch specific settings.
818 */
819 void
820 pci_set_master(struct pci_dev *dev)
821 {
822 u16 cmd;
824 pci_read_config_word(dev, PCI_COMMAND, &cmd);
825 if (! (cmd & PCI_COMMAND_MASTER)) {
826 DBG("PCI: Enabling bus mastering for device %s\n", dev->slot_name);
827 cmd |= PCI_COMMAND_MASTER;
828 pci_write_config_word(dev, PCI_COMMAND, cmd);
829 }
830 pcibios_set_master(dev);
831 }
833 #ifndef HAVE_ARCH_PCI_MWI
834 /* This can be overridden by arch code. */
835 u8 pci_cache_line_size = L1_CACHE_BYTES >> 2;
837 /**
838 * pci_generic_prep_mwi - helper function for pci_set_mwi
839 * @dev: the PCI device for which MWI is enabled
840 *
841 * Helper function for implementation the arch-specific pcibios_set_mwi
842 * function. Originally copied from drivers/net/acenic.c.
843 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
844 *
845 * RETURNS: An appriopriate -ERRNO error value on eror, or zero for success.
846 */
847 static int
848 pci_generic_prep_mwi(struct pci_dev *dev)
849 {
850 u8 cacheline_size;
852 if (!pci_cache_line_size)
853 return -EINVAL; /* The system doesn't support MWI. */
855 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
856 equal to or multiple of the right value. */
857 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
858 if (cacheline_size >= pci_cache_line_size &&
859 (cacheline_size % pci_cache_line_size) == 0)
860 return 0;
862 /* Write the correct value. */
863 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
864 /* Read it back. */
865 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
866 if (cacheline_size == pci_cache_line_size)
867 return 0;
869 printk(KERN_WARNING "PCI: cache line size of %d is not supported "
870 "by device %s\n", pci_cache_line_size << 2, dev->slot_name);
872 return -EINVAL;
873 }
874 #endif /* !HAVE_ARCH_PCI_MWI */
876 /**
877 * pci_set_mwi - enables memory-write-invalidate PCI transaction
878 * @dev: the PCI device for which MWI is enabled
879 *
880 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
881 * and then calls @pcibios_set_mwi to do the needed arch specific
882 * operations or a generic mwi-prep function.
883 *
884 * RETURNS: An appriopriate -ERRNO error value on eror, or zero for success.
885 */
886 int
887 pci_set_mwi(struct pci_dev *dev)
888 {
889 int rc;
890 u16 cmd;
892 #ifdef HAVE_ARCH_PCI_MWI
893 rc = pcibios_prep_mwi(dev);
894 #else
895 rc = pci_generic_prep_mwi(dev);
896 #endif
898 if (rc)
899 return rc;
901 pci_read_config_word(dev, PCI_COMMAND, &cmd);
902 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
903 DBG("PCI: Enabling Mem-Wr-Inval for device %s\n", dev->slot_name);
904 cmd |= PCI_COMMAND_INVALIDATE;
905 pci_write_config_word(dev, PCI_COMMAND, cmd);
906 }
908 return 0;
909 }
911 /**
912 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
913 * @dev: the PCI device to disable
914 *
915 * Disables PCI Memory-Write-Invalidate transaction on the device
916 */
917 void
918 pci_clear_mwi(struct pci_dev *dev)
919 {
920 u16 cmd;
922 pci_read_config_word(dev, PCI_COMMAND, &cmd);
923 if (cmd & PCI_COMMAND_INVALIDATE) {
924 cmd &= ~PCI_COMMAND_INVALIDATE;
925 pci_write_config_word(dev, PCI_COMMAND, cmd);
926 }
927 }
929 #if 0 /* NOT IN XEN */
930 int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
931 int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask)
932 #endif
934 /*
935 * Translate the low bits of the PCI base
936 * to the resource type
937 */
938 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
939 {
940 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
941 return IORESOURCE_IO;
943 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
944 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
946 return IORESOURCE_MEM;
947 }
949 /*
950 * Find the extent of a PCI decode, do sanity checks.
951 */
952 static u32 pci_size(u32 base, u32 maxbase, unsigned long mask)
953 {
954 u32 size = mask & maxbase; /* Find the significant bits */
955 if (!size)
956 return 0;
957 size = size & ~(size-1); /* Get the lowest of them to find the decode size */
958 size -= 1; /* extent = size - 1 */
959 if (base == maxbase && ((base | size) & mask) != mask)
960 return 0; /* base == maxbase can be valid only
961 if the BAR has been already
962 programmed with all 1s */
963 return size;
964 }
966 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
967 {
968 unsigned int pos, reg, next;
969 u32 l, sz;
970 struct resource *res;
972 for(pos=0; pos<howmany; pos = next) {
973 next = pos+1;
974 res = &dev->resource[pos];
975 res->name = dev->name;
976 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
977 pci_read_config_dword(dev, reg, &l);
978 pci_write_config_dword(dev, reg, ~0);
979 pci_read_config_dword(dev, reg, &sz);
980 pci_write_config_dword(dev, reg, l);
981 if (!sz || sz == 0xffffffff)
982 continue;
983 if (l == 0xffffffff)
984 l = 0;
985 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
986 sz = pci_size(l, sz, PCI_BASE_ADDRESS_MEM_MASK);
987 if (!sz)
988 continue;
989 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
990 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
991 } else {
992 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
993 if (!sz)
994 continue;
995 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
996 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
997 }
998 res->end = res->start + (unsigned long) sz;
999 res->flags |= pci_calc_resource_flags(l);
1000 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
1001 == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
1002 pci_read_config_dword(dev, reg+4, &l);
1003 next++;
1004 #if BITS_PER_LONG == 64
1005 res->start |= ((unsigned long) l) << 32;
1006 res->end = res->start + sz;
1007 pci_write_config_dword(dev, reg+4, ~0);
1008 pci_read_config_dword(dev, reg+4, &sz);
1009 pci_write_config_dword(dev, reg+4, l);
1010 if (~sz)
1011 res->end = res->start + 0xffffffff +
1012 (((unsigned long) ~sz) << 32);
1013 #else
1014 if (l) {
1015 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", dev->slot_name);
1016 res->start = 0;
1017 res->flags = 0;
1018 continue;
1020 #endif
1023 if (rom) {
1024 dev->rom_base_reg = rom;
1025 res = &dev->resource[PCI_ROM_RESOURCE];
1026 res->name = dev->name;
1027 pci_read_config_dword(dev, rom, &l);
1028 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
1029 pci_read_config_dword(dev, rom, &sz);
1030 pci_write_config_dword(dev, rom, l);
1031 if (l == 0xffffffff)
1032 l = 0;
1033 if (sz && sz != 0xffffffff) {
1034 sz = pci_size(l, sz, PCI_ROM_ADDRESS_MASK);
1035 if (!sz)
1036 return;
1037 res->flags = (l & PCI_ROM_ADDRESS_ENABLE) |
1038 IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
1039 res->start = l & PCI_ROM_ADDRESS_MASK;
1040 res->end = res->start + (unsigned long) sz;
1045 void __devinit pci_read_bridge_bases(struct pci_bus *child)
1047 struct pci_dev *dev = child->self;
1048 u8 io_base_lo, io_limit_lo;
1049 u16 mem_base_lo, mem_limit_lo;
1050 unsigned long base, limit;
1051 struct resource *res;
1052 int i;
1054 if (!dev) /* It's a host bus, nothing to read */
1055 return;
1057 if (dev->transparent) {
1058 printk("Transparent bridge - %s\n", dev->name);
1059 for(i = 0; i < 4; i++)
1060 child->resource[i] = child->parent->resource[i];
1061 return;
1064 for(i=0; i<3; i++)
1065 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
1067 res = child->resource[0];
1068 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1069 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
1070 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
1071 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
1073 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
1074 u16 io_base_hi, io_limit_hi;
1075 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
1076 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
1077 base |= (io_base_hi << 16);
1078 limit |= (io_limit_hi << 16);
1081 if (base && base <= limit) {
1082 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
1083 res->start = base;
1084 res->end = limit + 0xfff;
1087 res = child->resource[1];
1088 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
1089 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
1090 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
1091 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
1092 if (base && base <= limit) {
1093 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
1094 res->start = base;
1095 res->end = limit + 0xfffff;
1098 res = child->resource[2];
1099 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
1100 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
1101 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
1102 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
1104 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
1105 u32 mem_base_hi, mem_limit_hi;
1106 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
1107 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
1108 #if BITS_PER_LONG == 64
1109 base |= ((long) mem_base_hi) << 32;
1110 limit |= ((long) mem_limit_hi) << 32;
1111 #else
1112 if (mem_base_hi || mem_limit_hi) {
1113 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for %s\n", child->name);
1114 return;
1116 #endif
1118 if (base && base <= limit) {
1119 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
1120 res->start = base;
1121 res->end = limit + 0xfffff;
1125 static struct pci_bus * __devinit pci_alloc_bus(void)
1127 struct pci_bus *b;
1129 b = xmalloc(struct pci_bus);
1130 if (b) {
1131 memset(b, 0, sizeof(*b));
1132 INIT_LIST_HEAD(&b->children);
1133 INIT_LIST_HEAD(&b->devices);
1135 return b;
1138 struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
1140 struct pci_bus *child;
1141 int i;
1143 /*
1144 * Allocate a new bus, and inherit stuff from the parent..
1145 */
1146 child = pci_alloc_bus();
1148 list_add_tail(&child->node, &parent->children);
1149 child->self = dev;
1150 dev->subordinate = child;
1151 child->parent = parent;
1152 child->ops = parent->ops;
1153 child->sysdata = parent->sysdata;
1155 /*
1156 * Set up the primary, secondary and subordinate
1157 * bus numbers.
1158 */
1159 child->number = child->secondary = busnr;
1160 child->primary = parent->secondary;
1161 child->subordinate = 0xff;
1163 /* Set up default resource pointers and names.. */
1164 for (i = 0; i < 4; i++) {
1165 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
1166 child->resource[i]->name = child->name;
1169 return child;
1172 /*
1173 * If it's a bridge, configure it and scan the bus behind it.
1174 * For CardBus bridges, we don't scan behind as the devices will
1175 * be handled by the bridge driver itself.
1177 * We need to process bridges in two passes -- first we scan those
1178 * already configured by the BIOS and after we are done with all of
1179 * them, we proceed to assigning numbers to the remaining buses in
1180 * order to avoid overlaps between old and new bus numbers.
1181 */
1182 static int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
1184 unsigned int buses;
1185 unsigned short cr;
1186 struct pci_bus *child;
1187 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1189 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1190 DBG("Scanning behind PCI bridge %s, config %06x, pass %d\n", dev->slot_name, buses & 0xffffff, pass);
1191 if ((buses & 0xffff00) && !pcibios_assign_all_busses()) {
1192 /*
1193 * Bus already configured by firmware, process it in the first
1194 * pass and just note the configuration.
1195 */
1196 if (pass)
1197 return max;
1198 child = pci_add_new_bus(bus, dev, 0);
1199 child->primary = buses & 0xFF;
1200 child->secondary = (buses >> 8) & 0xFF;
1201 child->subordinate = (buses >> 16) & 0xFF;
1202 child->number = child->secondary;
1203 if (!is_cardbus) {
1204 unsigned int cmax = pci_do_scan_bus(child);
1205 if (cmax > max) max = cmax;
1206 } else {
1207 unsigned int cmax = child->subordinate;
1208 if (cmax > max) max = cmax;
1210 } else {
1211 /*
1212 * We need to assign a number to this bus which we always
1213 * do in the second pass. We also keep all address decoders
1214 * on the bridge disabled during scanning. FIXME: Why?
1215 */
1216 if (!pass)
1217 return max;
1218 pci_read_config_word(dev, PCI_COMMAND, &cr);
1219 pci_write_config_word(dev, PCI_COMMAND, 0x0000);
1220 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1222 child = pci_add_new_bus(bus, dev, ++max);
1223 buses = (buses & 0xff000000)
1224 | ((unsigned int)(child->primary) << 0)
1225 | ((unsigned int)(child->secondary) << 8)
1226 | ((unsigned int)(child->subordinate) << 16);
1227 /*
1228 * We need to blast all three values with a single write.
1229 */
1230 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1231 if (!is_cardbus) {
1232 /* Now we can scan all subordinate buses... */
1233 max = pci_do_scan_bus(child);
1234 } else {
1235 /*
1236 * For CardBus bridges, we leave 4 bus numbers
1237 * as cards with a PCI-to-PCI bridge can be
1238 * inserted later.
1239 */
1240 max += 3;
1242 /*
1243 * Set the subordinate bus number to its real value.
1244 */
1245 child->subordinate = max;
1246 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1247 pci_write_config_word(dev, PCI_COMMAND, cr);
1249 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
1250 return max;
1253 /*
1254 * Read interrupt line and base address registers.
1255 * The architecture-dependent code can tweak these, of course.
1256 */
1257 static void pci_read_irq(struct pci_dev *dev)
1259 unsigned char irq;
1261 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1262 if (irq)
1263 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1264 dev->irq = irq;
1267 /**
1268 * pci_setup_device - fill in class and map information of a device
1269 * @dev: the device structure to fill
1271 * Initialize the device structure with information about the device's
1272 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1273 * Called at initialisation of the PCI subsystem and by CardBus services.
1274 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
1275 * or CardBus).
1276 */
1277 int pci_setup_device(struct pci_dev * dev)
1279 u32 class;
1281 sprintf(dev->slot_name, "%02x:%02x.%d", dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
1282 sprintf(dev->name, "PCI device %04x:%04x", dev->vendor, dev->device);
1284 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1285 class >>= 8; /* upper 3 bytes */
1286 dev->class = class;
1287 class >>= 8;
1289 DBG("Found %02x:%02x [%04x/%04x] %06x %02x\n", dev->bus->number, dev->devfn, dev->vendor, dev->device, class, dev->hdr_type);
1291 /* "Unknown power state" */
1292 dev->current_state = 4;
1294 switch (dev->hdr_type) { /* header type */
1295 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1296 if (class == PCI_CLASS_BRIDGE_PCI)
1297 goto bad;
1298 pci_read_irq(dev);
1299 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1300 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1301 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1302 break;
1304 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1305 if (class != PCI_CLASS_BRIDGE_PCI)
1306 goto bad;
1307 /* The PCI-to-PCI bridge spec requires that subtractive
1308 decoding (i.e. transparent) bridge must have programming
1309 interface code of 0x01. */
1310 dev->transparent = ((dev->class & 0xff) == 1);
1311 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1312 break;
1314 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1315 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1316 goto bad;
1317 pci_read_irq(dev);
1318 pci_read_bases(dev, 1, 0);
1319 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1320 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1321 break;
1323 default: /* unknown header */
1324 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
1325 dev->slot_name, dev->hdr_type);
1326 return -1;
1328 bad:
1329 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
1330 dev->slot_name, class, dev->hdr_type);
1331 dev->class = PCI_CLASS_NOT_DEFINED;
1334 /* We found a fine healthy device, go go go... */
1335 return 0;
1338 /*
1339 * Read the config data for a PCI device, sanity-check it
1340 * and fill in the dev structure...
1341 */
1342 struct pci_dev * __devinit pci_scan_device(struct pci_dev *temp)
1344 struct pci_dev *dev;
1345 u32 l;
1347 if (pci_read_config_dword(temp, PCI_VENDOR_ID, &l))
1348 return NULL;
1350 /* some broken boards return 0 or ~0 if a slot is empty: */
1351 if (l == 0xffffffff || l == 0x00000000 || l == 0x0000ffff || l == 0xffff0000)
1352 return NULL;
1354 dev = xmalloc(struct pci_dev);
1355 if (!dev)
1356 return NULL;
1358 memcpy(dev, temp, sizeof(*dev));
1359 dev->vendor = l & 0xffff;
1360 dev->device = (l >> 16) & 0xffff;
1362 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1363 set this higher, assuming the system even supports it. */
1364 dev->dma_mask = 0xffffffff;
1365 if (pci_setup_device(dev) < 0) {
1366 xfree(dev);
1367 dev = NULL;
1369 return dev;
1372 struct pci_dev * __devinit pci_scan_slot(struct pci_dev *temp)
1374 struct pci_bus *bus = temp->bus;
1375 struct pci_dev *dev;
1376 struct pci_dev *first_dev = NULL;
1377 int func = 0;
1378 int is_multi = 0;
1379 u8 hdr_type;
1381 for (func = 0; func < 8; func++, temp->devfn++) {
1382 if (pci_read_config_byte(temp, PCI_HEADER_TYPE, &hdr_type))
1383 continue;
1384 temp->hdr_type = hdr_type & 0x7f;
1386 dev = pci_scan_device(temp);
1387 if (!pcibios_scan_all_fns(0,0) && func == 0) {
1388 if (!dev)
1389 break;
1390 } else {
1391 if (!dev)
1392 continue;
1393 is_multi = 1;
1396 pci_name_device(dev);
1397 if (!first_dev) {
1398 is_multi = hdr_type & 0x80;
1399 first_dev = dev;
1402 /*
1403 * Link the device to both the global PCI device chain and
1404 * the per-bus list of devices.
1405 */
1406 list_add_tail(&dev->global_list, &pci_devices);
1407 list_add_tail(&dev->bus_list, &bus->devices);
1409 /* Fix up broken headers */
1410 pci_fixup_device(PCI_FIXUP_HEADER, dev);
1412 /*
1413 * If this is a single function device
1414 * don't scan past the first function.
1415 */
1416 if (!is_multi)
1417 break;
1420 return first_dev;
1423 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
1425 unsigned int devfn, max, pass;
1426 struct list_head *ln;
1427 /* XEN MODIFICATION: Allocate dev0 on heap to avoid stack overflow. */
1428 struct pci_dev *dev, *dev0;
1430 DBG("Scanning bus %02x\n", bus->number);
1431 max = bus->secondary;
1433 /* Create a device template */
1434 dev0 = xmalloc(struct pci_dev);
1435 if(!dev0) {
1436 panic("Out of memory scanning PCI bus!\n");
1438 memset(dev0, 0, sizeof(struct pci_dev));
1439 dev0->bus = bus;
1440 dev0->sysdata = bus->sysdata;
1442 /* Go find them, Rover! */
1443 for (devfn = 0; devfn < 0x100; devfn += 8) {
1444 dev0->devfn = devfn;
1445 pci_scan_slot(dev0);
1447 xfree(dev0);
1449 /*
1450 * After performing arch-dependent fixup of the bus, look behind
1451 * all PCI-to-PCI bridges on this bus.
1452 */
1453 DBG("Fixups for bus %02x\n", bus->number);
1454 pcibios_fixup_bus(bus);
1455 for (pass=0; pass < 2; pass++)
1456 for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
1457 dev = pci_dev_b(ln);
1458 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1459 max = pci_scan_bridge(bus, dev, max, pass);
1462 /*
1463 * We've scanned the bus and so we know all about what's on
1464 * the other side of any bridges that may be on this bus plus
1465 * any devices.
1467 * Return how far we've got finding sub-buses.
1468 */
1469 DBG("Bus scan for %02x returning with max=%02x\n", bus->number, max);
1470 return max;
1473 int __devinit pci_bus_exists(const struct list_head *list, int nr)
1475 const struct list_head *l;
1477 for(l=list->next; l != list; l = l->next) {
1478 const struct pci_bus *b = pci_bus_b(l);
1479 if (b->number == nr || pci_bus_exists(&b->children, nr))
1480 return 1;
1482 return 0;
1485 struct pci_bus * __devinit pci_alloc_primary_bus(int bus)
1487 struct pci_bus *b;
1489 if (pci_bus_exists(&pci_root_buses, bus)) {
1490 /* If we already got to this bus through a different bridge, ignore it */
1491 DBG("PCI: Bus %02x already known\n", bus);
1492 return NULL;
1495 b = pci_alloc_bus();
1496 list_add_tail(&b->node, &pci_root_buses);
1498 b->number = b->secondary = bus;
1499 b->resource[0] = &ioport_resource;
1500 b->resource[1] = &iomem_resource;
1501 return b;
1504 struct pci_bus * __devinit pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
1506 struct pci_bus *b = pci_alloc_primary_bus(bus);
1507 if (b) {
1508 b->sysdata = sysdata;
1509 b->ops = ops;
1510 b->subordinate = pci_do_scan_bus(b);
1512 return b;
1515 #ifdef CONFIG_PM
1517 /*
1518 * PCI Power management..
1520 * This needs to be done centralized, so that we power manage PCI
1521 * devices in the right order: we should not shut down PCI bridges
1522 * before we've shut down the devices behind them, and we should
1523 * not wake up devices before we've woken up the bridge to the
1524 * device.. Eh?
1526 * We do not touch devices that don't have a driver that exports
1527 * a suspend/resume function. That is just too dangerous. If the default
1528 * PCI suspend/resume functions work for a device, the driver can
1529 * easily implement them (ie just have a suspend function that calls
1530 * the pci_set_power_state() function).
1531 */
1533 static int pci_pm_save_state_device(struct pci_dev *dev, u32 state)
1535 int error = 0;
1536 if (dev) {
1537 struct pci_driver *driver = dev->driver;
1538 if (driver && driver->save_state)
1539 error = driver->save_state(dev,state);
1541 return error;
1544 static int pci_pm_suspend_device(struct pci_dev *dev, u32 state)
1546 int error = 0;
1547 if (dev) {
1548 struct pci_driver *driver = dev->driver;
1549 if (driver && driver->suspend)
1550 error = driver->suspend(dev,state);
1552 return error;
1555 static int pci_pm_resume_device(struct pci_dev *dev)
1557 int error = 0;
1558 if (dev) {
1559 struct pci_driver *driver = dev->driver;
1560 if (driver && driver->resume)
1561 error = driver->resume(dev);
1563 return error;
1566 static int pci_pm_save_state_bus(struct pci_bus *bus, u32 state)
1568 struct pci_bus *i;
1569 int error = 0;
1571 list_for_each_entry(i, &bus->children, node) {
1572 error = pci_pm_save_state_bus(i, state);
1573 if (error) return error;
1575 list_for_each_entry(i, &bus->devices, node) {
1576 error = pci_pm_save_state_device(i, state);
1577 if (error) return error;
1579 return 0;
1582 static int pci_pm_suspend_bus(struct pci_bus *bus, u32 state)
1584 struct pci_bus *i;
1586 /* Walk the bus children list */
1587 list_for_each_entry(i, &bus->children, node)
1588 pci_pm_suspend_bus(i, state);
1590 /* Walk the device children list */
1591 list_for_each_entry(i, &bus->devices, node)
1592 pci_pm_suspend_device(i, state);
1593 return 0;
1596 static int pci_pm_resume_bus(struct pci_bus *bus)
1598 struct pci_bus *i;
1600 /* Walk the device children list */
1601 list_for_each_entry(i, &bus->devices, node)
1602 pci_pm_resume_device(i);
1604 /* And then walk the bus children */
1605 list_for_each_entry(i, &bus->children, node)
1606 pci_pm_resume_bus(i);
1607 return 0;
1610 static int pci_pm_save_state(u32 state)
1612 struct pci_bus *bus;
1613 int error = 0;
1615 list_for_each_entry(bus, &pci_root_buses, node) {
1616 error = pci_pm_save_state_bus(bus,state);
1617 if (!error)
1618 error = pci_pm_save_state_device(bus->self,state);
1620 return error;
1623 static int pci_pm_suspend(u32 state)
1625 struct pci_bus *bus;
1627 list_for_each_entry(bus, &pci_root_buses, node) {
1628 pci_pm_suspend_bus(bus,state);
1629 pci_pm_suspend_device(bus->self,state);
1631 return 0;
1634 int pci_pm_resume(void)
1636 struct pci_bus *bus;
1638 list_for_each_entry(bus, &pci_root_buses, node) {
1639 pci_pm_resume_device(bus->self);
1640 pci_pm_resume_bus(bus);
1642 return 0;
1645 static int
1646 pci_pm_callback(struct pm_dev *pm_device, pm_request_t rqst, void *data)
1648 int error = 0;
1650 switch (rqst) {
1651 case PM_SAVE_STATE:
1652 error = pci_pm_save_state((unsigned long)data);
1653 break;
1654 case PM_SUSPEND:
1655 error = pci_pm_suspend((unsigned long)data);
1656 break;
1657 case PM_RESUME:
1658 error = pci_pm_resume();
1659 break;
1660 default: break;
1662 return error;
1665 #endif
1667 /* NB. Xen doesn't include the pool allocator. */
1669 void __devinit pci_init(void)
1671 struct pci_dev *dev;
1673 pcibios_init();
1675 pci_for_each_dev(dev) {
1676 pci_fixup_device(PCI_FIXUP_FINAL, dev);
1679 #ifdef CONFIG_PM
1680 pm_register(PM_PCI_DEV, 0, pci_pm_callback);
1681 #endif
1684 static int __devinit pci_setup(char *str)
1686 while (str) {
1687 char *k = strchr(str, ',');
1688 if (k)
1689 *k++ = 0;
1690 if (*str && (str = pcibios_setup(str)) && *str) {
1691 /* PCI layer options should be handled here */
1692 printk(KERN_ERR "PCI: Unknown option `%s'\n", str);
1694 str = k;
1696 return 1;
1699 __setup("pci=", pci_setup);
1701 EXPORT_SYMBOL(pci_read_config_byte);
1702 EXPORT_SYMBOL(pci_read_config_word);
1703 EXPORT_SYMBOL(pci_read_config_dword);
1704 EXPORT_SYMBOL(pci_write_config_byte);
1705 EXPORT_SYMBOL(pci_write_config_word);
1706 EXPORT_SYMBOL(pci_write_config_dword);
1707 EXPORT_SYMBOL(pci_devices);
1708 EXPORT_SYMBOL(pci_root_buses);
1709 EXPORT_SYMBOL(pci_enable_device_bars);
1710 EXPORT_SYMBOL(pci_enable_device);
1711 EXPORT_SYMBOL(pci_disable_device);
1712 EXPORT_SYMBOL(pci_find_capability);
1713 EXPORT_SYMBOL(pci_release_regions);
1714 EXPORT_SYMBOL(pci_request_regions);
1715 EXPORT_SYMBOL(pci_release_region);
1716 EXPORT_SYMBOL(pci_request_region);
1717 EXPORT_SYMBOL(pci_find_class);
1718 EXPORT_SYMBOL(pci_find_device);
1719 EXPORT_SYMBOL(pci_find_slot);
1720 EXPORT_SYMBOL(pci_find_subsys);
1721 EXPORT_SYMBOL(pci_set_master);
1722 EXPORT_SYMBOL(pci_set_mwi);
1723 EXPORT_SYMBOL(pci_clear_mwi);
1724 EXPORT_SYMBOL(pci_set_dma_mask);
1725 EXPORT_SYMBOL(pci_dac_set_dma_mask);
1726 EXPORT_SYMBOL(pci_assign_resource);
1727 EXPORT_SYMBOL(pci_register_driver);
1728 EXPORT_SYMBOL(pci_unregister_driver);
1729 EXPORT_SYMBOL(pci_dev_driver);
1730 EXPORT_SYMBOL(pci_match_device);
1731 EXPORT_SYMBOL(pci_find_parent_resource);
1733 #ifdef CONFIG_HOTPLUG
1734 EXPORT_SYMBOL(pci_setup_device);
1735 EXPORT_SYMBOL(pci_insert_device);
1736 EXPORT_SYMBOL(pci_remove_device);
1737 EXPORT_SYMBOL(pci_announce_device_to_drivers);
1738 EXPORT_SYMBOL(pci_add_new_bus);
1739 EXPORT_SYMBOL(pci_do_scan_bus);
1740 EXPORT_SYMBOL(pci_scan_slot);
1741 EXPORT_SYMBOL(pci_scan_bus);
1742 EXPORT_SYMBOL(pci_scan_device);
1743 EXPORT_SYMBOL(pci_read_bridge_bases);
1744 #ifdef CONFIG_PROC_FS
1745 EXPORT_SYMBOL(pci_proc_attach_device);
1746 EXPORT_SYMBOL(pci_proc_detach_device);
1747 EXPORT_SYMBOL(pci_proc_attach_bus);
1748 EXPORT_SYMBOL(pci_proc_detach_bus);
1749 EXPORT_SYMBOL(proc_bus_pci_dir);
1750 #endif
1751 #endif
1753 EXPORT_SYMBOL(pci_set_power_state);
1754 EXPORT_SYMBOL(pci_save_state);
1755 EXPORT_SYMBOL(pci_restore_state);
1756 EXPORT_SYMBOL(pci_enable_wake);
1758 /* Obsolete functions */
1760 EXPORT_SYMBOL(pcibios_present);
1761 EXPORT_SYMBOL(pcibios_read_config_byte);
1762 EXPORT_SYMBOL(pcibios_read_config_word);
1763 EXPORT_SYMBOL(pcibios_read_config_dword);
1764 EXPORT_SYMBOL(pcibios_write_config_byte);
1765 EXPORT_SYMBOL(pcibios_write_config_word);
1766 EXPORT_SYMBOL(pcibios_write_config_dword);
1767 EXPORT_SYMBOL(pcibios_find_class);
1768 EXPORT_SYMBOL(pcibios_find_device);
1770 /* Quirk info */
1772 EXPORT_SYMBOL(isa_dma_bridge_buggy);
1773 EXPORT_SYMBOL(pci_pci_problems);