debuggers.hg

view tools/ioemu/hw/serial.c @ 16596:c0f7ba3aa9b2

ioemu: Include termios.h and sys/ioctl.h to get TIOCM_* definitions.
This is preferable to hard-coding them in the ioemu source file, or
including a Linux-specific header.
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Dec 07 12:48:36 2007 +0000 (2007-12-07)
parents ec61ca6cd55b
children 180e4a77e805
line source
1 /*
2 * QEMU 16550A UART emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
25 #include "vl.h"
26 #include <sys/time.h>
27 #include <time.h>
28 #include <assert.h>
29 #include <termios.h>
30 #include <sys/ioctl.h>
32 //#define DEBUG_SERIAL
34 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
36 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
37 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
38 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
39 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
41 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
42 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
44 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
45 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
46 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
47 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
48 #define UART_IIR_CTI 0x0C /* Character Timeout Indication */
50 #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */
51 #define UART_IIR_FE 0xC0 /* Fifo enabled */
53 /*
54 * These are the definitions for the Modem Control Register
55 */
56 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
57 #define UART_MCR_OUT2 0x08 /* Out2 complement */
58 #define UART_MCR_OUT1 0x04 /* Out1 complement */
59 #define UART_MCR_RTS 0x02 /* RTS complement */
60 #define UART_MCR_DTR 0x01 /* DTR complement */
62 /*
63 * These are the definitions for the Modem Status Register
64 */
65 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
66 #define UART_MSR_RI 0x40 /* Ring Indicator */
67 #define UART_MSR_DSR 0x20 /* Data Set Ready */
68 #define UART_MSR_CTS 0x10 /* Clear to Send */
69 #define UART_MSR_DDCD 0x08 /* Delta DCD */
70 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
71 #define UART_MSR_DDSR 0x02 /* Delta DSR */
72 #define UART_MSR_DCTS 0x01 /* Delta CTS */
73 #define UART_MSR_ANY_DELTA 0x0F /* Any of the msr delta bits */
75 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
76 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
77 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
78 #define UART_LSR_FE 0x08 /* Frame error indicator */
79 #define UART_LSR_PE 0x04 /* Parity error indicator */
80 #define UART_LSR_OE 0x02 /* Overrun error indicator */
81 #define UART_LSR_DR 0x01 /* Receiver data ready */
82 #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */
84 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
86 #define UART_FCR_ITL_1 0x00 /* 1 byte ITL */
87 #define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */
88 #define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */
89 #define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */
91 #define UART_FCR_DMS 0x08 /* DMA Mode Select */
92 #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */
93 #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */
94 #define UART_FCR_FE 0x01 /* FIFO Enable */
96 #define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */
98 #define XMIT_FIFO 0
99 #define RECV_FIFO 1
100 #define MAX_XMIT_RETRY 4
102 struct SerialFIFO {
103 uint8_t data[UART_FIFO_LENGTH];
104 uint8_t count;
105 uint8_t itl; /* Interrupt Trigger Level */
106 uint8_t tail;
107 uint8_t head;
108 } typedef SerialFIFO;
110 struct SerialState {
111 uint16_t divider;
112 uint8_t rbr; /* receive register */
113 uint8_t thr; /* transmit holding register */
114 uint8_t tsr; /* transmit shift register */
115 uint8_t ier;
116 uint8_t iir; /* read only */
117 uint8_t lcr;
118 uint8_t mcr;
119 uint8_t lsr; /* read only */
120 uint8_t msr; /* read only */
121 uint8_t scr;
122 uint8_t fcr;
123 /* NOTE: this hidden state is necessary for tx irq generation as
124 it can be reset while reading iir */
125 int thr_ipending;
126 SetIRQFunc *set_irq;
127 void *irq_opaque;
128 int irq;
129 CharDriverState *chr;
130 int last_break_enable;
131 target_ulong base;
132 int it_shift;
133 int tsr_retry;
135 uint64_t last_xmit_ts; /* Time when the last byte was successfully sent out of the tsr */
136 SerialFIFO recv_fifo;
137 SerialFIFO xmit_fifo;
139 struct QEMUTimer *fifo_timeout_timer;
140 int timeout_ipending; /* timeout interrupt pending state */
141 struct QEMUTimer *transmit_timer;
144 uint64_t char_transmit_time; /* time to transmit a char in ticks*/
145 int poll_msl;
147 struct QEMUTimer *modem_status_poll;
148 };
150 /* Rate limit serial requests so that e.g. grub on a serial console
151 doesn't kill dom0. Simple token bucket. If we get some actual
152 data from the user, instantly refil the bucket. */
154 /* How long it takes to generate a token, in microseconds. */
155 #define TOKEN_PERIOD 1000
156 /* Maximum and initial size of token bucket */
157 #define TOKENS_MAX 100000
159 static int tokens_avail;
161 static void fifo_clear(SerialState *s, int fifo) {
162 SerialFIFO *f = ( fifo ) ? &s->recv_fifo : &s->xmit_fifo;
163 memset(f->data, 0, UART_FIFO_LENGTH);
164 f->count = 0;
165 f->head = 0;
166 f->tail = 0;
167 }
169 static int fifo_put(SerialState *s, int fifo, uint8_t chr) {
170 SerialFIFO *f = ( fifo ) ? &s->recv_fifo : &s->xmit_fifo;
172 f->data[f->head++] = chr;
174 if (f->head == UART_FIFO_LENGTH)
175 f->head = 0;
176 f->count++;
178 tokens_avail = TOKENS_MAX;
180 return 1;
181 }
183 uint8_t fifo_get(SerialState *s, int fifo) {
184 SerialFIFO *f = ( fifo ) ? &s->recv_fifo : &s->xmit_fifo;
185 uint8_t c;
187 if( f->count == 0 )
188 return 0;
190 c = f->data[f->tail++];
191 if (f->tail == UART_FIFO_LENGTH)
192 f->tail = 0;
193 f->count--;
195 tokens_avail = TOKENS_MAX;
197 return c;
198 }
200 static void serial_update_irq(SerialState *s)
201 {
202 uint8_t tmp_iir = UART_IIR_NO_INT;
204 if (!s->ier) {
205 s->set_irq(s->irq_opaque, s->irq, 0);
206 return;
207 }
209 if ( ( s->ier & UART_IER_RLSI ) && (s->lsr & UART_LSR_INT_ANY ) ) {
210 tmp_iir = UART_IIR_RLSI;
211 } else if ( s->timeout_ipending ) {
212 tmp_iir = UART_IIR_CTI;
213 } else if ( ( s->ier & UART_IER_RDI ) && (s->lsr & UART_LSR_DR ) ) {
214 if ( !(s->iir & UART_FCR_FE) ) {
215 tmp_iir = UART_IIR_RDI;
216 } else if ( s->recv_fifo.count >= s->recv_fifo.itl ) {
217 tmp_iir = UART_IIR_RDI;
218 }
219 } else if ( (s->ier & UART_IER_THRI) && s->thr_ipending ) {
220 tmp_iir = UART_IIR_THRI;
221 } else if ( (s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA) ) {
222 tmp_iir = UART_IIR_MSI;
223 }
225 s->iir = tmp_iir | ( s->iir & 0xF0 );
227 if ( tmp_iir != UART_IIR_NO_INT ) {
228 s->set_irq(s->irq_opaque, s->irq, 1);
229 } else {
230 s->set_irq(s->irq_opaque, s->irq, 0);
231 }
232 }
234 static void serial_update_parameters(SerialState *s)
235 {
236 int speed, parity, data_bits, stop_bits, frame_size;
237 QEMUSerialSetParams ssp;
239 if (s->divider == 0)
240 return;
242 frame_size = 1;
243 if (s->lcr & 0x08) {
244 if (s->lcr & 0x10)
245 parity = 'E';
246 else
247 parity = 'O';
248 } else {
249 parity = 'N';
250 frame_size = 0;
251 }
252 if (s->lcr & 0x04)
253 stop_bits = 2;
254 else
255 stop_bits = 1;
257 data_bits = (s->lcr & 0x03) + 5;
258 frame_size += data_bits + stop_bits;
260 speed = 115200 / s->divider;
261 ssp.speed = speed;
262 ssp.parity = parity;
263 ssp.data_bits = data_bits;
264 ssp.stop_bits = stop_bits;
265 s->char_transmit_time = ( ticks_per_sec / speed ) * frame_size;
266 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
267 #if 0
268 printf("speed=%d parity=%c data=%d stop=%d\n",
269 speed, parity, data_bits, stop_bits);
270 #endif
271 }
273 static void serial_get_token(void)
274 {
275 static struct timeval last_refil_time;
276 static int started;
278 assert(tokens_avail >= 0);
279 if (!tokens_avail) {
280 struct timeval delta, now;
281 int generated;
283 if (!started) {
284 gettimeofday(&last_refil_time, NULL);
285 tokens_avail = TOKENS_MAX;
286 started = 1;
287 return;
288 }
289 retry:
290 gettimeofday(&now, NULL);
291 delta.tv_sec = now.tv_sec - last_refil_time.tv_sec;
292 delta.tv_usec = now.tv_usec - last_refil_time.tv_usec;
293 if (delta.tv_usec < 0) {
294 delta.tv_usec += 1000000;
295 delta.tv_sec--;
296 }
297 assert(delta.tv_usec >= 0 && delta.tv_sec >= 0);
298 if (delta.tv_usec < TOKEN_PERIOD) {
299 struct timespec ts;
300 /* Wait until at least one token is available. */
301 ts.tv_sec = TOKEN_PERIOD / 1000000;
302 ts.tv_nsec = (TOKEN_PERIOD % 1000000) * 1000;
303 while (nanosleep(&ts, &ts) < 0 && errno == EINTR)
304 ;
305 goto retry;
306 }
307 generated = (delta.tv_sec * 1000000) / TOKEN_PERIOD;
308 generated +=
309 ((delta.tv_sec * 1000000) % TOKEN_PERIOD + delta.tv_usec) / TOKEN_PERIOD;
310 assert(generated > 0);
312 last_refil_time.tv_usec += (generated * TOKEN_PERIOD) % 1000000;
313 last_refil_time.tv_sec += last_refil_time.tv_usec / 1000000;
314 last_refil_time.tv_usec %= 1000000;
315 last_refil_time.tv_sec += (generated * TOKEN_PERIOD) / 1000000;
316 if (generated > TOKENS_MAX)
317 generated = TOKENS_MAX;
318 tokens_avail = generated;
319 }
320 tokens_avail--;
321 }
323 static void serial_update_msl( SerialState *s )
324 {
325 uint8_t omsr;
326 int flags;
328 qemu_del_timer(s->modem_status_poll);
330 if ( qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP ) {
331 s->poll_msl = -1;
332 return;
333 }
335 omsr = s->msr;
337 s->msr = ( flags & TIOCM_CTS ) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
338 s->msr = ( flags & TIOCM_DSR ) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
339 s->msr = ( flags & TIOCM_CAR ) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
340 s->msr = ( flags & TIOCM_RI ) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
342 if ( s->msr != omsr ) {
343 /* Set delta bits */
344 s->msr = s->msr | ( ( s->msr >> 4 ) ^ ( omsr >> 4 ) );
345 /* UART_MSR_TERI only if change was from 1 -> 0 */
346 if ( ( s->msr & UART_MSR_TERI ) && !( omsr & UART_MSR_RI ) )
347 s->msr &= ~UART_MSR_TERI;
348 serial_update_irq(s);
349 }
351 /* The real 16550A apparently has a 250ns response latency to line status changes.
352 We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
354 if ( s->poll_msl )
355 qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + ticks_per_sec / 100);
356 }
358 static void serial_xmit(void *opaque) {
359 SerialState *s = opaque;
360 uint64_t new_xmit_ts = qemu_get_clock(vm_clock);
362 if ( s->tsr_retry == 0 ) {
363 if (s->fcr & UART_FCR_FE) {
364 s->tsr = fifo_get(s,XMIT_FIFO);
365 if ( !s->xmit_fifo.count )
366 s->lsr |= UART_LSR_THRE;
367 } else {
368 s->tsr = s->thr;
369 s->lsr |= UART_LSR_THRE;
370 }
371 }
373 if ( qemu_chr_write(s->chr, &s->tsr, 1) != 1 ) {
374 s->tsr_retry++;
375 if ( s->tsr_retry <= MAX_XMIT_RETRY ) {
376 qemu_mod_timer(s->transmit_timer, new_xmit_ts + s->char_transmit_time );
377 return;
378 }
379 }
381 s->tsr_retry = 0;
382 s->last_xmit_ts = qemu_get_clock(vm_clock);
384 if ( !(s->lsr & UART_LSR_THRE) )
385 qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time );
387 if ( s->lsr & UART_LSR_THRE ) {
388 s->lsr |= UART_LSR_TEMT;
389 s->thr_ipending = 1;
390 serial_update_irq(s);
391 }
392 }
395 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
396 {
397 SerialState *s = opaque;
399 addr &= 7;
400 #ifdef DEBUG_SERIAL
401 printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
402 #endif
403 switch(addr) {
404 default:
405 case 0:
406 if (s->lcr & UART_LCR_DLAB) {
407 s->divider = (s->divider & 0xff00) | val;
408 serial_update_parameters(s);
409 } else {
410 s->thr = (uint8_t) val;
411 if(s->fcr & UART_FCR_FE) {
412 fifo_put(s, XMIT_FIFO, s->thr);
413 s->thr_ipending = 0;
414 s->lsr &= ~UART_LSR_TEMT;
415 s->lsr &= ~UART_LSR_THRE;
416 serial_update_irq(s);
417 } else {
418 s->thr_ipending = 0;
419 s->lsr &= ~UART_LSR_THRE;
420 serial_update_irq(s);
421 }
422 serial_xmit(s);
423 }
424 break;
425 case 1:
426 if (s->lcr & UART_LCR_DLAB) {
427 s->divider = (s->divider & 0x00ff) | (val << 8);
428 serial_update_parameters(s);
429 } else {
430 s->ier = val & 0x0f;
431 /* If the backend device is a real serial port, turn polling of the modem
432 status lines on physical port on or off depending on UART_IER_MSI state */
433 if ( s->poll_msl >= 0 ) {
434 if ( s->ier & UART_IER_MSI ) {
435 s->poll_msl = 1;
436 serial_update_msl(s);
437 } else {
438 qemu_del_timer(s->modem_status_poll);
439 s->poll_msl = 0;
440 }
441 }
442 if (s->lsr & UART_LSR_THRE) {
443 s->thr_ipending = 1;
444 serial_update_irq(s);
445 }
446 }
447 break;
448 case 2:
449 val = val & 0xFF;
451 if ( s->fcr == val)
452 break;
454 /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
455 if ( (val ^ s->fcr) & UART_FCR_FE )
456 val |= UART_FCR_XFR | UART_FCR_RFR;
458 /* FIFO clear */
460 if ( val & UART_FCR_RFR ) {
461 qemu_del_timer(s->fifo_timeout_timer);
462 s->timeout_ipending=0;
463 fifo_clear(s,RECV_FIFO);
464 }
466 if ( val & UART_FCR_XFR ) {
467 fifo_clear(s,XMIT_FIFO);
468 }
470 if ( val & UART_FCR_FE ) {
471 s->iir |= UART_IIR_FE;
472 /* Set RECV_FIFO trigger Level */
473 switch ( val & 0xC0 ) {
474 case UART_FCR_ITL_1:
475 s->recv_fifo.itl = 1;
476 break;
477 case UART_FCR_ITL_2:
478 s->recv_fifo.itl = 4;
479 break;
480 case UART_FCR_ITL_3:
481 s->recv_fifo.itl = 8;
482 break;
483 case UART_FCR_ITL_4:
484 s->recv_fifo.itl = 14;
485 break;
486 }
487 } else
488 s->iir &= ~UART_IIR_FE;
490 /* Set fcr - or at least the bits in it that are supposed to "stick" */
491 s->fcr = val & 0xC9;
492 serial_update_irq(s);
493 break;
494 case 3:
495 {
496 int break_enable;
497 s->lcr = val;
498 serial_update_parameters(s);
499 break_enable = (val >> 6) & 1;
500 if (break_enable != s->last_break_enable) {
501 s->last_break_enable = break_enable;
502 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
503 &break_enable);
504 }
505 }
506 break;
507 case 4:
508 {
509 int flags;
510 int old_mcr = s->mcr;
511 s->mcr = val & 0x1f;
512 if ( val & UART_MCR_LOOP )
513 break;
515 if ( s->poll_msl >= 0 && old_mcr != s->mcr ) {
517 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
519 flags &= ~( TIOCM_RTS | TIOCM_DTR );
521 if ( val & UART_MCR_RTS )
522 flags |= TIOCM_RTS;
523 if ( val & UART_MCR_DTR )
524 flags |= TIOCM_DTR;
526 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
527 /* Update the modem status after a one-character-send wait-time, since there may be a response
528 from the device/computer at the other end of the serial line */
529 qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time );
530 }
531 }
532 break;
533 case 5:
534 break;
535 case 6:
536 break;
537 case 7:
538 s->scr = val;
539 break;
540 }
541 }
543 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
544 {
545 SerialState *s = opaque;
546 uint32_t ret;
548 addr &= 7;
549 switch(addr) {
550 default:
551 case 0:
552 if (s->lcr & UART_LCR_DLAB) {
553 ret = s->divider & 0xff;
554 } else {
555 if(s->fcr & UART_FCR_FE) {
556 ret = fifo_get(s,RECV_FIFO);
557 if ( s->recv_fifo.count == 0 )
558 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
559 else
560 qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4 );
561 s->timeout_ipending = 0;
562 } else {
563 ret = s->rbr;
564 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
565 }
566 serial_update_irq(s);
567 }
568 break;
569 case 1:
570 if (s->lcr & UART_LCR_DLAB) {
571 ret = (s->divider >> 8) & 0xff;
572 } else {
573 ret = s->ier;
574 }
575 break;
576 case 2:
577 ret = s->iir;
578 s->thr_ipending = 0;
579 serial_update_irq(s);
580 break;
581 case 3:
582 ret = s->lcr;
583 break;
584 case 4:
585 ret = s->mcr;
586 break;
587 case 5:
588 serial_get_token();
589 ret = s->lsr;
590 /* Clear break interrupt */
591 if ( s->lsr & UART_LSR_BI ) {
592 s->lsr &= ~UART_LSR_BI;
593 serial_update_irq(s);
594 }
595 break;
596 case 6:
597 serial_get_token();
598 if (s->mcr & UART_MCR_LOOP) {
599 /* in loopback, the modem output pins are connected to the
600 inputs */
601 ret = (s->mcr & 0x0c) << 4;
602 ret |= (s->mcr & 0x02) << 3;
603 ret |= (s->mcr & 0x01) << 5;
604 } else {
605 if ( s->poll_msl >= 0 )
606 serial_update_msl(s);
607 ret = s->msr;
608 /* Clear delta bits & msr int after read, if they were set */
609 if ( s->msr & UART_MSR_ANY_DELTA ) {
610 s->msr &= 0xF0;
611 serial_update_irq(s);
612 }
613 }
614 break;
615 case 7:
616 ret = s->scr;
617 break;
618 }
619 #ifdef DEBUG_SERIAL
620 printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
621 #endif
622 return ret;
623 }
625 static int serial_can_receive(SerialState *s)
626 {
627 if(s->fcr & UART_FCR_FE) {
628 if(s->recv_fifo.count < UART_FIFO_LENGTH)
629 /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
630 advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
631 effectively overriding the ITL that the guest has set. */
632 return ( s->recv_fifo.count <= s->recv_fifo.itl ) ? s->recv_fifo.itl - s->recv_fifo.count : 1;
633 else
634 return 0;
635 } else {
636 return !(s->lsr & UART_LSR_DR);
637 }
638 }
640 static void serial_receive_break(SerialState *s)
641 {
642 s->rbr = 0;
643 s->lsr |= UART_LSR_BI | UART_LSR_DR;
644 serial_update_irq(s);
645 }
647 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
648 static void fifo_timeout_int (void *opaque) {
649 SerialState *s = opaque;
650 if ( s->recv_fifo.count ) {
651 s->timeout_ipending = 1;
652 serial_update_irq(s);
653 }
654 }
656 static int serial_can_receive1(void *opaque)
657 {
658 SerialState *s = opaque;
659 return serial_can_receive(s);
660 }
662 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
663 {
664 SerialState *s = opaque;
665 tokens_avail = TOKENS_MAX;
666 if(s->fcr & UART_FCR_FE) {
667 int i;
668 for (i = 0; i < size; i++) {
669 fifo_put(s, RECV_FIFO, buf[i]);
670 }
671 s->lsr |= UART_LSR_DR;
672 /* call the timeout receive callback in 4 char transmit time */
673 qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
674 } else {
675 s->rbr = buf[0];
676 s->lsr |= UART_LSR_DR;
677 }
678 serial_update_irq(s);
679 }
681 static void serial_event(void *opaque, int event)
682 {
683 SerialState *s = opaque;
684 tokens_avail = TOKENS_MAX;
685 if (event == CHR_EVENT_BREAK)
686 serial_receive_break(s);
687 }
689 static void serial_save(QEMUFile *f, void *opaque)
690 {
691 SerialState *s = opaque;
693 qemu_put_be16s(f,&s->divider);
694 qemu_put_8s(f,&s->rbr);
695 qemu_put_8s(f,&s->ier);
696 qemu_put_8s(f,&s->iir);
697 qemu_put_8s(f,&s->lcr);
698 qemu_put_8s(f,&s->mcr);
699 qemu_put_8s(f,&s->lsr);
700 qemu_put_8s(f,&s->msr);
701 qemu_put_8s(f,&s->scr);
702 qemu_get_8s(f,&s->fcr);
703 }
705 static int serial_load(QEMUFile *f, void *opaque, int version_id)
706 {
707 SerialState *s = opaque;
709 if(version_id > 2)
710 return -EINVAL;
712 if (version_id >= 2)
713 qemu_get_be16s(f, &s->divider);
714 else
715 s->divider = qemu_get_byte(f);
716 qemu_get_8s(f,&s->rbr);
717 qemu_get_8s(f,&s->ier);
718 qemu_get_8s(f,&s->iir);
719 qemu_get_8s(f,&s->lcr);
720 qemu_get_8s(f,&s->mcr);
721 qemu_get_8s(f,&s->lsr);
722 qemu_get_8s(f,&s->msr);
723 qemu_get_8s(f,&s->scr);
724 qemu_get_8s(f,&s->fcr);
726 return 0;
727 }
729 /* If fd is zero, it means that the serial device uses the console */
730 SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
731 int base, int irq, CharDriverState *chr)
732 {
733 SerialState *s;
735 s = qemu_mallocz(sizeof(SerialState));
736 if (!s)
737 return NULL;
738 s->set_irq = set_irq;
739 s->irq_opaque = opaque;
740 s->irq = irq;
741 s->ier = 0;
742 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
743 s->iir = UART_IIR_NO_INT;
744 s->mcr = UART_MCR_OUT2;
745 s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
746 /* Default to 9600 baud, no parity, one stop bit */
747 s->divider = 0x0C;
748 s->tsr_retry = 0;
749 s->char_transmit_time = ( ticks_per_sec / 9600 ) * 9;
751 s->modem_status_poll = qemu_new_timer(vm_clock, ( QEMUTimerCB *) serial_update_msl, s);
753 s->poll_msl = 0;
755 fifo_clear(s,RECV_FIFO);
756 fifo_clear(s,XMIT_FIFO);
757 s->last_xmit_ts = qemu_get_clock(vm_clock);
758 s->fifo_timeout_timer = qemu_new_timer(vm_clock, ( QEMUTimerCB *) fifo_timeout_int, s);
759 s->transmit_timer = qemu_new_timer(vm_clock, ( QEMUTimerCB *) serial_xmit, s);
761 register_savevm("serial", base, 2, serial_save, serial_load, s);
763 register_ioport_write(base, 8, 1, serial_ioport_write, s);
764 register_ioport_read(base, 8, 1, serial_ioport_read, s);
765 s->chr = chr;
766 qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
767 serial_event, s);
768 serial_update_msl(s);
769 return s;
770 }