debuggers.hg

view xen/arch/x86/mtrr/main.c @ 3241:c23dd7ec1f54

bitkeeper revision 1.1159.1.472 (41ab49ab0UJYMrnMqSqKOFhhX2ypGw)

Merge arcadians.cl.cam.ac.uk:/auto/groups/xeno-xenod/BK/xen-unstable.bk
into arcadians.cl.cam.ac.uk:/auto/groups/xeno/users/cl349/BK/xen.bk-smp
author cl349@arcadians.cl.cam.ac.uk
date Mon Nov 29 16:09:15 2004 +0000 (2004-11-29)
parents a31bdfb8d4ea
children beb0887c54bc 0ef6e8e6e85d bbe8541361dd
line source
1 /* Generic MTRR (Memory Type Range Register) driver.
3 Copyright (C) 1997-2000 Richard Gooch
4 Copyright (c) 2002 Patrick Mochel
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Library General Public
8 License as published by the Free Software Foundation; either
9 version 2 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Library General Public License for more details.
16 You should have received a copy of the GNU Library General Public
17 License along with this library; if not, write to the Free
18 Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 Richard Gooch may be reached by email at rgooch@atnf.csiro.au
21 The postal address is:
22 Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
24 Source: "Pentium Pro Family Developer's Manual, Volume 3:
25 Operating System Writer's Guide" (Intel document number 242692),
26 section 11.11.7
28 This was cleaned and made readable by Patrick Mochel <mochel@osdl.org>
29 on 6-7 March 2002.
30 Source: Intel Architecture Software Developers Manual, Volume 3:
31 System Programming Guide; Section 9.11. (1997 edition - PPro).
32 */
34 #include <xen/config.h>
35 #include <xen/init.h>
36 #include <xen/pci.h>
37 #include <xen/smp.h>
38 #include <asm/mtrr.h>
39 #include <asm/uaccess.h>
40 #include <asm/processor.h>
41 #include <asm/msr.h>
42 #include "mtrr.h"
44 #define MTRR_VERSION "2.0 (20020519)"
46 /* No blocking mutexes in Xen. Spin instead. */
47 #define DECLARE_MUTEX(_m) spinlock_t _m = SPIN_LOCK_UNLOCKED
48 #define down(_m) spin_lock(_m)
49 #define up(_m) spin_unlock(_m)
51 #define num_booting_cpus() smp_num_cpus
53 u32 num_var_ranges = 0;
55 unsigned int *usage_table;
56 static DECLARE_MUTEX(main_lock);
58 u32 size_or_mask, size_and_mask;
60 static struct mtrr_ops * mtrr_ops[X86_VENDOR_NUM] = {};
62 struct mtrr_ops * mtrr_if = NULL;
64 __initdata char *mtrr_if_name[] = {
65 "none", "Intel", "AMD K6", "Cyrix ARR", "Centaur MCR"
66 };
68 static void set_mtrr(unsigned int reg, unsigned long base,
69 unsigned long size, mtrr_type type);
71 extern int arr3_protected;
73 static char *mtrr_strings[MTRR_NUM_TYPES] =
74 {
75 "uncachable", /* 0 */
76 "write-combining", /* 1 */
77 "?", /* 2 */
78 "?", /* 3 */
79 "write-through", /* 4 */
80 "write-protect", /* 5 */
81 "write-back", /* 6 */
82 };
84 char *mtrr_attrib_to_str(int x)
85 {
86 return (x <= 6) ? mtrr_strings[x] : "?";
87 }
89 void set_mtrr_ops(struct mtrr_ops * ops)
90 {
91 if (ops->vendor && ops->vendor < X86_VENDOR_NUM)
92 mtrr_ops[ops->vendor] = ops;
93 }
95 /* Returns non-zero if we have the write-combining memory type */
96 static int have_wrcomb(void)
97 {
98 struct pci_dev *dev;
100 if ((dev = pci_find_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) {
101 /* ServerWorks LE chipsets have problems with write-combining
102 Don't allow it and leave room for other chipsets to be tagged */
103 if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
104 dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) {
105 printk(KERN_INFO "mtrr: Serverworks LE detected. Write-combining disabled.\n");
106 return 0;
107 }
108 /* Intel 450NX errata # 23. Non ascending cachline evictions to
109 write combining memory may resulting in data corruption */
110 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
111 dev->device == PCI_DEVICE_ID_INTEL_82451NX)
112 {
113 printk(KERN_INFO "mtrr: Intel 450NX MMC detected. Write-combining disabled.\n");
114 return 0;
115 }
116 }
117 return (mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0);
118 }
120 /* This function returns the number of variable MTRRs */
121 void __init set_num_var_ranges(void)
122 {
123 unsigned long config = 0, dummy;
125 if (use_intel()) {
126 rdmsr(MTRRcap_MSR, config, dummy);
127 } else if (is_cpu(AMD))
128 config = 2;
129 else if (is_cpu(CYRIX) || is_cpu(CENTAUR))
130 config = 8;
131 num_var_ranges = config & 0xff;
132 }
134 static void __init init_table(void)
135 {
136 int i, max;
138 max = num_var_ranges;
139 if ((usage_table = xmalloc(max * sizeof *usage_table))
140 == NULL) {
141 printk(KERN_ERR "mtrr: could not allocate\n");
142 return;
143 }
144 for (i = 0; i < max; i++)
145 usage_table[i] = 1;
146 }
148 struct set_mtrr_data {
149 atomic_t count;
150 atomic_t gate;
151 unsigned long smp_base;
152 unsigned long smp_size;
153 unsigned int smp_reg;
154 mtrr_type smp_type;
155 };
157 #ifdef CONFIG_SMP
159 static void ipi_handler(void *info)
160 /* [SUMMARY] Synchronisation handler. Executed by "other" CPUs.
161 [RETURNS] Nothing.
162 */
163 {
164 struct set_mtrr_data *data = info;
165 unsigned long flags;
167 local_irq_save(flags);
169 atomic_dec(&data->count);
170 while(!atomic_read(&data->gate)) {
171 cpu_relax();
172 barrier();
173 }
175 /* The master has cleared me to execute */
176 if (data->smp_reg != ~0U)
177 mtrr_if->set(data->smp_reg, data->smp_base,
178 data->smp_size, data->smp_type);
179 else
180 mtrr_if->set_all();
182 atomic_dec(&data->count);
183 while(atomic_read(&data->gate)) {
184 cpu_relax();
185 barrier();
186 }
187 atomic_dec(&data->count);
188 local_irq_restore(flags);
189 }
191 #endif
193 /**
194 * set_mtrr - update mtrrs on all processors
195 * @reg: mtrr in question
196 * @base: mtrr base
197 * @size: mtrr size
198 * @type: mtrr type
199 *
200 * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly:
201 *
202 * 1. Send IPI to do the following:
203 * 2. Disable Interrupts
204 * 3. Wait for all procs to do so
205 * 4. Enter no-fill cache mode
206 * 5. Flush caches
207 * 6. Clear PGE bit
208 * 7. Flush all TLBs
209 * 8. Disable all range registers
210 * 9. Update the MTRRs
211 * 10. Enable all range registers
212 * 11. Flush all TLBs and caches again
213 * 12. Enter normal cache mode and reenable caching
214 * 13. Set PGE
215 * 14. Wait for buddies to catch up
216 * 15. Enable interrupts.
217 *
218 * What does that mean for us? Well, first we set data.count to the number
219 * of CPUs. As each CPU disables interrupts, it'll decrement it once. We wait
220 * until it hits 0 and proceed. We set the data.gate flag and reset data.count.
221 * Meanwhile, they are waiting for that flag to be set. Once it's set, each
222 * CPU goes through the transition of updating MTRRs. The CPU vendors may each do it
223 * differently, so we call mtrr_if->set() callback and let them take care of it.
224 * When they're done, they again decrement data->count and wait for data.gate to
225 * be reset.
226 * When we finish, we wait for data.count to hit 0 and toggle the data.gate flag.
227 * Everyone then enables interrupts and we all continue on.
228 *
229 * Note that the mechanism is the same for UP systems, too; all the SMP stuff
230 * becomes nops.
231 */
232 static void set_mtrr(unsigned int reg, unsigned long base,
233 unsigned long size, mtrr_type type)
234 {
235 struct set_mtrr_data data;
236 unsigned long flags;
238 data.smp_reg = reg;
239 data.smp_base = base;
240 data.smp_size = size;
241 data.smp_type = type;
242 atomic_set(&data.count, num_booting_cpus() - 1);
243 atomic_set(&data.gate,0);
245 /* Start the ball rolling on other CPUs */
246 if (smp_call_function(ipi_handler, &data, 1, 0) != 0)
247 panic("mtrr: timed out waiting for other CPUs\n");
249 local_irq_save(flags);
251 while(atomic_read(&data.count)) {
252 cpu_relax();
253 barrier();
254 }
255 /* ok, reset count and toggle gate */
256 atomic_set(&data.count, num_booting_cpus() - 1);
257 atomic_set(&data.gate,1);
259 /* do our MTRR business */
261 /* HACK!
262 * We use this same function to initialize the mtrrs on boot.
263 * The state of the boot cpu's mtrrs has been saved, and we want
264 * to replicate across all the APs.
265 * If we're doing that @reg is set to something special...
266 */
267 if (reg != ~0U)
268 mtrr_if->set(reg,base,size,type);
270 /* wait for the others */
271 while(atomic_read(&data.count)) {
272 cpu_relax();
273 barrier();
274 }
275 atomic_set(&data.count, num_booting_cpus() - 1);
276 atomic_set(&data.gate,0);
278 /*
279 * Wait here for everyone to have seen the gate change
280 * So we're the last ones to touch 'data'
281 */
282 while(atomic_read(&data.count)) {
283 cpu_relax();
284 barrier();
285 }
286 local_irq_restore(flags);
287 }
289 /**
290 * mtrr_add_page - Add a memory type region
291 * @base: Physical base address of region in pages (4 KB)
292 * @size: Physical size of region in pages (4 KB)
293 * @type: Type of MTRR desired
294 * @increment: If this is true do usage counting on the region
295 *
296 * Memory type region registers control the caching on newer Intel and
297 * non Intel processors. This function allows drivers to request an
298 * MTRR is added. The details and hardware specifics of each processor's
299 * implementation are hidden from the caller, but nevertheless the
300 * caller should expect to need to provide a power of two size on an
301 * equivalent power of two boundary.
302 *
303 * If the region cannot be added either because all regions are in use
304 * or the CPU cannot support it a negative value is returned. On success
305 * the register number for this entry is returned, but should be treated
306 * as a cookie only.
307 *
308 * On a multiprocessor machine the changes are made to all processors.
309 * This is required on x86 by the Intel processors.
310 *
311 * The available types are
312 *
313 * %MTRR_TYPE_UNCACHABLE - No caching
314 *
315 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
316 *
317 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
318 *
319 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
320 *
321 * BUGS: Needs a quiet flag for the cases where drivers do not mind
322 * failures and do not wish system log messages to be sent.
323 */
325 int mtrr_add_page(unsigned long base, unsigned long size,
326 unsigned int type, char increment)
327 {
328 int i;
329 mtrr_type ltype;
330 unsigned long lbase;
331 unsigned int lsize;
332 int error;
334 if (!mtrr_if)
335 return -ENXIO;
337 if ((error = mtrr_if->validate_add_page(base,size,type)))
338 return error;
340 if (type >= MTRR_NUM_TYPES) {
341 printk(KERN_WARNING "mtrr: type: %u invalid\n", type);
342 return -EINVAL;
343 }
345 /* If the type is WC, check that this processor supports it */
346 if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) {
347 printk(KERN_WARNING
348 "mtrr: your processor doesn't support write-combining\n");
349 return -ENOSYS;
350 }
352 if (base & size_or_mask || size & size_or_mask) {
353 printk(KERN_WARNING "mtrr: base or size exceeds the MTRR width\n");
354 return -EINVAL;
355 }
357 error = -EINVAL;
359 /* Search for existing MTRR */
360 down(&main_lock);
361 for (i = 0; i < num_var_ranges; ++i) {
362 mtrr_if->get(i, &lbase, &lsize, &ltype);
363 if (base >= lbase + lsize)
364 continue;
365 if ((base < lbase) && (base + size <= lbase))
366 continue;
367 /* At this point we know there is some kind of overlap/enclosure */
368 if ((base < lbase) || (base + size > lbase + lsize)) {
369 printk(KERN_WARNING
370 "mtrr: 0x%lx000,0x%lx000 overlaps existing"
371 " 0x%lx000,0x%x000\n", base, size, lbase,
372 lsize);
373 goto out;
374 }
375 /* New region is enclosed by an existing region */
376 if (ltype != type) {
377 if (type == MTRR_TYPE_UNCACHABLE)
378 continue;
379 printk (KERN_WARNING "mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n",
380 base, size, mtrr_attrib_to_str(ltype),
381 mtrr_attrib_to_str(type));
382 goto out;
383 }
384 if (increment)
385 ++usage_table[i];
386 error = i;
387 goto out;
388 }
389 /* Search for an empty MTRR */
390 i = mtrr_if->get_free_region(base, size);
391 if (i >= 0) {
392 set_mtrr(i, base, size, type);
393 usage_table[i] = 1;
394 } else
395 printk(KERN_INFO "mtrr: no more MTRRs available\n");
396 error = i;
397 out:
398 up(&main_lock);
399 return error;
400 }
402 /**
403 * mtrr_add - Add a memory type region
404 * @base: Physical base address of region
405 * @size: Physical size of region
406 * @type: Type of MTRR desired
407 * @increment: If this is true do usage counting on the region
408 *
409 * Memory type region registers control the caching on newer Intel and
410 * non Intel processors. This function allows drivers to request an
411 * MTRR is added. The details and hardware specifics of each processor's
412 * implementation are hidden from the caller, but nevertheless the
413 * caller should expect to need to provide a power of two size on an
414 * equivalent power of two boundary.
415 *
416 * If the region cannot be added either because all regions are in use
417 * or the CPU cannot support it a negative value is returned. On success
418 * the register number for this entry is returned, but should be treated
419 * as a cookie only.
420 *
421 * On a multiprocessor machine the changes are made to all processors.
422 * This is required on x86 by the Intel processors.
423 *
424 * The available types are
425 *
426 * %MTRR_TYPE_UNCACHABLE - No caching
427 *
428 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
429 *
430 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
431 *
432 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
433 *
434 * BUGS: Needs a quiet flag for the cases where drivers do not mind
435 * failures and do not wish system log messages to be sent.
436 */
438 int
439 mtrr_add(unsigned long base, unsigned long size, unsigned int type,
440 char increment)
441 {
442 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
443 printk(KERN_WARNING "mtrr: size and base must be multiples of 4 kiB\n");
444 printk(KERN_DEBUG "mtrr: size: 0x%lx base: 0x%lx\n", size, base);
445 return -EINVAL;
446 }
447 return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type,
448 increment);
449 }
451 /**
452 * mtrr_del_page - delete a memory type region
453 * @reg: Register returned by mtrr_add
454 * @base: Physical base address
455 * @size: Size of region
456 *
457 * If register is supplied then base and size are ignored. This is
458 * how drivers should call it.
459 *
460 * Releases an MTRR region. If the usage count drops to zero the
461 * register is freed and the region returns to default state.
462 * On success the register is returned, on failure a negative error
463 * code.
464 */
466 int mtrr_del_page(int reg, unsigned long base, unsigned long size)
467 {
468 int i, max;
469 mtrr_type ltype;
470 unsigned long lbase;
471 unsigned int lsize;
472 int error = -EINVAL;
474 if (!mtrr_if)
475 return -ENXIO;
477 max = num_var_ranges;
478 down(&main_lock);
479 if (reg < 0) {
480 /* Search for existing MTRR */
481 for (i = 0; i < max; ++i) {
482 mtrr_if->get(i, &lbase, &lsize, &ltype);
483 if (lbase == base && lsize == size) {
484 reg = i;
485 break;
486 }
487 }
488 if (reg < 0) {
489 printk(KERN_DEBUG "mtrr: no MTRR for %lx000,%lx000 found\n", base,
490 size);
491 goto out;
492 }
493 }
494 if (reg >= max) {
495 printk(KERN_WARNING "mtrr: register: %d too big\n", reg);
496 goto out;
497 }
498 if (is_cpu(CYRIX) && !use_intel()) {
499 if ((reg == 3) && arr3_protected) {
500 printk(KERN_WARNING "mtrr: ARR3 cannot be changed\n");
501 goto out;
502 }
503 }
504 mtrr_if->get(reg, &lbase, &lsize, &ltype);
505 if (lsize < 1) {
506 printk(KERN_WARNING "mtrr: MTRR %d not used\n", reg);
507 goto out;
508 }
509 if (usage_table[reg] < 1) {
510 printk(KERN_WARNING "mtrr: reg: %d has count=0\n", reg);
511 goto out;
512 }
513 if (--usage_table[reg] < 1)
514 set_mtrr(reg, 0, 0, 0);
515 error = reg;
516 out:
517 up(&main_lock);
518 return error;
519 }
520 /**
521 * mtrr_del - delete a memory type region
522 * @reg: Register returned by mtrr_add
523 * @base: Physical base address
524 * @size: Size of region
525 *
526 * If register is supplied then base and size are ignored. This is
527 * how drivers should call it.
528 *
529 * Releases an MTRR region. If the usage count drops to zero the
530 * register is freed and the region returns to default state.
531 * On success the register is returned, on failure a negative error
532 * code.
533 */
535 int
536 mtrr_del(int reg, unsigned long base, unsigned long size)
537 {
538 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
539 printk(KERN_INFO "mtrr: size and base must be multiples of 4 kiB\n");
540 printk(KERN_DEBUG "mtrr: size: 0x%lx base: 0x%lx\n", size, base);
541 return -EINVAL;
542 }
543 return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT);
544 }
546 EXPORT_SYMBOL(mtrr_add);
547 EXPORT_SYMBOL(mtrr_del);
549 /* HACK ALERT!
550 * These should be called implicitly, but we can't yet until all the initcall
551 * stuff is done...
552 */
553 extern void amd_init_mtrr(void);
554 extern void cyrix_init_mtrr(void);
555 extern void centaur_init_mtrr(void);
557 static void __init init_ifs(void)
558 {
559 amd_init_mtrr();
560 cyrix_init_mtrr();
561 centaur_init_mtrr();
562 }
564 static void __init init_other_cpus(void)
565 {
566 if (use_intel())
567 get_mtrr_state();
569 /* bring up the other processors */
570 set_mtrr(~0U,0,0,0);
572 if (use_intel()) {
573 finalize_mtrr_state();
574 mtrr_state_warn();
575 }
576 }
579 struct mtrr_value {
580 mtrr_type ltype;
581 unsigned long lbase;
582 unsigned int lsize;
583 };
585 /**
586 * mtrr_init - initialize mtrrs on the boot CPU
587 *
588 * This needs to be called early; before any of the other CPUs are
589 * initialized (i.e. before smp_init()).
590 *
591 */
592 static int __init mtrr_init(void)
593 {
594 init_ifs();
596 if (cpu_has_mtrr) {
597 mtrr_if = &generic_mtrr_ops;
598 size_or_mask = 0xff000000; /* 36 bits */
599 size_and_mask = 0x00f00000;
601 switch (boot_cpu_data.x86_vendor) {
602 case X86_VENDOR_AMD:
603 /* The original Athlon docs said that
604 total addressable memory is 44 bits wide.
605 It was not really clear whether its MTRRs
606 follow this or not. (Read: 44 or 36 bits).
607 However, "x86-64_overview.pdf" explicitly
608 states that "previous implementations support
609 36 bit MTRRs" and also provides a way to
610 query the width (in bits) of the physical
611 addressable memory on the Hammer family.
612 */
613 if (boot_cpu_data.x86 == 15
614 && (cpuid_eax(0x80000000) >= 0x80000008)) {
615 u32 phys_addr;
616 phys_addr = cpuid_eax(0x80000008) & 0xff;
617 size_or_mask =
618 ~((1 << (phys_addr - PAGE_SHIFT)) - 1);
619 size_and_mask = ~size_or_mask & 0xfff00000;
620 }
621 /* Athlon MTRRs use an Intel-compatible interface for
622 * getting and setting */
623 break;
624 case X86_VENDOR_CENTAUR:
625 if (boot_cpu_data.x86 == 6) {
626 /* VIA Cyrix family have Intel style MTRRs, but don't support PAE */
627 size_or_mask = 0xfff00000; /* 32 bits */
628 size_and_mask = 0;
629 }
630 break;
632 default:
633 break;
634 }
635 } else {
636 switch (boot_cpu_data.x86_vendor) {
637 case X86_VENDOR_AMD:
638 if (cpu_has_k6_mtrr) {
639 /* Pre-Athlon (K6) AMD CPU MTRRs */
640 mtrr_if = mtrr_ops[X86_VENDOR_AMD];
641 size_or_mask = 0xfff00000; /* 32 bits */
642 size_and_mask = 0;
643 }
644 break;
645 case X86_VENDOR_CENTAUR:
646 if (cpu_has_centaur_mcr) {
647 mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR];
648 size_or_mask = 0xfff00000; /* 32 bits */
649 size_and_mask = 0;
650 }
651 break;
652 case X86_VENDOR_CYRIX:
653 if (cpu_has_cyrix_arr) {
654 mtrr_if = mtrr_ops[X86_VENDOR_CYRIX];
655 size_or_mask = 0xfff00000; /* 32 bits */
656 size_and_mask = 0;
657 }
658 break;
659 default:
660 break;
661 }
662 }
663 printk(KERN_INFO "mtrr: v%s\n",MTRR_VERSION);
665 if (mtrr_if) {
666 set_num_var_ranges();
667 init_table();
668 init_other_cpus();
669 return 0;
670 }
671 return -ENXIO;
672 }
674 __initcall(mtrr_init);