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view xen/arch/i386/apic.c @ 656:c7557b3832b9

bitkeeper revision 1.339.1.6 (3f12cffdzSdqoflJR3gfS-S45xcteA)

nmi.c:
new file
Many files:
NMI watchdog support in Xen.
author kaf24@scramble.cl.cam.ac.uk
date Mon Jul 14 15:45:01 2003 +0000 (2003-07-14)
parents 90eb994a96e2
children c085fac641e2
line source
1 /* -*- Mode:C; c-basic-offset:4; tab-width:4 -*-
2 ****************************************************************************
3 * (C) 2002 - Rolf Neugebauer - Intel Research Cambridge
4 ****************************************************************************
5 *
6 * File: apic.c
7 * Author:
8 * Changes:
9 *
10 * Date: Nov 2002
11 *
12 * Environment: Xen Hypervisor
13 * Description: programmable APIC timer interface for accurate timers
14 * modified version of Linux' apic.c
15 *
16 ****************************************************************************
17 * $Id: c-insert.c,v 1.7 2002/11/08 16:04:34 rn Exp $
18 ****************************************************************************
19 */
21 /*
22 * Local APIC handling, local APIC timers
23 *
24 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
25 *
26 * Fixes
27 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
28 * thanks to Eric Gilmore
29 * and Rolf G. Tews
30 * for testing these extensively.
31 */
34 #include <xeno/config.h>
35 #include <xeno/init.h>
36 #include <xeno/sched.h>
37 #include <xeno/irq.h>
38 #include <xeno/delay.h>
39 #include <asm/mc146818rtc.h>
40 #include <asm/msr.h>
41 #include <xeno/errno.h>
42 #include <asm/atomic.h>
43 #include <xeno/smp.h>
44 #include <xeno/interrupt.h>
45 #include <asm/mpspec.h>
46 #include <asm/pgalloc.h>
47 #include <asm/hardirq.h>
48 #include <asm/apic.h>
49 #include <xeno/mm.h>
51 #include <asm/timex.h>
52 #include <xeno/ac_timer.h>
53 #include <xeno/perfc.h>
55 #undef APIC_TIME_TRACE
56 #ifdef APIC_TIME_TRACE
57 #define TRC(_x) _x
58 #else
59 #define TRC(_x)
60 #endif
63 /* Using APIC to generate smp_local_timer_interrupt? */
64 int using_apic_timer = 0;
66 int get_maxlvt(void)
67 {
68 unsigned int v, ver, maxlvt;
70 v = apic_read(APIC_LVR);
71 ver = GET_APIC_VERSION(v);
72 /* 82489DXs do not report # of LVT entries. */
73 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
74 return maxlvt;
75 }
77 static void clear_local_APIC(void)
78 {
79 int maxlvt;
80 unsigned long v;
82 maxlvt = get_maxlvt();
84 /*
85 * Careful: we have to set masks only first to deassert
86 * any level-triggered sources.
87 */
88 v = apic_read(APIC_LVTT);
89 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
90 v = apic_read(APIC_LVT0);
91 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
92 v = apic_read(APIC_LVT1);
93 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
94 if (maxlvt >= 3) {
95 v = apic_read(APIC_LVTERR);
96 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
97 }
98 if (maxlvt >= 4) {
99 v = apic_read(APIC_LVTPC);
100 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
101 }
103 /*
104 * Clean APIC state for other OSs:
105 */
106 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
107 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
108 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
109 if (maxlvt >= 3)
110 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
111 if (maxlvt >= 4)
112 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
113 }
115 void __init connect_bsp_APIC(void)
116 {
117 if (pic_mode) {
118 /*
119 * Do not trust the local APIC being empty at bootup.
120 */
121 clear_local_APIC();
122 /*
123 * PIC mode, enable APIC mode in the IMCR, i.e.
124 * connect BSP's local APIC to INT and NMI lines.
125 */
126 printk("leaving PIC mode, enabling APIC mode.\n");
127 outb(0x70, 0x22);
128 outb(0x01, 0x23);
129 }
130 }
132 void disconnect_bsp_APIC(void)
133 {
134 if (pic_mode) {
135 /*
136 * Put the board back into PIC mode (has an effect
137 * only on certain older boards). Note that APIC
138 * interrupts, including IPIs, won't work beyond
139 * this point! The only exception are INIT IPIs.
140 */
141 printk("disabling APIC mode, entering PIC mode.\n");
142 outb(0x70, 0x22);
143 outb(0x00, 0x23);
144 }
145 }
147 void disable_local_APIC(void)
148 {
149 unsigned long value;
151 clear_local_APIC();
153 /*
154 * Disable APIC (implies clearing of registers
155 * for 82489DX!).
156 */
157 value = apic_read(APIC_SPIV);
158 value &= ~APIC_SPIV_APIC_ENABLED;
159 apic_write_around(APIC_SPIV, value);
160 }
162 /*
163 * This is to verify that we're looking at a real local APIC.
164 * Check these against your board if the CPUs aren't getting
165 * started for no apparent reason.
166 */
167 int __init verify_local_APIC(void)
168 {
169 unsigned int reg0, reg1;
171 /*
172 * The version register is read-only in a real APIC.
173 */
174 reg0 = apic_read(APIC_LVR);
175 Dprintk("Getting VERSION: %x\n", reg0);
176 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
177 reg1 = apic_read(APIC_LVR);
178 Dprintk("Getting VERSION: %x\n", reg1);
180 /*
181 * The two version reads above should print the same
182 * numbers. If the second one is different, then we
183 * poke at a non-APIC.
184 */
185 if (reg1 != reg0)
186 return 0;
188 /*
189 * Check if the version looks reasonably.
190 */
191 reg1 = GET_APIC_VERSION(reg0);
192 if (reg1 == 0x00 || reg1 == 0xff)
193 return 0;
194 reg1 = get_maxlvt();
195 if (reg1 < 0x02 || reg1 == 0xff)
196 return 0;
198 /*
199 * The ID register is read/write in a real APIC.
200 */
201 reg0 = apic_read(APIC_ID);
202 Dprintk("Getting ID: %x\n", reg0);
203 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
204 reg1 = apic_read(APIC_ID);
205 Dprintk("Getting ID: %x\n", reg1);
206 apic_write(APIC_ID, reg0);
207 if (reg1 != (reg0 ^ APIC_ID_MASK))
208 return 0;
210 /*
211 * The next two are just to see if we have sane values.
212 * They're only really relevant if we're in Virtual Wire
213 * compatibility mode, but most boxes are anymore.
214 */
215 reg0 = apic_read(APIC_LVT0);
216 Dprintk("Getting LVT0: %x\n", reg0);
217 reg1 = apic_read(APIC_LVT1);
218 Dprintk("Getting LVT1: %x\n", reg1);
220 return 1;
221 }
223 void __init sync_Arb_IDs(void)
224 {
225 /* Wait for idle. */
226 apic_wait_icr_idle();
228 Dprintk("Synchronizing Arb IDs.\n");
229 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
230 | APIC_DM_INIT);
231 }
233 extern void __error_in_apic_c (void);
235 /*
236 * WAS: An initial setup of the virtual wire mode.
237 * NOW: We don't bother doing anything. All we need at this point
238 * is to receive timer ticks, so that 'jiffies' is incremented.
239 * If we're SMP, then we can assume BIOS did setup for us.
240 * If we're UP, then the APIC should be disabled (it is at reset).
241 * If we're UP and APIC is enabled, then BIOS is clever and has
242 * probably done initial interrupt routing for us.
243 */
244 void __init init_bsp_APIC(void)
245 {
246 }
248 void __init setup_local_APIC (void)
249 {
250 unsigned long value, ver, maxlvt;
252 value = apic_read(APIC_LVR);
253 ver = GET_APIC_VERSION(value);
255 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
256 __error_in_apic_c();
258 /* Double-check wether this APIC is really registered. */
259 if (!test_bit(GET_APIC_ID(apic_read(APIC_ID)), &phys_cpu_present_map))
260 BUG();
262 /*
263 * Intel recommends to set DFR, LDR and TPR before enabling
264 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
265 * document number 292116). So here it goes...
266 */
268 /*
269 * In clustered apic mode, the firmware does this for us
270 * Put the APIC into flat delivery mode.
271 * Must be "all ones" explicitly for 82489DX.
272 */
273 apic_write_around(APIC_DFR, 0xffffffff);
275 /*
276 * Set up the logical destination ID.
277 */
278 value = apic_read(APIC_LDR);
279 value &= ~APIC_LDR_MASK;
280 value |= (1<<(smp_processor_id()+24));
281 apic_write_around(APIC_LDR, value);
283 /*
284 * Set Task Priority to 'accept all'. We never change this
285 * later on.
286 */
287 value = apic_read(APIC_TASKPRI);
288 value &= ~APIC_TPRI_MASK;
289 apic_write_around(APIC_TASKPRI, value);
291 /*
292 * Now that we are all set up, enable the APIC
293 */
294 value = apic_read(APIC_SPIV);
295 value &= ~APIC_VECTOR_MASK;
296 /*
297 * Enable APIC
298 */
299 value |= APIC_SPIV_APIC_ENABLED;
301 /* Enable focus processor (bit==0) */
302 value &= ~APIC_SPIV_FOCUS_DISABLED;
304 /* Set spurious IRQ vector */
305 value |= SPURIOUS_APIC_VECTOR;
306 apic_write_around(APIC_SPIV, value);
308 /*
309 * Set up LVT0, LVT1:
310 *
311 * set up through-local-APIC on the BP's LINT0. This is not
312 * strictly necessery in pure symmetric-IO mode, but sometimes
313 * we delegate interrupts to the 8259A.
314 */
315 /*
316 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
317 */
318 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
319 if (!smp_processor_id()) {
320 value = APIC_DM_EXTINT;
321 printk("enabled ExtINT on CPU#%d\n", smp_processor_id());
322 } else {
323 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
324 printk("masked ExtINT on CPU#%d\n", smp_processor_id());
325 }
326 apic_write_around(APIC_LVT0, value);
328 /*
329 * only the BP should see the LINT1 NMI signal, obviously.
330 */
331 if (!smp_processor_id())
332 value = APIC_DM_NMI;
333 else
334 value = APIC_DM_NMI | APIC_LVT_MASKED;
335 if (!APIC_INTEGRATED(ver)) /* 82489DX */
336 value |= APIC_LVT_LEVEL_TRIGGER;
337 apic_write_around(APIC_LVT1, value);
339 if (APIC_INTEGRATED(ver)) { /* !82489DX */
340 maxlvt = get_maxlvt();
341 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
342 apic_write(APIC_ESR, 0);
343 value = apic_read(APIC_ESR);
344 printk("ESR value before enabling vector: %08lx\n", value);
346 value = ERROR_APIC_VECTOR; /* enables sending errors */
347 apic_write_around(APIC_LVTERR, value);
348 /* spec says clear errors after enabling vector. */
349 if (maxlvt > 3)
350 apic_write(APIC_ESR, 0);
351 value = apic_read(APIC_ESR);
352 printk("ESR value after enabling vector: %08lx\n", value);
353 } else {
354 printk("No ESR for 82489DX.\n");
355 }
357 if (nmi_watchdog == NMI_LOCAL_APIC)
358 setup_apic_nmi_watchdog();
359 }
362 static inline void apic_pm_init1(void) { }
363 static inline void apic_pm_init2(void) { }
366 /*
367 * Detect and enable local APICs on non-SMP boards.
368 * Original code written by Keir Fraser.
369 */
371 static int __init detect_init_APIC (void)
372 {
373 u32 h, l, features;
374 extern void get_cpu_vendor(struct cpuinfo_x86*);
376 /* Workaround for us being called before identify_cpu(). */
377 get_cpu_vendor(&boot_cpu_data);
379 switch (boot_cpu_data.x86_vendor) {
380 case X86_VENDOR_AMD:
381 if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1)
382 break;
383 goto no_apic;
384 case X86_VENDOR_INTEL:
385 if (boot_cpu_data.x86 == 6 ||
386 (boot_cpu_data.x86 == 15 && cpu_has_apic) ||
387 (boot_cpu_data.x86 == 5 && cpu_has_apic))
388 break;
389 goto no_apic;
390 default:
391 goto no_apic;
392 }
394 if (!cpu_has_apic) {
395 /*
396 * Some BIOSes disable the local APIC in the
397 * APIC_BASE MSR. This can only be done in
398 * software for Intel P6 and AMD K7 (Model > 1).
399 */
400 rdmsr(MSR_IA32_APICBASE, l, h);
401 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
402 printk("Local APIC disabled by BIOS -- reenabling.\n");
403 l &= ~MSR_IA32_APICBASE_BASE;
404 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
405 wrmsr(MSR_IA32_APICBASE, l, h);
406 }
407 }
409 /* The APIC feature bit should now be enabled in `cpuid' */
410 features = cpuid_edx(1);
411 if (!(features & (1 << X86_FEATURE_APIC))) {
412 printk("Could not enable APIC!\n");
413 return -1;
414 }
416 set_bit(X86_FEATURE_APIC, &boot_cpu_data.x86_capability);
417 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
418 boot_cpu_physical_apicid = 0;
419 if (nmi_watchdog != NMI_NONE)
420 nmi_watchdog = NMI_LOCAL_APIC;
422 printk("Found and enabled local APIC!\n");
423 apic_pm_init1();
424 return 0;
426 no_apic:
427 printk("No local APIC present or hardware disabled\n");
428 return -1;
429 }
431 void __init init_apic_mappings(void)
432 {
433 unsigned long apic_phys = 0;
435 /*
436 * If no local APIC can be found then set up a fake all zeroes page to
437 * simulate the local APIC and another one for the IO-APIC.
438 */
439 if (!smp_found_config && detect_init_APIC()) {
440 apic_phys = get_free_page(GFP_KERNEL);
441 apic_phys = __pa(apic_phys);
442 } else
443 apic_phys = mp_lapic_addr;
445 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
446 Dprintk("mapped APIC to %08lx (%08lx)\n", APIC_BASE, apic_phys);
448 /*
449 * Fetch the APIC ID of the BSP in case we have a
450 * default configuration (or the MP table is broken).
451 */
452 if (boot_cpu_physical_apicid == -1U)
453 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
455 #ifdef CONFIG_X86_IO_APIC
456 {
457 unsigned long ioapic_phys = 0, idx = FIX_IO_APIC_BASE_0;
458 int i;
460 for (i = 0; i < nr_ioapics; i++) {
461 if (smp_found_config)
462 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
463 set_fixmap_nocache(idx, ioapic_phys);
464 Dprintk("mapped IOAPIC to %08lx (%08lx)\n",
465 __fix_to_virt(idx), ioapic_phys);
466 idx++;
467 }
468 }
469 #endif
470 }
472 /*****************************************************************************
473 * APIC calibration
474 *
475 * The APIC is programmed in bus cycles.
476 * Timeout values should specified in real time units.
477 * The "cheapest" time source is the cyclecounter.
478 *
479 * Thus, we need a mappings from: bus cycles <- cycle counter <- system time
480 *
481 * The calibration is currently a bit shoddy since it requires the external
482 * timer chip to generate periodic timer interupts.
483 *****************************************************************************/
485 /* used for system time scaling */
486 static unsigned int bus_freq;
487 static u32 bus_cycle; /* length of one bus cycle in pico-seconds */
488 static u32 bus_scale; /* scaling factor convert ns to bus cycles */
489 u64 cpu_freq;
491 /*
492 * The timer chip is already set up at HZ interrupts per second here,
493 * but we do not accept timer interrupts yet. We only allow the BP
494 * to calibrate.
495 */
496 static unsigned int __init get_8254_timer_count(void)
497 {
498 /*extern spinlock_t i8253_lock;*/
499 /*unsigned long flags;*/
500 unsigned int count;
501 /*spin_lock_irqsave(&i8253_lock, flags);*/
502 outb_p(0x00, 0x43);
503 count = inb_p(0x40);
504 count |= inb_p(0x40) << 8;
505 /*spin_unlock_irqrestore(&i8253_lock, flags);*/
506 return count;
507 }
509 void __init wait_8254_wraparound(void)
510 {
511 unsigned int curr_count, prev_count=~0;
512 int delta;
513 curr_count = get_8254_timer_count();
514 do {
515 prev_count = curr_count;
516 curr_count = get_8254_timer_count();
517 delta = curr_count-prev_count;
518 /*
519 * This limit for delta seems arbitrary, but it isn't, it's slightly
520 * above the level of error a buggy Mercury/Neptune chipset timer can
521 * cause.
522 */
523 } while (delta < 300);
524 }
526 /*
527 * This function sets up the local APIC timer, with a timeout of
528 * 'clocks' APIC bus clock. During calibration we actually call
529 * this function with a very large value and read the current time after
530 * a well defined period of time as expired.
531 *
532 * Calibration is only performed once, for CPU0!
533 *
534 * We do reads before writes even if unnecessary, to get around the
535 * P5 APIC double write bug.
536 */
537 #define APIC_DIVISOR 1
538 static void __setup_APIC_LVTT(unsigned int clocks)
539 {
540 unsigned int lvtt1_value, tmp_value;
541 lvtt1_value = SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV)|LOCAL_TIMER_VECTOR;
542 apic_write_around(APIC_LVTT, lvtt1_value);
543 tmp_value = apic_read(APIC_TDCR);
544 apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
545 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
546 }
548 /*
549 * this is done for every CPU from setup_APIC_clocks() below.
550 * We setup each local APIC with a zero timeout value for now.
551 * Unlike Linux, we don't have to wait for slices etc.
552 */
553 void setup_APIC_timer(void * data)
554 {
555 unsigned long flags;
556 __save_flags(flags);
557 __sti();
558 printk("cpu: %d: setup timer.", smp_processor_id());
559 __setup_APIC_LVTT(0);
560 printk("done\n");
561 __restore_flags(flags);
562 }
564 /*
565 * In this function we calibrate APIC bus clocks to the external timer.
566 *
567 * As a result we have the Bys Speed and CPU speed in Hz.
568 *
569 * We want to do the calibration only once (for CPU0). CPUs connected by the
570 * same APIC bus have the very same bus frequency.
571 *
572 * This bit is a bit shoddy since we use the very same periodic timer interrupt
573 * we try to eliminate to calibrate the APIC.
574 */
576 int __init calibrate_APIC_clock(void)
577 {
578 unsigned long long t1 = 0, t2 = 0;
579 long tt1, tt2;
580 long result;
581 int i;
582 const int LOOPS = HZ/10;
584 printk("calibrating APIC timer for CPU%d...\n", smp_processor_id());
586 /* Put whatever arbitrary (but long enough) timeout
587 * value into the APIC clock, we just want to get the
588 * counter running for calibration. */
589 __setup_APIC_LVTT(1000000000);
591 /* The timer chip counts down to zero. Let's wait
592 * for a wraparound to start exact measurement:
593 * (the current tick might have been already half done) */
594 wait_8254_wraparound();
596 /* We wrapped around just now. Let's start: */
597 rdtscll(t1);
598 tt1 = apic_read(APIC_TMCCT);
600 /* Let's wait LOOPS wraprounds: */
601 for (i = 0; i < LOOPS; i++)
602 wait_8254_wraparound();
604 tt2 = apic_read(APIC_TMCCT);
605 rdtscll(t2);
607 /* The APIC bus clock counter is 32 bits only, it
608 * might have overflown, but note that we use signed
609 * longs, thus no extra care needed.
610 * underflown to be exact, as the timer counts down ;) */
611 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
613 printk("..... CPU speed is %ld.%04ld MHz.\n",
614 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
615 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
617 printk("..... Bus speed is %ld.%04ld MHz.\n",
618 result/(1000000/HZ),
619 result%(1000000/HZ));
621 cpu_freq = (u64)(((t2-t1)/LOOPS)*HZ);
623 /* set up multipliers for accurate timer code */
624 bus_freq = result*HZ;
625 bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */
626 bus_scale = (1000*262144)/bus_cycle;
628 /* print results */
629 printk("..... bus_freq = %u Hz\n", bus_freq);
630 printk("..... bus_cycle = %u ps\n", bus_cycle);
631 printk("..... bus_scale = %u \n", bus_scale);
632 /* reset APIC to zero timeout value */
633 __setup_APIC_LVTT(0);
634 return result;
635 }
637 /*
638 * initialise the APIC timers for all CPUs
639 * we start with the first and find out processor frequency and bus speed
640 */
641 void __init setup_APIC_clocks (void)
642 {
643 printk("Using local APIC timer interrupts.\n");
644 using_apic_timer = 1;
645 __cli();
646 /* calibrate CPU0 for CPU speed and BUS speed */
647 bus_freq = calibrate_APIC_clock();
648 /* Now set up the timer for real. */
649 setup_APIC_timer((void *)bus_freq);
650 __sti();
651 /* and update all other cpus */
652 smp_call_function(setup_APIC_timer, (void *)bus_freq, 1, 1);
653 }
655 #undef APIC_DIVISOR
657 /*
658 * reprogram the APIC timer. Timeoutvalue is in ns from start of boot
659 * returns 1 on success
660 * returns 0 if the timeout value is too small or in the past.
661 */
662 int reprogram_ac_timer(s_time_t timeout)
663 {
664 int cpu = smp_processor_id();
665 s_time_t now;
666 s_time_t expire;
667 u64 apic_tmict;
669 /*
670 * We use this value because we don't trust zero (we think it may just
671 * cause an immediate interrupt). At least this is guaranteed to hold it
672 * off for ages (esp. since the clock ticks on bus clock, not cpu clock!).
673 */
674 if (timeout == 0) {
675 apic_tmict = 0xffffffff;
676 goto reprogram;
677 }
679 now = NOW();
680 expire = timeout - now; /* value from now */
682 if (expire <= 0) {
683 printk("APICT[%02d] Timeout in the past 0x%08X%08X > 0x%08X%08X\n",
684 cpu, (u32)(now>>32), (u32)now, (u32)(timeout>>32),(u32)timeout);
685 return 0; /* timeout value in the past */
686 }
688 /* conversion to bus units */
689 apic_tmict = (((u64)bus_scale) * expire)>>18;
691 if (apic_tmict >= 0xffffffff) {
692 printk("APICT[%02d] Timeout value too large\n", cpu);
693 apic_tmict = 0xffffffff;
694 }
695 if (apic_tmict == 0) {
696 printk("APICT[%02d] timeout value too small\n", cpu);
697 return 0;
698 }
700 reprogram:
701 /* Program the timer. */
702 apic_write(APIC_TMICT, (unsigned long)apic_tmict);
704 TRC(printk("APICT[%02d] reprog(): expire=%lld %u\n",
705 cpu, expire, apic_tmict));
706 return 1;
707 }
709 /*
710 * Local timer interrupt handler.
711 * here the programmable, accurate timers are executed.
712 * If we are on CPU0 and we should have updated jiffies, we do this
713 * as well and and deal with traditional linux timers. Note, that of
714 * the timer APIC on CPU does not go off every 10ms or so the linux
715 * timers loose accuracy, but that shouldn't be a problem.
716 */
717 static s_time_t last_cpu0_tirq = 0;
718 inline void smp_local_timer_interrupt(struct pt_regs * regs)
719 {
720 int cpu = smp_processor_id();
721 s_time_t diff, now;
723 /* if CPU 0 do old timer stuff */
724 if (cpu == 0)
725 {
726 now = NOW();
727 diff = now - last_cpu0_tirq;
729 if (diff <= 0) {
730 printk ("System Time went backwards: %lld\n", diff);
731 return;
732 }
734 while (diff >= MILLISECS(10)) {
735 do_timer(regs);
736 diff -= MILLISECS(10);
737 last_cpu0_tirq += MILLISECS(10);
738 }
739 }
740 /* call accurate timer function */
741 do_ac_timer();
742 }
744 /*
745 * Local APIC timer interrupt. This is the most natural way for doing
746 * local interrupts, but local timer interrupts can be emulated by
747 * broadcast interrupts too. [in case the hw doesnt support APIC timers]
748 *
749 * [ if a single-CPU system runs an SMP kernel then we call the local
750 * interrupt as well. Thus we cannot inline the local irq ... ]
751 */
752 unsigned int apic_timer_irqs [NR_CPUS];
754 void smp_apic_timer_interrupt(struct pt_regs * regs)
755 {
756 int cpu = smp_processor_id();
757 #ifndef NDEBUG
758 u32 cc_start, cc_end;
759 rdtscl(cc_start);
760 #endif
762 /*
763 * the NMI deadlock-detector uses this.
764 */
765 apic_timer_irqs[cpu]++;
767 /*
768 * NOTE! We'd better ACK the irq immediately, because timer handling can
769 * be slow. XXX is this save?
770 */
771 ack_APIC_irq();
773 /* call the local handler */
774 irq_enter(cpu, 0);
775 perfc_incrc(apic_timer);
776 smp_local_timer_interrupt(regs);
777 irq_exit(cpu, 0);
779 if (softirq_pending(cpu))
780 do_softirq();
782 #ifndef NDEBUG
783 rdtscl(cc_end);
784 if ( (cc_end - cc_start) > (cpu_khz * 100) )
785 printk("APIC Long ISR on CPU=%02d %08X -> %08X\n",cpu,cc_start,cc_end);
786 #endif
787 }
789 /*
790 * This interrupt should _never_ happen with our APIC/SMP architecture
791 */
792 asmlinkage void smp_spurious_interrupt(void)
793 {
794 unsigned long v;
796 /*
797 * Check if this really is a spurious interrupt and ACK it
798 * if it is a vectored one. Just in case...
799 * Spurious interrupts should not be ACKed.
800 */
801 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
802 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
803 ack_APIC_irq();
805 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
806 printk("spurious APIC interrupt on CPU#%d, should never happen.\n",
807 smp_processor_id());
808 }
810 /*
811 * This interrupt should never happen with our APIC/SMP architecture
812 */
814 asmlinkage void smp_error_interrupt(void)
815 {
816 unsigned long v, v1;
818 /* First tickle the hardware, only then report what went on. -- REW */
819 v = apic_read(APIC_ESR);
820 apic_write(APIC_ESR, 0);
821 v1 = apic_read(APIC_ESR);
822 ack_APIC_irq();
823 atomic_inc(&irq_err_count);
825 /* Here is what the APIC error bits mean:
826 0: Send CS error
827 1: Receive CS error
828 2: Send accept error
829 3: Receive accept error
830 4: Reserved
831 5: Send illegal vector
832 6: Received illegal vector
833 7: Illegal register address
834 */
835 printk ("APIC error on CPU%d: %02lx(%02lx)\n",
836 smp_processor_id(), v , v1);
837 }
839 /*
840 * This initializes the IO-APIC and APIC hardware if this is
841 * a UP kernel.
842 */
843 int __init APIC_init_uniprocessor (void)
844 {
845 if (!smp_found_config && !cpu_has_apic)
846 return -1;
848 /*
849 * Complain if the BIOS pretends there is one.
850 */
851 if (!cpu_has_apic&&APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]))
852 {
853 printk("BIOS bug, local APIC #%d not detected!...\n",
854 boot_cpu_physical_apicid);
855 return -1;
856 }
858 verify_local_APIC();
860 connect_bsp_APIC();
862 #ifdef CONFIG_SMP
863 cpu_online_map = 1;
864 #endif
865 phys_cpu_present_map = 1;
866 apic_write_around(APIC_ID, boot_cpu_physical_apicid);
868 apic_pm_init2();
870 setup_local_APIC();
872 #ifdef CONFIG_X86_IO_APIC
873 if (smp_found_config && nr_ioapics)
874 setup_IO_APIC();
875 #endif
876 setup_APIC_clocks();
878 return 0;
879 }