debuggers.hg

view xen/arch/i386/io_apic.c @ 656:c7557b3832b9

bitkeeper revision 1.339.1.6 (3f12cffdzSdqoflJR3gfS-S45xcteA)

nmi.c:
new file
Many files:
NMI watchdog support in Xen.
author kaf24@scramble.cl.cam.ac.uk
date Mon Jul 14 15:45:01 2003 +0000 (2003-07-14)
parents bb07751512ba
children c085fac641e2
line source
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 */
22 #include <xeno/config.h>
23 #include <xeno/init.h>
24 #include <xeno/interrupt.h>
25 #include <xeno/irq.h>
26 #include <xeno/delay.h>
27 #include <xeno/sched.h>
28 #include <xeno/config.h>
29 #include <asm/mc146818rtc.h>
30 #include <asm/io.h>
31 #include <asm/smp.h>
32 #include <asm/desc.h>
33 #include <asm/smpboot.h>
35 #ifdef CONFIG_X86_IO_APIC
37 #undef APIC_LOCKUP_DEBUG
39 #define APIC_LOCKUP_DEBUG
41 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
43 unsigned int int_dest_addr_mode = APIC_DEST_LOGICAL;
44 unsigned char int_delivery_mode = dest_LowestPrio;
47 /*
48 * # of IRQ routing registers
49 */
50 int nr_ioapic_registers[MAX_IO_APICS];
52 /*
53 * Rough estimation of how many shared IRQs there are, can
54 * be changed anytime.
55 */
56 #define MAX_PLUS_SHARED_IRQS NR_IRQS
57 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
59 /*
60 * This is performance-critical, we want to do it O(1)
61 *
62 * the indexing order of this array favors 1:1 mappings
63 * between pins and IRQs.
64 */
66 static struct irq_pin_list {
67 int apic, pin, next;
68 } irq_2_pin[PIN_MAP_SIZE];
70 /*
71 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
72 * shared ISA-space IRQs, so we have to support them. We are super
73 * fast in the common case, and fast for shared ISA-space IRQs.
74 */
75 static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
76 {
77 static int first_free_entry = NR_IRQS;
78 struct irq_pin_list *entry = irq_2_pin + irq;
80 while (entry->next)
81 entry = irq_2_pin + entry->next;
83 if (entry->pin != -1) {
84 entry->next = first_free_entry;
85 entry = irq_2_pin + entry->next;
86 if (++first_free_entry >= PIN_MAP_SIZE)
87 panic("io_apic.c: whoops");
88 }
89 entry->apic = apic;
90 entry->pin = pin;
91 }
93 /*
94 * Reroute an IRQ to a different pin.
95 */
96 static void __init replace_pin_at_irq(unsigned int irq,
97 int oldapic, int oldpin,
98 int newapic, int newpin)
99 {
100 struct irq_pin_list *entry = irq_2_pin + irq;
102 while (1) {
103 if (entry->apic == oldapic && entry->pin == oldpin) {
104 entry->apic = newapic;
105 entry->pin = newpin;
106 }
107 if (!entry->next)
108 break;
109 entry = irq_2_pin + entry->next;
110 }
111 }
113 #define __DO_ACTION(R, ACTION, FINAL) \
114 \
115 { \
116 int pin; \
117 struct irq_pin_list *entry = irq_2_pin + irq; \
118 \
119 for (;;) { \
120 unsigned int reg; \
121 pin = entry->pin; \
122 if (pin == -1) \
123 break; \
124 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
125 reg ACTION; \
126 io_apic_modify(entry->apic, reg); \
127 if (!entry->next) \
128 break; \
129 entry = irq_2_pin + entry->next; \
130 } \
131 FINAL; \
132 }
134 #define DO_ACTION(name,R,ACTION, FINAL) \
135 \
136 static void name##_IO_APIC_irq (unsigned int irq) \
137 __DO_ACTION(R, ACTION, FINAL)
139 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
140 /* mask = 1 */
141 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
142 /* mask = 0 */
143 DO_ACTION( __mask_and_edge, 0, = (reg & 0xffff7fff) | 0x00010000, )
144 /* mask = 1, trigger = 0 */
145 DO_ACTION( __unmask_and_level, 0, = (reg & 0xfffeffff) | 0x00008000, )
146 /* mask = 0, trigger = 1 */
148 static void mask_IO_APIC_irq (unsigned int irq)
149 {
150 unsigned long flags;
152 spin_lock_irqsave(&ioapic_lock, flags);
153 __mask_IO_APIC_irq(irq);
154 spin_unlock_irqrestore(&ioapic_lock, flags);
155 }
157 static void unmask_IO_APIC_irq (unsigned int irq)
158 {
159 unsigned long flags;
161 spin_lock_irqsave(&ioapic_lock, flags);
162 __unmask_IO_APIC_irq(irq);
163 spin_unlock_irqrestore(&ioapic_lock, flags);
164 }
166 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
167 {
168 struct IO_APIC_route_entry entry;
169 unsigned long flags;
171 /*
172 * Disable it in the IO-APIC irq-routing table:
173 */
174 memset(&entry, 0, sizeof(entry));
175 entry.mask = 1;
176 spin_lock_irqsave(&ioapic_lock, flags);
177 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
178 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
179 spin_unlock_irqrestore(&ioapic_lock, flags);
180 }
182 static void clear_IO_APIC (void)
183 {
184 int apic, pin;
186 for (apic = 0; apic < nr_ioapics; apic++)
187 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
188 clear_IO_APIC_pin(apic, pin);
189 }
191 static void set_ioapic_affinity (unsigned int irq, unsigned long mask)
192 {
193 unsigned long flags;
195 /*
196 * Only the first 8 bits are valid.
197 */
198 mask = mask << 24;
199 spin_lock_irqsave(&ioapic_lock, flags);
200 __DO_ACTION(1, = mask, )
201 spin_unlock_irqrestore(&ioapic_lock, flags);
202 }
204 #if CONFIG_SMP
206 typedef struct {
207 unsigned int cpu;
208 unsigned long timestamp;
209 } ____cacheline_aligned irq_balance_t;
211 static irq_balance_t irq_balance[NR_IRQS] __cacheline_aligned
212 = { [ 0 ... NR_IRQS-1 ] = { 0, 0 } };
214 extern unsigned long irq_affinity [NR_IRQS];
216 #endif
218 #define IDLE_ENOUGH(cpu,now) \
219 (idle_cpu(cpu) && ((now) - irq_stat[(cpu)].idle_timestamp > 1))
221 #define IRQ_ALLOWED(cpu,allowed_mask) \
222 ((1 << cpu) & (allowed_mask))
224 static unsigned long move(int curr_cpu, unsigned long allowed_mask, unsigned long now, int direction)
225 {
226 int search_idle = 1;
227 int cpu = curr_cpu;
229 goto inside;
231 do {
232 if (unlikely(cpu == curr_cpu))
233 search_idle = 0;
234 inside:
235 if (direction == 1) {
236 cpu++;
237 if (cpu >= smp_num_cpus)
238 cpu = 0;
239 } else {
240 cpu--;
241 if (cpu == -1)
242 cpu = smp_num_cpus-1;
243 }
244 } while (!IRQ_ALLOWED(cpu,allowed_mask) ||
245 (search_idle && !IDLE_ENOUGH(cpu,now)));
247 return cpu;
248 }
250 static inline void balance_irq(int irq)
251 {
252 #if CONFIG_SMP
253 irq_balance_t *entry = irq_balance + irq;
254 unsigned long now = jiffies;
256 if (unlikely(entry->timestamp != now)) {
257 unsigned long allowed_mask;
258 int random_number;
260 rdtscl(random_number);
261 random_number &= 1;
263 allowed_mask = cpu_online_map & irq_affinity[irq];
264 entry->timestamp = now;
265 entry->cpu = move(entry->cpu, allowed_mask, now, random_number);
266 set_ioapic_affinity(irq, apicid_to_phys_cpu_present(entry->cpu));
267 }
268 #endif
269 }
271 /*
272 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
273 * specific CPU-side IRQs.
274 */
276 #define MAX_PIRQS 8
277 int pirq_entries [MAX_PIRQS];
278 int pirqs_enabled;
280 int skip_ioapic_setup;
281 #if 0
283 static int __init noioapic_setup(char *str)
284 {
285 skip_ioapic_setup = 1;
286 return 1;
287 }
289 __setup("noapic", noioapic_setup);
291 static int __init ioapic_setup(char *str)
292 {
293 skip_ioapic_setup = 0;
294 return 1;
295 }
297 __setup("apic", ioapic_setup);
301 static int __init ioapic_pirq_setup(char *str)
302 {
303 int i, max;
304 int ints[MAX_PIRQS+1];
306 get_options(str, ARRAY_SIZE(ints), ints);
308 for (i = 0; i < MAX_PIRQS; i++)
309 pirq_entries[i] = -1;
311 pirqs_enabled = 1;
312 printk(KERN_INFO "PIRQ redirection, working around broken MP-BIOS.\n");
313 max = MAX_PIRQS;
314 if (ints[0] < MAX_PIRQS)
315 max = ints[0];
317 for (i = 0; i < max; i++) {
318 printk(KERN_DEBUG "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
319 /*
320 * PIRQs are mapped upside down, usually.
321 */
322 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
323 }
324 return 1;
325 }
327 __setup("pirq=", ioapic_pirq_setup);
329 #endif
331 /*
332 * Find the IRQ entry number of a certain pin.
333 */
334 static int __init find_irq_entry(int apic, int pin, int type)
335 {
336 int i;
338 for (i = 0; i < mp_irq_entries; i++)
339 if (mp_irqs[i].mpc_irqtype == type &&
340 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
341 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
342 mp_irqs[i].mpc_dstirq == pin)
343 return i;
345 return -1;
346 }
348 /*
349 * Find the pin to which IRQ[irq] (ISA) is connected
350 */
351 static int __init find_isa_irq_pin(int irq, int type)
352 {
353 int i;
355 for (i = 0; i < mp_irq_entries; i++) {
356 int lbus = mp_irqs[i].mpc_srcbus;
358 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
359 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
360 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
361 (mp_irqs[i].mpc_irqtype == type) &&
362 (mp_irqs[i].mpc_srcbusirq == irq))
364 return mp_irqs[i].mpc_dstirq;
365 }
366 return -1;
367 }
369 /*
370 * Find a specific PCI IRQ entry.
371 * Not an __init, possibly needed by modules
372 */
373 static int pin_2_irq(int idx, int apic, int pin);
375 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
376 {
377 int apic, i, best_guess = -1;
379 Dprintk("querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
380 bus, slot, pin);
381 if ((mp_bus_id_to_pci_bus==NULL) || (mp_bus_id_to_pci_bus[bus] == -1)) {
382 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
383 return -1;
384 }
385 for (i = 0; i < mp_irq_entries; i++) {
386 int lbus = mp_irqs[i].mpc_srcbus;
388 for (apic = 0; apic < nr_ioapics; apic++)
389 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
390 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
391 break;
393 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
394 !mp_irqs[i].mpc_irqtype &&
395 (bus == lbus) &&
396 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
397 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
399 if (!(apic || IO_APIC_IRQ(irq)))
400 continue;
402 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
403 return irq;
404 /*
405 * Use the first all-but-pin matching entry as a
406 * best-guess fuzzy result for broken mptables.
407 */
408 if (best_guess < 0)
409 best_guess = irq;
410 }
411 }
412 return best_guess;
413 }
415 /*
416 * EISA Edge/Level control register, ELCR
417 */
418 static int __init EISA_ELCR(unsigned int irq)
419 {
420 if (irq < 16) {
421 unsigned int port = 0x4d0 + (irq >> 3);
422 return (inb(port) >> (irq & 7)) & 1;
423 }
424 printk(KERN_INFO "Broken MPtable reports ISA irq %d\n", irq);
425 return 0;
426 }
428 /* EISA interrupts are always polarity zero and can be edge or level
429 * trigger depending on the ELCR value. If an interrupt is listed as
430 * EISA conforming in the MP table, that means its trigger type must
431 * be read in from the ELCR */
433 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
434 #define default_EISA_polarity(idx) (0)
436 /* ISA interrupts are always polarity zero edge triggered,
437 * when listed as conforming in the MP table. */
439 #define default_ISA_trigger(idx) (0)
440 #define default_ISA_polarity(idx) (0)
442 /* PCI interrupts are always polarity one level triggered,
443 * when listed as conforming in the MP table. */
445 #define default_PCI_trigger(idx) (1)
446 #define default_PCI_polarity(idx) (1)
448 /* MCA interrupts are always polarity zero level triggered,
449 * when listed as conforming in the MP table. */
451 #define default_MCA_trigger(idx) (1)
452 #define default_MCA_polarity(idx) (0)
454 static int __init MPBIOS_polarity(int idx)
455 {
456 int bus = mp_irqs[idx].mpc_srcbus;
457 int polarity;
459 /*
460 * Determine IRQ line polarity (high active or low active):
461 */
462 switch (mp_irqs[idx].mpc_irqflag & 3)
463 {
464 case 0: /* conforms, ie. bus-type dependent polarity */
465 {
466 switch (mp_bus_id_to_type[bus])
467 {
468 case MP_BUS_ISA: /* ISA pin */
469 {
470 polarity = default_ISA_polarity(idx);
471 break;
472 }
473 case MP_BUS_EISA: /* EISA pin */
474 {
475 polarity = default_EISA_polarity(idx);
476 break;
477 }
478 case MP_BUS_PCI: /* PCI pin */
479 {
480 polarity = default_PCI_polarity(idx);
481 break;
482 }
483 case MP_BUS_MCA: /* MCA pin */
484 {
485 polarity = default_MCA_polarity(idx);
486 break;
487 }
488 default:
489 {
490 printk(KERN_WARNING "broken BIOS!!\n");
491 polarity = 1;
492 break;
493 }
494 }
495 break;
496 }
497 case 1: /* high active */
498 {
499 polarity = 0;
500 break;
501 }
502 case 2: /* reserved */
503 {
504 printk(KERN_WARNING "broken BIOS!!\n");
505 polarity = 1;
506 break;
507 }
508 case 3: /* low active */
509 {
510 polarity = 1;
511 break;
512 }
513 default: /* invalid */
514 {
515 printk(KERN_WARNING "broken BIOS!!\n");
516 polarity = 1;
517 break;
518 }
519 }
520 return polarity;
521 }
523 static int __init MPBIOS_trigger(int idx)
524 {
525 int bus = mp_irqs[idx].mpc_srcbus;
526 int trigger;
528 /*
529 * Determine IRQ trigger mode (edge or level sensitive):
530 */
531 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
532 {
533 case 0: /* conforms, ie. bus-type dependent */
534 {
535 switch (mp_bus_id_to_type[bus])
536 {
537 case MP_BUS_ISA: /* ISA pin */
538 {
539 trigger = default_ISA_trigger(idx);
540 break;
541 }
542 case MP_BUS_EISA: /* EISA pin */
543 {
544 trigger = default_EISA_trigger(idx);
545 break;
546 }
547 case MP_BUS_PCI: /* PCI pin */
548 {
549 trigger = default_PCI_trigger(idx);
550 break;
551 }
552 case MP_BUS_MCA: /* MCA pin */
553 {
554 trigger = default_MCA_trigger(idx);
555 break;
556 }
557 default:
558 {
559 printk(KERN_WARNING "broken BIOS!!\n");
560 trigger = 1;
561 break;
562 }
563 }
564 break;
565 }
566 case 1: /* edge */
567 {
568 trigger = 0;
569 break;
570 }
571 case 2: /* reserved */
572 {
573 printk(KERN_WARNING "broken BIOS!!\n");
574 trigger = 1;
575 break;
576 }
577 case 3: /* level */
578 {
579 trigger = 1;
580 break;
581 }
582 default: /* invalid */
583 {
584 printk(KERN_WARNING "broken BIOS!!\n");
585 trigger = 0;
586 break;
587 }
588 }
589 return trigger;
590 }
592 static inline int irq_polarity(int idx)
593 {
594 return MPBIOS_polarity(idx);
595 }
597 static inline int irq_trigger(int idx)
598 {
599 return MPBIOS_trigger(idx);
600 }
602 static int pin_2_irq(int idx, int apic, int pin)
603 {
604 int irq, i;
605 int bus = mp_irqs[idx].mpc_srcbus;
607 /*
608 * Debugging check, we are in big trouble if this message pops up!
609 */
610 if (mp_irqs[idx].mpc_dstirq != pin)
611 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
613 switch (mp_bus_id_to_type[bus])
614 {
615 case MP_BUS_ISA: /* ISA pin */
616 case MP_BUS_EISA:
617 case MP_BUS_MCA:
618 {
619 irq = mp_irqs[idx].mpc_srcbusirq;
620 break;
621 }
622 case MP_BUS_PCI: /* PCI pin */
623 {
624 /*
625 * PCI IRQs are mapped in order
626 */
627 i = irq = 0;
628 while (i < apic)
629 irq += nr_ioapic_registers[i++];
630 irq += pin;
631 break;
632 }
633 default:
634 {
635 printk(KERN_ERR "unknown bus type %d.\n",bus);
636 irq = 0;
637 break;
638 }
639 }
641 /*
642 * PCI IRQ command line redirection. Yes, limits are hardcoded.
643 */
644 if ((pin >= 16) && (pin <= 23)) {
645 if (pirq_entries[pin-16] != -1) {
646 if (!pirq_entries[pin-16]) {
647 printk(KERN_DEBUG "disabling PIRQ%d\n", pin-16);
648 } else {
649 irq = pirq_entries[pin-16];
650 printk(KERN_DEBUG "using PIRQ%d -> IRQ %d\n",
651 pin-16, irq);
652 }
653 }
654 }
655 return irq;
656 }
658 static inline int IO_APIC_irq_trigger(int irq)
659 {
660 int apic, idx, pin;
662 for (apic = 0; apic < nr_ioapics; apic++) {
663 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
664 idx = find_irq_entry(apic,pin,mp_INT);
665 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
666 return irq_trigger(idx);
667 }
668 }
669 /*
670 * nonexistent IRQs are edge default
671 */
672 return 0;
673 }
675 int irq_vector[NR_IRQS] = { FIRST_DEVICE_VECTOR , 0 };
677 static int __init assign_irq_vector(int irq)
678 {
679 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
680 if (IO_APIC_VECTOR(irq) > 0)
681 return IO_APIC_VECTOR(irq);
682 next:
683 current_vector += 8;
685 /* XXX Skip the guestOS -> Xen syscall vector! XXX */
686 if (current_vector == HYPERVISOR_CALL_VECTOR) goto next;
687 /* XXX Skip the Linux/BSD fast-trap vector! XXX */
688 if (current_vector == 0x80) goto next;
690 #if 0
691 if (current_vector == SYSCALL_VECTOR)
692 goto next;
693 #endif
695 if (current_vector > FIRST_SYSTEM_VECTOR) {
696 offset++;
697 current_vector = FIRST_DEVICE_VECTOR + offset;
698 }
700 if (current_vector == FIRST_SYSTEM_VECTOR)
701 panic("ran out of interrupt sources!");
703 IO_APIC_VECTOR(irq) = current_vector;
704 return current_vector;
705 }
707 extern void (*interrupt[NR_IRQS])(void);
708 static struct hw_interrupt_type ioapic_level_irq_type;
709 static struct hw_interrupt_type ioapic_edge_irq_type;
711 void __init setup_IO_APIC_irqs(void)
712 {
713 struct IO_APIC_route_entry entry;
714 int apic, pin, idx, irq, first_notcon = 1, vector;
715 unsigned long flags;
717 printk(KERN_DEBUG "init IO_APIC IRQs\n");
719 for (apic = 0; apic < nr_ioapics; apic++) {
720 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
722 /*
723 * add it to the IO-APIC irq-routing table:
724 */
725 memset(&entry,0,sizeof(entry));
727 entry.delivery_mode = INT_DELIVERY_MODE;
728 entry.dest_mode = (INT_DEST_ADDR_MODE != 0);
729 entry.mask = 0; /* enable IRQ */
730 entry.dest.logical.logical_dest = target_cpus();
732 idx = find_irq_entry(apic,pin,mp_INT);
733 if (idx == -1) {
734 if (first_notcon) {
735 printk(KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
736 first_notcon = 0;
737 } else
738 printk(", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
739 continue;
740 }
742 entry.trigger = irq_trigger(idx);
743 entry.polarity = irq_polarity(idx);
745 if (irq_trigger(idx)) {
746 entry.trigger = 1;
747 entry.mask = 1;
748 }
750 irq = pin_2_irq(idx, apic, pin);
751 /*
752 * skip adding the timer int on secondary nodes, which causes
753 * a small but painful rift in the time-space continuum
754 */
755 if ((clustered_apic_mode == CLUSTERED_APIC_NUMAQ)
756 && (apic != 0) && (irq == 0))
757 continue;
758 else
759 add_pin_to_irq(irq, apic, pin);
761 if (!apic && !IO_APIC_IRQ(irq))
762 continue;
764 if (IO_APIC_IRQ(irq)) {
765 vector = assign_irq_vector(irq);
766 entry.vector = vector;
768 if (IO_APIC_irq_trigger(irq))
769 irq_desc[irq].handler = &ioapic_level_irq_type;
770 else
771 irq_desc[irq].handler = &ioapic_edge_irq_type;
773 set_intr_gate(vector, interrupt[irq]);
775 if (!apic && (irq < 16))
776 disable_8259A_irq(irq);
777 }
778 spin_lock_irqsave(&ioapic_lock, flags);
779 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
780 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
781 spin_unlock_irqrestore(&ioapic_lock, flags);
782 }
783 }
785 if (!first_notcon)
786 printk(" not connected.\n");
787 }
789 /*
790 * Set up the 8259A-master output pin as broadcast to all
791 * CPUs.
792 */
793 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
794 {
795 struct IO_APIC_route_entry entry;
796 unsigned long flags;
798 memset(&entry,0,sizeof(entry));
800 disable_8259A_irq(0);
802 /* mask LVT0 */
803 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
805 /*
806 * We use logical delivery to get the timer IRQ
807 * to the first CPU.
808 */
809 entry.dest_mode = (INT_DEST_ADDR_MODE != 0);
810 entry.mask = 0; /* unmask IRQ now */
811 entry.dest.logical.logical_dest = target_cpus();
812 entry.delivery_mode = INT_DELIVERY_MODE;
813 entry.polarity = 0;
814 entry.trigger = 0;
815 entry.vector = vector;
817 /*
818 * The timer IRQ doesn't have to know that behind the
819 * scene we have a 8259A-master in AEOI mode ...
820 */
821 irq_desc[0].handler = &ioapic_edge_irq_type;
823 /*
824 * Add it to the IO-APIC irq-routing table:
825 */
826 spin_lock_irqsave(&ioapic_lock, flags);
827 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
828 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
829 spin_unlock_irqrestore(&ioapic_lock, flags);
831 enable_8259A_irq(0);
832 }
834 void __init UNEXPECTED_IO_APIC(void)
835 {
836 printk(KERN_WARNING
837 "An unexpected IO-APIC was found. If this kernel release is less than\n"
838 "three months old please report this to linux-smp@vger.kernel.org\n");
839 }
841 void __init print_IO_APIC(void)
842 {
843 int apic, i;
844 struct IO_APIC_reg_00 reg_00;
845 struct IO_APIC_reg_01 reg_01;
846 struct IO_APIC_reg_02 reg_02;
847 unsigned long flags;
849 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
850 for (i = 0; i < nr_ioapics; i++)
851 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
852 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
854 /*
855 * We are a bit conservative about what we expect. We have to
856 * know about every hardware change ASAP.
857 */
858 printk(KERN_INFO "testing the IO APIC.......................\n");
860 for (apic = 0; apic < nr_ioapics; apic++) {
862 spin_lock_irqsave(&ioapic_lock, flags);
863 *(int *)&reg_00 = io_apic_read(apic, 0);
864 *(int *)&reg_01 = io_apic_read(apic, 1);
865 if (reg_01.version >= 0x10)
866 *(int *)&reg_02 = io_apic_read(apic, 2);
867 spin_unlock_irqrestore(&ioapic_lock, flags);
869 printk("\n");
870 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
871 printk(KERN_DEBUG ".... register #00: %08X\n", *(int *)&reg_00);
872 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.ID);
873 if (reg_00.__reserved_1 || reg_00.__reserved_2)
874 UNEXPECTED_IO_APIC();
876 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
877 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.entries);
878 if ( (reg_01.entries != 0x0f) && /* older (Neptune) boards */
879 (reg_01.entries != 0x17) && /* typical ISA+PCI boards */
880 (reg_01.entries != 0x1b) && /* Compaq Proliant boards */
881 (reg_01.entries != 0x1f) && /* dual Xeon boards */
882 (reg_01.entries != 0x22) && /* bigger Xeon boards */
883 (reg_01.entries != 0x2E) &&
884 (reg_01.entries != 0x3F)
885 )
886 UNEXPECTED_IO_APIC();
888 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.PRQ);
889 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.version);
890 if ( (reg_01.version != 0x01) && /* 82489DX IO-APICs */
891 (reg_01.version != 0x02) && /* VIA */
892 (reg_01.version != 0x10) && /* oldest IO-APICs */
893 (reg_01.version != 0x11) && /* Pentium/Pro IO-APICs */
894 (reg_01.version != 0x13) && /* Xeon IO-APICs */
895 (reg_01.version != 0x20) /* Intel P64H (82806 AA) */
896 )
897 UNEXPECTED_IO_APIC();
898 if (reg_01.__reserved_1 || reg_01.__reserved_2)
899 UNEXPECTED_IO_APIC();
901 if (reg_01.version >= 0x10) {
902 printk(KERN_DEBUG ".... register #02: %08X\n", *(int *)&reg_02);
903 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.arbitration);
904 if (reg_02.__reserved_1 || reg_02.__reserved_2)
905 UNEXPECTED_IO_APIC();
906 }
908 printk(KERN_DEBUG ".... IRQ redirection table:\n");
910 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
911 " Stat Dest Deli Vect: \n");
913 for (i = 0; i <= reg_01.entries; i++) {
914 struct IO_APIC_route_entry entry;
916 spin_lock_irqsave(&ioapic_lock, flags);
917 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
918 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
919 spin_unlock_irqrestore(&ioapic_lock, flags);
921 printk(KERN_DEBUG " %02x %03X %02X ",
922 i,
923 entry.dest.logical.logical_dest,
924 entry.dest.physical.physical_dest
925 );
927 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
928 entry.mask,
929 entry.trigger,
930 entry.irr,
931 entry.polarity,
932 entry.delivery_status,
933 entry.dest_mode,
934 entry.delivery_mode,
935 entry.vector
936 );
937 }
938 }
939 printk(KERN_DEBUG "IRQ to pin mappings:\n");
940 for (i = 0; i < NR_IRQS; i++) {
941 struct irq_pin_list *entry = irq_2_pin + i;
942 if (entry->pin < 0)
943 continue;
944 printk(KERN_DEBUG "IRQ%d ", i);
945 for (;;) {
946 printk("-> %d:%d", entry->apic, entry->pin);
947 if (!entry->next)
948 break;
949 entry = irq_2_pin + entry->next;
950 }
951 printk("\n");
952 }
954 printk(KERN_INFO ".................................... done.\n");
956 return;
957 }
959 static void print_APIC_bitfield (int base)
960 {
961 unsigned int v;
962 int i, j;
964 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
965 for (i = 0; i < 8; i++) {
966 v = apic_read(base + i*0x10);
967 for (j = 0; j < 32; j++) {
968 if (v & (1<<j))
969 printk("1");
970 else
971 printk("0");
972 }
973 printk("\n");
974 }
975 }
977 void /*__init*/ print_local_APIC(void * dummy)
978 {
979 unsigned int v, ver, maxlvt;
981 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
982 smp_processor_id(), hard_smp_processor_id());
983 v = apic_read(APIC_ID);
984 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
985 v = apic_read(APIC_LVR);
986 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
987 ver = GET_APIC_VERSION(v);
988 maxlvt = get_maxlvt();
990 v = apic_read(APIC_TASKPRI);
991 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
993 if (APIC_INTEGRATED(ver)) { /* !82489DX */
994 v = apic_read(APIC_ARBPRI);
995 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
996 v & APIC_ARBPRI_MASK);
997 v = apic_read(APIC_PROCPRI);
998 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
999 }
1001 v = apic_read(APIC_EOI);
1002 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1003 v = apic_read(APIC_RRR);
1004 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1005 v = apic_read(APIC_LDR);
1006 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1007 v = apic_read(APIC_DFR);
1008 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1009 v = apic_read(APIC_SPIV);
1010 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1012 printk(KERN_DEBUG "... APIC ISR field:\n");
1013 print_APIC_bitfield(APIC_ISR);
1014 printk(KERN_DEBUG "... APIC TMR field:\n");
1015 print_APIC_bitfield(APIC_TMR);
1016 printk(KERN_DEBUG "... APIC IRR field:\n");
1017 print_APIC_bitfield(APIC_IRR);
1019 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1020 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1021 apic_write(APIC_ESR, 0);
1022 v = apic_read(APIC_ESR);
1023 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1026 v = apic_read(APIC_ICR);
1027 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1028 v = apic_read(APIC_ICR2);
1029 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1031 v = apic_read(APIC_LVTT);
1032 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1034 if (maxlvt > 3) { /* PC is LVT#4. */
1035 v = apic_read(APIC_LVTPC);
1036 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1038 v = apic_read(APIC_LVT0);
1039 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1040 v = apic_read(APIC_LVT1);
1041 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1043 if (maxlvt > 2) { /* ERR is LVT#3. */
1044 v = apic_read(APIC_LVTERR);
1045 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1048 v = apic_read(APIC_TMICT);
1049 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1050 v = apic_read(APIC_TMCCT);
1051 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1052 v = apic_read(APIC_TDCR);
1053 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1054 printk("\n");
1057 void print_all_local_APICs (void)
1059 smp_call_function(print_local_APIC, NULL, 1, 1);
1060 print_local_APIC(NULL);
1063 void /*__init*/ print_PIC(void)
1065 extern spinlock_t i8259A_lock;
1066 unsigned int v, flags;
1068 printk(KERN_DEBUG "\nprinting PIC contents\n");
1070 spin_lock_irqsave(&i8259A_lock, flags);
1072 v = inb(0xa1) << 8 | inb(0x21);
1073 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1075 v = inb(0xa0) << 8 | inb(0x20);
1076 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1078 outb(0x0b,0xa0);
1079 outb(0x0b,0x20);
1080 v = inb(0xa0) << 8 | inb(0x20);
1081 outb(0x0a,0xa0);
1082 outb(0x0a,0x20);
1084 spin_unlock_irqrestore(&i8259A_lock, flags);
1086 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1088 v = inb(0x4d1) << 8 | inb(0x4d0);
1089 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1092 static void __init enable_IO_APIC(void)
1094 struct IO_APIC_reg_01 reg_01;
1095 int i;
1096 unsigned long flags;
1098 for (i = 0; i < PIN_MAP_SIZE; i++) {
1099 irq_2_pin[i].pin = -1;
1100 irq_2_pin[i].next = 0;
1102 if (!pirqs_enabled)
1103 for (i = 0; i < MAX_PIRQS; i++)
1104 pirq_entries[i] = -1;
1106 /*
1107 * The number of IO-APIC IRQ registers (== #pins):
1108 */
1109 for (i = 0; i < nr_ioapics; i++) {
1110 spin_lock_irqsave(&ioapic_lock, flags);
1111 *(int *)&reg_01 = io_apic_read(i, 1);
1112 spin_unlock_irqrestore(&ioapic_lock, flags);
1113 nr_ioapic_registers[i] = reg_01.entries+1;
1116 /*
1117 * Do not trust the IO-APIC being empty at bootup
1118 */
1119 clear_IO_APIC();
1122 /*
1123 * Not an __init, needed by the reboot code
1124 */
1125 void disable_IO_APIC(void)
1127 /*
1128 * Clear the IO-APIC before rebooting:
1129 */
1130 clear_IO_APIC();
1132 disconnect_bsp_APIC();
1135 /*
1136 * function to set the IO-APIC physical IDs based on the
1137 * values stored in the MPC table.
1139 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1140 */
1142 static void __init setup_ioapic_ids_from_mpc (void)
1144 struct IO_APIC_reg_00 reg_00;
1145 unsigned long phys_id_present_map = phys_cpu_present_map;
1146 int apic;
1147 int i;
1148 unsigned char old_id;
1149 unsigned long flags;
1151 if (clustered_apic_mode)
1152 /* We don't have a good way to do this yet - hack */
1153 phys_id_present_map = (u_long) 0xf;
1154 /*
1155 * Set the IOAPIC ID to the value stored in the MPC table.
1156 */
1157 for (apic = 0; apic < nr_ioapics; apic++) {
1159 /* Read the register 0 value */
1160 spin_lock_irqsave(&ioapic_lock, flags);
1161 *(int *)&reg_00 = io_apic_read(apic, 0);
1162 spin_unlock_irqrestore(&ioapic_lock, flags);
1164 old_id = mp_ioapics[apic].mpc_apicid;
1166 if (mp_ioapics[apic].mpc_apicid >= apic_broadcast_id) {
1167 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1168 apic, mp_ioapics[apic].mpc_apicid);
1169 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1170 reg_00.ID);
1171 mp_ioapics[apic].mpc_apicid = reg_00.ID;
1174 /*
1175 * Sanity check, is the ID really free? Every APIC in a
1176 * system must have a unique ID or we get lots of nice
1177 * 'stuck on smp_invalidate_needed IPI wait' messages.
1178 * I/O APIC IDs no longer have any meaning for xAPICs and SAPICs.
1179 */
1180 if ((clustered_apic_mode != CLUSTERED_APIC_XAPIC) &&
1181 (phys_id_present_map & (1 << mp_ioapics[apic].mpc_apicid))) {
1182 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1183 apic, mp_ioapics[apic].mpc_apicid);
1184 for (i = 0; i < 0xf; i++)
1185 if (!(phys_id_present_map & (1 << i)))
1186 break;
1187 if (i >= apic_broadcast_id)
1188 panic("Max APIC ID exceeded!\n");
1189 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1190 i);
1191 phys_id_present_map |= 1 << i;
1192 mp_ioapics[apic].mpc_apicid = i;
1193 } else {
1194 printk("Setting %d in the phys_id_present_map\n", mp_ioapics[apic].mpc_apicid);
1195 phys_id_present_map |= 1 << mp_ioapics[apic].mpc_apicid;
1199 /*
1200 * We need to adjust the IRQ routing table
1201 * if the ID changed.
1202 */
1203 if (old_id != mp_ioapics[apic].mpc_apicid)
1204 for (i = 0; i < mp_irq_entries; i++)
1205 if (mp_irqs[i].mpc_dstapic == old_id)
1206 mp_irqs[i].mpc_dstapic
1207 = mp_ioapics[apic].mpc_apicid;
1209 /*
1210 * Read the right value from the MPC table and
1211 * write it into the ID register.
1212 */
1213 printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1214 mp_ioapics[apic].mpc_apicid);
1216 reg_00.ID = mp_ioapics[apic].mpc_apicid;
1217 spin_lock_irqsave(&ioapic_lock, flags);
1218 io_apic_write(apic, 0, *(int *)&reg_00);
1219 spin_unlock_irqrestore(&ioapic_lock, flags);
1221 /*
1222 * Sanity check
1223 */
1224 spin_lock_irqsave(&ioapic_lock, flags);
1225 *(int *)&reg_00 = io_apic_read(apic, 0);
1226 spin_unlock_irqrestore(&ioapic_lock, flags);
1227 if (reg_00.ID != mp_ioapics[apic].mpc_apicid)
1228 panic("could not set ID!\n");
1229 else
1230 printk(" ok.\n");
1234 /*
1235 * There is a nasty bug in some older SMP boards, their mptable lies
1236 * about the timer IRQ. We do the following to work around the situation:
1238 * - timer IRQ defaults to IO-APIC IRQ
1239 * - if this function detects that timer IRQs are defunct, then we fall
1240 * back to ISA timer IRQs
1241 */
1242 static int __init timer_irq_works(void)
1244 unsigned int t1 = jiffies;
1246 sti();
1247 /* Let ten ticks pass... */
1248 mdelay((10 * 1000) / HZ);
1250 /*
1251 * Expect a few ticks at least, to be sure some possible
1252 * glue logic does not lock up after one or two first
1253 * ticks in a non-ExtINT mode. Also the local APIC
1254 * might have cached one ExtINT interrupt. Finally, at
1255 * least one tick may be lost due to delays.
1256 */
1257 if (jiffies - t1 > 4)
1258 return 1;
1260 return 0;
1263 /*
1264 * In the SMP+IOAPIC case it might happen that there are an unspecified
1265 * number of pending IRQ events unhandled. These cases are very rare,
1266 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1267 * better to do it this way as thus we do not have to be aware of
1268 * 'pending' interrupts in the IRQ path, except at this point.
1269 */
1270 /*
1271 * Edge triggered needs to resend any interrupt
1272 * that was delayed but this is now handled in the device
1273 * independent code.
1274 */
1275 #define enable_edge_ioapic_irq unmask_IO_APIC_irq
1277 static void disable_edge_ioapic_irq (unsigned int irq) { /* nothing */ }
1279 /*
1280 * Starting up a edge-triggered IO-APIC interrupt is
1281 * nasty - we need to make sure that we get the edge.
1282 * If it is already asserted for some reason, we need
1283 * return 1 to indicate that is was pending.
1285 * This is not complete - we should be able to fake
1286 * an edge even if it isn't on the 8259A...
1287 */
1289 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1291 int was_pending = 0;
1292 unsigned long flags;
1294 spin_lock_irqsave(&ioapic_lock, flags);
1295 if (irq < 16) {
1296 disable_8259A_irq(irq);
1297 if (i8259A_irq_pending(irq))
1298 was_pending = 1;
1300 __unmask_IO_APIC_irq(irq);
1301 spin_unlock_irqrestore(&ioapic_lock, flags);
1303 return was_pending;
1306 #define shutdown_edge_ioapic_irq disable_edge_ioapic_irq
1308 /*
1309 * Once we have recorded IRQ_PENDING already, we can mask the
1310 * interrupt for real. This prevents IRQ storms from unhandled
1311 * devices.
1312 */
1313 static void ack_edge_ioapic_irq(unsigned int irq)
1315 balance_irq(irq);
1316 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1317 == (IRQ_PENDING | IRQ_DISABLED))
1318 mask_IO_APIC_irq(irq);
1319 ack_APIC_irq();
1322 static void end_edge_ioapic_irq (unsigned int i) { /* nothing */ }
1325 /*
1326 * Level triggered interrupts can just be masked,
1327 * and shutting down and starting up the interrupt
1328 * is the same as enabling and disabling them -- except
1329 * with a startup need to return a "was pending" value.
1331 * Level triggered interrupts are special because we
1332 * do not touch any IO-APIC register while handling
1333 * them. We ack the APIC in the end-IRQ handler, not
1334 * in the start-IRQ-handler. Protection against reentrance
1335 * from the same interrupt is still provided, both by the
1336 * generic IRQ layer and by the fact that an unacked local
1337 * APIC does not accept IRQs.
1338 */
1339 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1341 unmask_IO_APIC_irq(irq);
1343 return 0; /* don't check for pending */
1346 #define shutdown_level_ioapic_irq mask_IO_APIC_irq
1347 #define enable_level_ioapic_irq unmask_IO_APIC_irq
1348 #define disable_level_ioapic_irq mask_IO_APIC_irq
1350 static void end_level_ioapic_irq (unsigned int irq)
1352 unsigned long v;
1353 int i;
1355 balance_irq(irq);
1357 /*
1358 * It appears there is an erratum which affects at least version 0x11
1359 * of I/O APIC (that's the 82093AA and cores integrated into various
1360 * chipsets). Under certain conditions a level-triggered interrupt is
1361 * erroneously delivered as edge-triggered one but the respective IRR
1362 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1363 * message but it will never arrive and further interrupts are blocked
1364 * from the source. The exact reason is so far unknown, but the
1365 * phenomenon was observed when two consecutive interrupt requests
1366 * from a given source get delivered to the same CPU and the source is
1367 * temporarily disabled in between.
1369 * A workaround is to simulate an EOI message manually. We achieve it
1370 * by setting the trigger mode to edge and then to level when the edge
1371 * trigger mode gets detected in the TMR of a local APIC for a
1372 * level-triggered interrupt. We mask the source for the time of the
1373 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1374 * The idea is from Manfred Spraul. --macro
1375 */
1376 i = IO_APIC_VECTOR(irq);
1377 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1379 ack_APIC_irq();
1381 if (!(v & (1 << (i & 0x1f)))) {
1382 #ifdef APIC_LOCKUP_DEBUG
1383 struct irq_pin_list *entry;
1384 #endif
1386 #ifdef APIC_MISMATCH_DEBUG
1387 atomic_inc(&irq_mis_count);
1388 #endif
1389 spin_lock(&ioapic_lock);
1390 __mask_and_edge_IO_APIC_irq(irq);
1391 #ifdef APIC_LOCKUP_DEBUG
1392 for (entry = irq_2_pin + irq;;) {
1393 unsigned int reg;
1395 if (entry->pin == -1)
1396 break;
1397 reg = io_apic_read(entry->apic, 0x10 + entry->pin * 2);
1398 if (reg & 0x00004000)
1399 printk(KERN_CRIT "Aieee!!! Remote IRR"
1400 " still set after unlock!\n");
1401 if (!entry->next)
1402 break;
1403 entry = irq_2_pin + entry->next;
1405 #endif
1406 __unmask_and_level_IO_APIC_irq(irq);
1407 spin_unlock(&ioapic_lock);
1411 static void mask_and_ack_level_ioapic_irq (unsigned int irq) { /* nothing */ }
1413 /*
1414 * Level and edge triggered IO-APIC interrupts need different handling,
1415 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1416 * handled with the level-triggered descriptor, but that one has slightly
1417 * more overhead. Level-triggered interrupts cannot be handled with the
1418 * edge-triggered handler, without risking IRQ storms and other ugly
1419 * races.
1420 */
1422 static struct hw_interrupt_type ioapic_edge_irq_type = {
1423 "IO-APIC-edge",
1424 startup_edge_ioapic_irq,
1425 shutdown_edge_ioapic_irq,
1426 enable_edge_ioapic_irq,
1427 disable_edge_ioapic_irq,
1428 ack_edge_ioapic_irq,
1429 end_edge_ioapic_irq,
1430 set_ioapic_affinity,
1431 };
1433 static struct hw_interrupt_type ioapic_level_irq_type = {
1434 "IO-APIC-level",
1435 startup_level_ioapic_irq,
1436 shutdown_level_ioapic_irq,
1437 enable_level_ioapic_irq,
1438 disable_level_ioapic_irq,
1439 mask_and_ack_level_ioapic_irq,
1440 end_level_ioapic_irq,
1441 set_ioapic_affinity,
1442 };
1444 static inline void init_IO_APIC_traps(void)
1446 int irq;
1448 /*
1449 * NOTE! The local APIC isn't very good at handling
1450 * multiple interrupts at the same interrupt level.
1451 * As the interrupt level is determined by taking the
1452 * vector number and shifting that right by 4, we
1453 * want to spread these out a bit so that they don't
1454 * all fall in the same interrupt level.
1456 * Also, we've got to be careful not to trash gate
1457 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1458 */
1459 for (irq = 0; irq < NR_IRQS ; irq++) {
1460 if (IO_APIC_IRQ(irq) && !IO_APIC_VECTOR(irq)) {
1461 /*
1462 * Hmm.. We don't have an entry for this,
1463 * so default to an old-fashioned 8259
1464 * interrupt if we can..
1465 */
1466 if (irq < 16)
1467 make_8259A_irq(irq);
1468 else
1469 /* Strange. Oh, well.. */
1470 irq_desc[irq].handler = &no_irq_type;
1475 static void enable_lapic_irq (unsigned int irq)
1477 unsigned long v;
1479 v = apic_read(APIC_LVT0);
1480 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1483 static void disable_lapic_irq (unsigned int irq)
1485 unsigned long v;
1487 v = apic_read(APIC_LVT0);
1488 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1491 static void ack_lapic_irq (unsigned int irq)
1493 ack_APIC_irq();
1496 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1498 static struct hw_interrupt_type lapic_irq_type = {
1499 "local-APIC-edge",
1500 NULL, /* startup_irq() not used for IRQ0 */
1501 NULL, /* shutdown_irq() not used for IRQ0 */
1502 enable_lapic_irq,
1503 disable_lapic_irq,
1504 ack_lapic_irq,
1505 end_lapic_irq
1506 };
1508 static void enable_NMI_through_LVT0 (void * dummy)
1510 unsigned int v, ver;
1512 ver = apic_read(APIC_LVR);
1513 ver = GET_APIC_VERSION(ver);
1514 v = APIC_DM_NMI; /* unmask and set to NMI */
1515 if (!APIC_INTEGRATED(ver)) /* 82489DX */
1516 v |= APIC_LVT_LEVEL_TRIGGER;
1517 apic_write_around(APIC_LVT0, v);
1520 static void setup_nmi (void)
1522 /*
1523 * Dirty trick to enable the NMI watchdog ...
1524 * We put the 8259A master into AEOI mode and
1525 * unmask on all local APICs LVT0 as NMI.
1527 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1528 * is from Maciej W. Rozycki - so we do not have to EOI from
1529 * the NMI handler or the timer interrupt.
1530 */
1531 printk(KERN_INFO "activating NMI Watchdog ...");
1533 smp_call_function(enable_NMI_through_LVT0, NULL, 1, 1);
1534 enable_NMI_through_LVT0(NULL);
1536 printk(" done.\n");
1539 /*
1540 * This looks a bit hackish but it's about the only one way of sending
1541 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1542 * not support the ExtINT mode, unfortunately. We need to send these
1543 * cycles as some i82489DX-based boards have glue logic that keeps the
1544 * 8259A interrupt line asserted until INTA. --macro
1545 */
1546 static inline void unlock_ExtINT_logic(void)
1548 int pin, i;
1549 struct IO_APIC_route_entry entry0, entry1;
1550 unsigned char save_control, save_freq_select;
1551 unsigned long flags;
1553 pin = find_isa_irq_pin(8, mp_INT);
1554 if (pin == -1)
1555 return;
1557 spin_lock_irqsave(&ioapic_lock, flags);
1558 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1559 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1560 spin_unlock_irqrestore(&ioapic_lock, flags);
1561 clear_IO_APIC_pin(0, pin);
1563 memset(&entry1, 0, sizeof(entry1));
1565 entry1.dest_mode = 0; /* physical delivery */
1566 entry1.mask = 0; /* unmask IRQ now */
1567 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1568 entry1.delivery_mode = dest_ExtINT;
1569 entry1.polarity = entry0.polarity;
1570 entry1.trigger = 0;
1571 entry1.vector = 0;
1573 spin_lock_irqsave(&ioapic_lock, flags);
1574 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1575 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1576 spin_unlock_irqrestore(&ioapic_lock, flags);
1578 save_control = CMOS_READ(RTC_CONTROL);
1579 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1580 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1581 RTC_FREQ_SELECT);
1582 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1584 i = 100;
1585 while (i-- > 0) {
1586 mdelay(10);
1587 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1588 i -= 10;
1591 CMOS_WRITE(save_control, RTC_CONTROL);
1592 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1593 clear_IO_APIC_pin(0, pin);
1595 spin_lock_irqsave(&ioapic_lock, flags);
1596 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1597 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1598 spin_unlock_irqrestore(&ioapic_lock, flags);
1601 /*
1602 * This code may look a bit paranoid, but it's supposed to cooperate with
1603 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1604 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1605 * fanatically on his truly buggy board.
1606 */
1607 static inline void check_timer(void)
1609 extern int timer_ack;
1610 int pin1, pin2;
1611 int vector;
1613 /*
1614 * get/set the timer IRQ vector:
1615 */
1616 disable_8259A_irq(0);
1617 vector = assign_irq_vector(0);
1618 set_intr_gate(vector, interrupt[0]);
1620 /*
1621 * Subtle, code in do_timer_interrupt() expects an AEOI
1622 * mode for the 8259A whenever interrupts are routed
1623 * through I/O APICs. Also IRQ0 has to be enabled in
1624 * the 8259A which implies the virtual wire has to be
1625 * disabled in the local APIC.
1626 */
1627 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1628 init_8259A(1);
1629 timer_ack = 1;
1630 enable_8259A_irq(0);
1632 pin1 = find_isa_irq_pin(0, mp_INT);
1633 pin2 = find_isa_irq_pin(0, mp_ExtINT);
1635 printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1637 if (pin1 != -1) {
1638 /*
1639 * Ok, does IRQ0 through the IOAPIC work?
1640 */
1641 unmask_IO_APIC_irq(0);
1642 if (timer_irq_works())
1643 return;
1644 clear_IO_APIC_pin(0, pin1);
1645 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1648 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1649 if (pin2 != -1) {
1650 printk("\n..... (found pin %d) ...", pin2);
1651 /*
1652 * legacy devices should be connected to IO APIC #0
1653 */
1654 setup_ExtINT_IRQ0_pin(pin2, vector);
1655 if (timer_irq_works()) {
1656 printk("works.\n");
1657 if (pin1 != -1)
1658 replace_pin_at_irq(0, 0, pin1, 0, pin2);
1659 else
1660 add_pin_to_irq(0, 0, pin2);
1661 return;
1663 /*
1664 * Cleanup, just in case ...
1665 */
1666 clear_IO_APIC_pin(0, pin2);
1668 printk(" failed.\n");
1670 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1672 disable_8259A_irq(0);
1673 irq_desc[0].handler = &lapic_irq_type;
1674 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1675 enable_8259A_irq(0);
1677 if (timer_irq_works()) {
1678 printk(" works.\n");
1679 return;
1681 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1682 printk(" failed.\n");
1684 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1686 init_8259A(0);
1687 make_8259A_irq(0);
1688 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1690 unlock_ExtINT_logic();
1692 if (timer_irq_works()) {
1693 printk(" works.\n");
1694 return;
1696 printk(" failed :(.\n");
1697 panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
1700 /*
1702 * IRQ's that are handled by the old PIC in all cases:
1703 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1704 * Linux doesn't really care, as it's not actually used
1705 * for any interrupt handling anyway.
1706 * - There used to be IRQ13 here as well, but all
1707 * MPS-compliant must not use it for FPU coupling and we
1708 * want to use exception 16 anyway. And there are
1709 * systems who connect it to an I/O APIC for other uses.
1710 * Thus we don't mark it special any longer.
1712 * Additionally, something is definitely wrong with irq9
1713 * on PIIX4 boards.
1714 */
1715 #define PIC_IRQS (1<<2)
1717 void __init setup_IO_APIC(void)
1719 enable_IO_APIC();
1721 io_apic_irqs = ~PIC_IRQS;
1722 printk("ENABLING IO-APIC IRQs\n");
1724 /*
1725 * Set up the IO-APIC IRQ routing table by parsing the MP-BIOS
1726 * mptable:
1727 */
1728 setup_ioapic_ids_from_mpc();
1729 sync_Arb_IDs();
1730 setup_IO_APIC_irqs();
1731 init_IO_APIC_traps();
1732 check_timer();
1733 print_IO_APIC();
1736 #endif /* CONFIG_X86_IO_APIC */