debuggers.hg

view xen/arch/x86/cpu/intel.c @ 21940:c9e7850ec9a1

x86: unmask CPUID levels on Intel CPUs

If the CPUID limit bit in MSR_IA32_MISC_ENABLE is set, clear it to
make all CPUID information available. This is required for some
features to work, such as MWAIT in cpuidle, get cpu topology, XSAVE,
etc.

Signed-off-by: Wei Gang <gang.wei@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jul 30 11:36:34 2010 +0100 (2010-07-30)
parents 12f0618400de
children ae0cd4e5cc01
line source
1 #include <xen/config.h>
2 #include <xen/init.h>
3 #include <xen/kernel.h>
4 #include <xen/string.h>
5 #include <xen/bitops.h>
6 #include <xen/smp.h>
7 #include <asm/processor.h>
8 #include <asm/msr.h>
9 #include <asm/uaccess.h>
10 #include <asm/mpspec.h>
11 #include <asm/apic.h>
12 #include <asm/i387.h>
13 #include <mach_apic.h>
14 #include <asm/hvm/support.h>
15 #include <asm/setup.h>
17 #include "cpu.h"
19 #define select_idle_routine(x) ((void)0)
21 extern int trap_init_f00f_bug(void);
23 static int use_xsave = 1;
24 boolean_param("xsave", use_xsave);
26 #ifdef CONFIG_X86_INTEL_USERCOPY
27 /*
28 * Alignment at which movsl is preferred for bulk memory copies.
29 */
30 struct movsl_mask movsl_mask __read_mostly;
31 #endif
33 /*
34 * opt_cpuid_mask_ecx/edx: cpuid.1[ecx, edx] feature mask.
35 * For example, E8400[Intel Core 2 Duo Processor series] ecx = 0x0008E3FD,
36 * edx = 0xBFEBFBFF when executing CPUID.EAX = 1 normally. If you want to
37 * 'rev down' to E8400, you can set these values in these Xen boot parameters.
38 */
39 static void __devinit set_cpuidmask(const struct cpuinfo_x86 *c)
40 {
41 const char *extra = "";
43 if (!~(opt_cpuid_mask_ecx & opt_cpuid_mask_edx &
44 opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx))
45 return;
47 /* Only family 6 supports this feature */
48 switch ((c->x86 == 6) * c->x86_model) {
49 case 0x17:
50 if ((c->x86_mask & 0x0f) < 4)
51 break;
52 /* fall through */
53 case 0x1d:
54 wrmsr(MSR_INTEL_CPUID_FEATURE_MASK,
55 opt_cpuid_mask_ecx,
56 opt_cpuid_mask_edx);
57 if (!~(opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx))
58 return;
59 extra = "extended ";
60 break;
61 /*
62 * CPU supports this feature if the processor signature meets the following:
63 * (CPUID.(EAX=01h):EAX) > 000106A2h, or
64 * (CPUID.(EAX=01h):EAX) == 000106Exh, 0002065xh, 000206Cxh, 000206Exh, or 000206Fxh
65 *
66 */
67 case 0x1a:
68 if ((c->x86_mask & 0x0f) <= 2)
69 break;
70 /* fall through */
71 case 0x1e: case 0x1f:
72 case 0x25: case 0x2c: case 0x2e: case 0x2f:
73 wrmsr(MSR_INTEL_CPUID1_FEATURE_MASK,
74 opt_cpuid_mask_ecx,
75 opt_cpuid_mask_edx);
76 wrmsr(MSR_INTEL_CPUID80000001_FEATURE_MASK,
77 opt_cpuid_mask_ext_ecx,
78 opt_cpuid_mask_ext_edx);
79 return;
80 }
82 printk(XENLOG_ERR "Cannot set CPU feature mask on CPU#%d\n",
83 smp_processor_id());
84 }
86 void __devinit early_intel_workaround(struct cpuinfo_x86 *c)
87 {
88 if (c->x86_vendor != X86_VENDOR_INTEL)
89 return;
90 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
91 if (c->x86 == 15 && c->x86_cache_alignment == 64)
92 c->x86_cache_alignment = 128;
94 /* Unmask CPUID levels if masked: */
95 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
96 u64 misc_enable;
98 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
100 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
101 misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
102 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
103 c->cpuid_level = cpuid_eax(0);
104 printk("revised cpuid_level = %d\n", c->cpuid_level);
105 }
106 }
107 }
109 /*
110 * P4 Xeon errata 037 workaround.
111 * Hardware prefetcher may cause stale data to be loaded into the cache.
112 */
113 static void __devinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
114 {
115 unsigned long lo, hi;
117 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
118 rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
119 if ((lo & (1<<9)) == 0) {
120 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
121 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
122 lo |= (1<<9); /* Disable hw prefetching */
123 wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
124 }
125 }
126 }
129 /*
130 * find out the number of processor cores on the die
131 */
132 static int __devinit num_cpu_cores(struct cpuinfo_x86 *c)
133 {
134 unsigned int eax, ebx, ecx, edx;
136 if (c->cpuid_level < 4)
137 return 1;
139 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
140 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
141 if (eax & 0x1f)
142 return ((eax >> 26) + 1);
143 else
144 return 1;
145 }
147 static void __devinit init_intel(struct cpuinfo_x86 *c)
148 {
149 unsigned int l2 = 0;
150 char *p = NULL;
152 #ifdef CONFIG_X86_F00F_BUG
153 /*
154 * All current models of Pentium and Pentium with MMX technology CPUs
155 * have the F0 0F bug, which lets nonprivileged users lock up the system.
156 * Note that the workaround only should be initialized once...
157 */
158 c->f00f_bug = 0;
159 if ( c->x86 == 5 ) {
160 static int f00f_workaround_enabled = 0;
162 c->f00f_bug = 1;
163 if ( !f00f_workaround_enabled ) {
164 trap_init_f00f_bug();
165 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
166 f00f_workaround_enabled = 1;
167 }
168 }
169 #endif
171 /* Detect the extended topology information if available */
172 detect_extended_topology(c);
174 select_idle_routine(c);
175 l2 = init_intel_cacheinfo(c);
176 if (c->cpuid_level > 9) {
177 unsigned eax = cpuid_eax(10);
178 /* Check for version and the number of counters */
179 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
180 set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability);
181 }
183 /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
184 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
185 clear_bit(X86_FEATURE_SEP, c->x86_capability);
187 /* Names for the Pentium II/Celeron processors
188 detectable only by also checking the cache size.
189 Dixon is NOT a Celeron. */
190 if (c->x86 == 6) {
191 switch (c->x86_model) {
192 case 5:
193 if (c->x86_mask == 0) {
194 if (l2 == 0)
195 p = "Celeron (Covington)";
196 else if (l2 == 256)
197 p = "Mobile Pentium II (Dixon)";
198 }
199 break;
201 case 6:
202 if (l2 == 128)
203 p = "Celeron (Mendocino)";
204 else if (c->x86_mask == 0 || c->x86_mask == 5)
205 p = "Celeron-A";
206 break;
208 case 8:
209 if (l2 == 128)
210 p = "Celeron (Coppermine)";
211 break;
212 }
213 }
215 if ( p )
216 safe_strcpy(c->x86_model_id, p);
218 if ( !cpu_has(c, X86_FEATURE_XTOPOLOGY) )
219 {
220 c->x86_max_cores = num_cpu_cores(c);
221 detect_ht(c);
222 }
224 set_cpuidmask(c);
226 /* Work around errata */
227 Intel_errata_workarounds(c);
229 #ifdef CONFIG_X86_INTEL_USERCOPY
230 /*
231 * Set up the preferred alignment for movsl bulk memory moves
232 */
233 switch (c->x86) {
234 case 4: /* 486: untested */
235 break;
236 case 5: /* Old Pentia: untested */
237 break;
238 case 6: /* PII/PIII only like movsl with 8-byte alignment */
239 movsl_mask.mask = 7;
240 break;
241 case 15: /* P4 is OK down to 8-byte alignment */
242 movsl_mask.mask = 7;
243 break;
244 }
245 #endif
247 if (c->x86 == 15)
248 set_bit(X86_FEATURE_P4, c->x86_capability);
249 if (c->x86 == 6)
250 set_bit(X86_FEATURE_P3, c->x86_capability);
251 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
252 (c->x86 == 0x6 && c->x86_model >= 0x0e))
253 set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
254 if (cpuid_edx(0x80000007) & (1u<<8)) {
255 set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
256 set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability);
257 set_bit(X86_FEATURE_TSC_RELIABLE, c->x86_capability);
258 }
259 if ((c->cpuid_level >= 0x00000006) &&
260 (cpuid_eax(0x00000006) & (1u<<2)))
261 set_bit(X86_FEATURE_ARAT, c->x86_capability);
263 if ( !use_xsave )
264 clear_bit(X86_FEATURE_XSAVE, boot_cpu_data.x86_capability);
266 if ( cpu_has_xsave )
267 xsave_init();
268 }
271 static unsigned int intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
272 {
273 /* Intel PIII Tualatin. This comes in two flavours.
274 * One has 256kb of cache, the other 512. We have no way
275 * to determine which, so we use a boottime override
276 * for the 512kb model, and assume 256 otherwise.
277 */
278 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
279 size = 256;
280 return size;
281 }
283 static struct cpu_dev intel_cpu_dev __devinitdata = {
284 .c_vendor = "Intel",
285 .c_ident = { "GenuineIntel" },
286 .c_models = {
287 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
288 {
289 [0] = "486 DX-25/33",
290 [1] = "486 DX-50",
291 [2] = "486 SX",
292 [3] = "486 DX/2",
293 [4] = "486 SL",
294 [5] = "486 SX/2",
295 [7] = "486 DX/2-WB",
296 [8] = "486 DX/4",
297 [9] = "486 DX/4-WB"
298 }
299 },
300 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
301 {
302 [0] = "Pentium 60/66 A-step",
303 [1] = "Pentium 60/66",
304 [2] = "Pentium 75 - 200",
305 [3] = "OverDrive PODP5V83",
306 [4] = "Pentium MMX",
307 [7] = "Mobile Pentium 75 - 200",
308 [8] = "Mobile Pentium MMX"
309 }
310 },
311 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
312 {
313 [0] = "Pentium Pro A-step",
314 [1] = "Pentium Pro",
315 [3] = "Pentium II (Klamath)",
316 [4] = "Pentium II (Deschutes)",
317 [5] = "Pentium II (Deschutes)",
318 [6] = "Mobile Pentium II",
319 [7] = "Pentium III (Katmai)",
320 [8] = "Pentium III (Coppermine)",
321 [10] = "Pentium III (Cascades)",
322 [11] = "Pentium III (Tualatin)",
323 }
324 },
325 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
326 {
327 [0] = "Pentium 4 (Unknown)",
328 [1] = "Pentium 4 (Willamette)",
329 [2] = "Pentium 4 (Northwood)",
330 [4] = "Pentium 4 (Foster)",
331 [5] = "Pentium 4 (Foster)",
332 }
333 },
334 },
335 .c_init = init_intel,
336 .c_identify = generic_identify,
337 .c_size_cache = intel_size_cache,
338 };
340 int __init intel_cpu_init(void)
341 {
342 cpu_devs[X86_VENDOR_INTEL] = &intel_cpu_dev;
343 return 0;
344 }
346 // arch_initcall(intel_cpu_init);