debuggers.hg

view xen/include/asm-x86/msr-index.h @ 21940:c9e7850ec9a1

x86: unmask CPUID levels on Intel CPUs

If the CPUID limit bit in MSR_IA32_MISC_ENABLE is set, clear it to
make all CPUID information available. This is required for some
features to work, such as MWAIT in cpuidle, get cpu topology, XSAVE,
etc.

Signed-off-by: Wei Gang <gang.wei@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jul 30 11:36:34 2010 +0100 (2010-07-30)
parents f483b5ce7be2
children 1a3b8b84e58b
line source
1 #ifndef __ASM_MSR_INDEX_H
2 #define __ASM_MSR_INDEX_H
4 /* CPU model specific register (MSR) numbers */
6 /* x86-64 specific MSRs */
7 #define MSR_EFER 0xc0000080 /* extended feature register */
8 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
9 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
10 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
11 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
12 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
13 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
14 #define MSR_SHADOW_GS_BASE 0xc0000102 /* SwapGS GS shadow */
15 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
17 /* EFER bits: */
18 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
19 #define _EFER_LME 8 /* Long mode enable */
20 #define _EFER_LMA 10 /* Long mode active (read-only) */
21 #define _EFER_NX 11 /* No execute enable */
22 #define _EFER_SVME 12 /* AMD: SVM enable */
23 #define _EFER_LMSLE 13 /* AMD: Long-mode segment limit enable */
24 #define _EFER_FFXSE 14 /* AMD: Fast FXSAVE/FXRSTOR enable */
26 #define EFER_SCE (1<<_EFER_SCE)
27 #define EFER_LME (1<<_EFER_LME)
28 #define EFER_LMA (1<<_EFER_LMA)
29 #define EFER_NX (1<<_EFER_NX)
30 #define EFER_SVME (1<<_EFER_SVME)
31 #define EFER_LMSLE (1<<_EFER_LMSLE)
32 #define EFER_FFXSE (1<<_EFER_FFXSE)
34 /* Intel MSRs. Some also available on other CPUs */
35 #define MSR_IA32_PERFCTR0 0x000000c1
36 #define MSR_IA32_PERFCTR1 0x000000c2
37 #define MSR_FSB_FREQ 0x000000cd
39 #define MSR_MTRRcap 0x000000fe
40 #define MSR_IA32_BBL_CR_CTL 0x00000119
42 #define MSR_IA32_SYSENTER_CS 0x00000174
43 #define MSR_IA32_SYSENTER_ESP 0x00000175
44 #define MSR_IA32_SYSENTER_EIP 0x00000176
46 #define MSR_IA32_MCG_CAP 0x00000179
47 #define MSR_IA32_MCG_STATUS 0x0000017a
48 #define MSR_IA32_MCG_CTL 0x0000017b
50 #define MSR_IA32_PEBS_ENABLE 0x000003f1
51 #define MSR_IA32_DS_AREA 0x00000600
52 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
54 #define MSR_MTRRfix64K_00000 0x00000250
55 #define MSR_MTRRfix16K_80000 0x00000258
56 #define MSR_MTRRfix16K_A0000 0x00000259
57 #define MSR_MTRRfix4K_C0000 0x00000268
58 #define MSR_MTRRfix4K_C8000 0x00000269
59 #define MSR_MTRRfix4K_D0000 0x0000026a
60 #define MSR_MTRRfix4K_D8000 0x0000026b
61 #define MSR_MTRRfix4K_E0000 0x0000026c
62 #define MSR_MTRRfix4K_E8000 0x0000026d
63 #define MSR_MTRRfix4K_F0000 0x0000026e
64 #define MSR_MTRRfix4K_F8000 0x0000026f
65 #define MSR_MTRRdefType 0x000002ff
67 #define MSR_IA32_DEBUGCTLMSR 0x000001d9
68 #define MSR_IA32_LASTBRANCHFROMIP 0x000001db
69 #define MSR_IA32_LASTBRANCHTOIP 0x000001dc
70 #define MSR_IA32_LASTINTFROMIP 0x000001dd
71 #define MSR_IA32_LASTINTTOIP 0x000001de
73 #define MSR_IA32_MTRR_PHYSBASE0 0x00000200
74 #define MSR_IA32_MTRR_PHYSMASK0 0x00000201
75 #define MSR_IA32_MTRR_PHYSBASE1 0x00000202
76 #define MSR_IA32_MTRR_PHYSMASK1 0x00000203
77 #define MSR_IA32_MTRR_PHYSBASE2 0x00000204
78 #define MSR_IA32_MTRR_PHYSMASK2 0x00000205
79 #define MSR_IA32_MTRR_PHYSBASE3 0x00000206
80 #define MSR_IA32_MTRR_PHYSMASK3 0x00000207
81 #define MSR_IA32_MTRR_PHYSBASE4 0x00000208
82 #define MSR_IA32_MTRR_PHYSMASK4 0x00000209
83 #define MSR_IA32_MTRR_PHYSBASE5 0x0000020a
84 #define MSR_IA32_MTRR_PHYSMASK5 0x0000020b
85 #define MSR_IA32_MTRR_PHYSBASE6 0x0000020c
86 #define MSR_IA32_MTRR_PHYSMASK6 0x0000020d
87 #define MSR_IA32_MTRR_PHYSBASE7 0x0000020e
88 #define MSR_IA32_MTRR_PHYSMASK7 0x0000020f
90 #define MSR_IA32_CR_PAT 0x00000277
91 #define MSR_IA32_CR_PAT_RESET 0x0007040600070406ULL
93 #define MSR_IA32_MC0_CTL 0x00000400
94 #define MSR_IA32_MC0_STATUS 0x00000401
95 #define MSR_IA32_MC0_ADDR 0x00000402
96 #define MSR_IA32_MC0_MISC 0x00000403
97 #define MSR_IA32_MC0_CTL2 0x00000280
98 #define CMCI_EN (1UL<<30)
99 #define CMCI_THRESHOLD_MASK 0x7FFF
101 #define MSR_IA32_MC1_CTL 0x00000404
102 #define MSR_IA32_MC1_CTL2 0x00000281
103 #define MSR_IA32_MC1_STATUS 0x00000405
104 #define MSR_IA32_MC1_ADDR 0x00000406
105 #define MSR_IA32_MC1_MISC 0x00000407
107 #define MSR_IA32_MC2_CTL 0x00000408
108 #define MSR_IA32_MC2_CTL2 0x00000282
109 #define MSR_IA32_MC2_STATUS 0x00000409
110 #define MSR_IA32_MC2_ADDR 0x0000040A
111 #define MSR_IA32_MC2_MISC 0x0000040B
113 #define MSR_IA32_MC3_CTL2 0x00000283
114 #define MSR_IA32_MC3_CTL 0x0000040C
115 #define MSR_IA32_MC3_STATUS 0x0000040D
116 #define MSR_IA32_MC3_ADDR 0x0000040E
117 #define MSR_IA32_MC3_MISC 0x0000040F
119 #define MSR_IA32_MC4_CTL2 0x00000284
120 #define MSR_IA32_MC4_CTL 0x00000410
121 #define MSR_IA32_MC4_STATUS 0x00000411
122 #define MSR_IA32_MC4_ADDR 0x00000412
123 #define MSR_IA32_MC4_MISC 0x00000413
125 #define MSR_IA32_MC5_CTL2 0x00000285
126 #define MSR_IA32_MC5_CTL 0x00000414
127 #define MSR_IA32_MC5_STATUS 0x00000415
128 #define MSR_IA32_MC5_ADDR 0x00000416
129 #define MSR_IA32_MC5_MISC 0x00000417
131 #define MSR_IA32_MC6_CTL2 0x00000286
132 #define MSR_IA32_MC6_CTL 0x00000418
133 #define MSR_IA32_MC6_STATUS 0x00000419
134 #define MSR_IA32_MC6_ADDR 0x0000041A
135 #define MSR_IA32_MC6_MISC 0x0000041B
137 #define MSR_IA32_MC7_CTL2 0x00000287
138 #define MSR_IA32_MC7_CTL 0x0000041C
139 #define MSR_IA32_MC7_STATUS 0x0000041D
140 #define MSR_IA32_MC7_ADDR 0x0000041E
141 #define MSR_IA32_MC7_MISC 0x0000041F
143 #define MSR_IA32_MC8_CTL2 0x00000288
144 #define MSR_IA32_MC8_CTL 0x00000420
145 #define MSR_IA32_MC8_STATUS 0x00000421
146 #define MSR_IA32_MC8_ADDR 0x00000422
147 #define MSR_IA32_MC8_MISC 0x00000423
149 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
150 #define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
151 #define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
152 #define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
154 #define MSR_P6_PERFCTR0 0x000000c1
155 #define MSR_P6_PERFCTR1 0x000000c2
156 #define MSR_P6_EVNTSEL0 0x00000186
157 #define MSR_P6_EVNTSEL1 0x00000187
159 /* MSRs for Intel cpuid feature mask */
160 #define MSR_INTEL_CPUID_FEATURE_MASK 0x00000478
161 #define MSR_INTEL_CPUID1_FEATURE_MASK 0x00000130
162 #define MSR_INTEL_CPUID80000001_FEATURE_MASK 0x00000131
164 /* MSRs & bits used for VMX enabling */
165 #define MSR_IA32_VMX_BASIC 0x480
166 #define MSR_IA32_VMX_PINBASED_CTLS 0x481
167 #define MSR_IA32_VMX_PROCBASED_CTLS 0x482
168 #define MSR_IA32_VMX_EXIT_CTLS 0x483
169 #define MSR_IA32_VMX_ENTRY_CTLS 0x484
170 #define MSR_IA32_VMX_MISC 0x485
171 #define MSR_IA32_VMX_CR0_FIXED0 0x486
172 #define MSR_IA32_VMX_CR0_FIXED1 0x487
173 #define MSR_IA32_VMX_CR4_FIXED0 0x488
174 #define MSR_IA32_VMX_CR4_FIXED1 0x489
175 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48b
176 #define MSR_IA32_VMX_EPT_VPID_CAP 0x48c
177 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48d
178 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48e
179 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48f
180 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
181 #define IA32_FEATURE_CONTROL_MSR 0x3a
182 #define IA32_FEATURE_CONTROL_MSR_LOCK 0x0001
183 #define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX 0x0002
184 #define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX 0x0004
185 #define IA32_FEATURE_CONTROL_MSR_SENTER_PARAM_CTL 0x7f00
186 #define IA32_FEATURE_CONTROL_MSR_ENABLE_SENTER 0x8000
188 /* K7/K8 MSRs. Not complete. See the architecture manual for a more
189 complete list. */
190 #define MSR_K7_EVNTSEL0 0xc0010000
191 #define MSR_K7_PERFCTR0 0xc0010004
192 #define MSR_K7_EVNTSEL1 0xc0010001
193 #define MSR_K7_PERFCTR1 0xc0010005
194 #define MSR_K7_EVNTSEL2 0xc0010002
195 #define MSR_K7_PERFCTR2 0xc0010006
196 #define MSR_K7_EVNTSEL3 0xc0010003
197 #define MSR_K7_PERFCTR3 0xc0010007
198 #define MSR_K8_TOP_MEM1 0xc001001a
199 #define MSR_K7_CLK_CTL 0xc001001b
200 #define MSR_K8_TOP_MEM2 0xc001001d
201 #define MSR_K8_SYSCFG 0xc0010010
203 #define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
204 #define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
205 #define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
207 #define MSR_K7_HWCR 0xc0010015
208 #define MSR_K8_HWCR 0xc0010015
209 #define MSR_K7_FID_VID_CTL 0xc0010041
210 #define MSR_K7_FID_VID_STATUS 0xc0010042
211 #define MSR_K8_PSTATE_LIMIT 0xc0010061
212 #define MSR_K8_PSTATE_CTRL 0xc0010062
213 #define MSR_K8_PSTATE_STATUS 0xc0010063
214 #define MSR_K8_PSTATE0 0xc0010064
215 #define MSR_K8_PSTATE1 0xc0010065
216 #define MSR_K8_PSTATE2 0xc0010066
217 #define MSR_K8_PSTATE3 0xc0010067
218 #define MSR_K8_PSTATE4 0xc0010068
219 #define MSR_K8_PSTATE5 0xc0010069
220 #define MSR_K8_PSTATE6 0xc001006A
221 #define MSR_K8_PSTATE7 0xc001006B
222 #define MSR_K8_ENABLE_C1E 0xc0010055
223 #define MSR_K8_VM_CR 0xc0010114
224 #define MSR_K8_VM_HSAVE_PA 0xc0010117
226 #define MSR_K8_FEATURE_MASK 0xc0011004
227 #define MSR_K8_EXT_FEATURE_MASK 0xc0011005
229 /* MSR_K8_VM_CR bits: */
230 #define _K8_VMCR_SVME_DISABLE 4
231 #define K8_VMCR_SVME_DISABLE (1 << _K8_VMCR_SVME_DISABLE)
233 /* AMD64 MSRs */
234 #define MSR_AMD64_NB_CFG 0xc001001f
235 #define MSR_AMD64_DC_CFG 0xc0011022
236 #define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT 46
238 /* AMD Family10h machine check MSRs */
239 #define MSR_F10_MC4_MISC1 0xc0000408
240 #define MSR_F10_MC4_MISC2 0xc0000409
241 #define MSR_F10_MC4_MISC3 0xc000040A
243 /* Other AMD Fam10h MSRs */
244 #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
245 #define FAM10H_MMIO_CONF_ENABLE (1<<0)
246 #define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
247 #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
248 #define FAM10H_MMIO_CONF_BASE_MASK 0xfffffff
249 #define FAM10H_MMIO_CONF_BASE_SHIFT 20
251 /* AMD Microcode MSRs */
252 #define MSR_AMD_PATCHLEVEL 0x0000008b
253 #define MSR_AMD_PATCHLOADER 0xc0010020
255 /* AMD OS Visible Workaround MSRs */
256 #define MSR_AMD_OSVW_ID_LENGTH 0xc0010140
257 #define MSR_AMD_OSVW_STATUS 0xc0010141
259 /* K6 MSRs */
260 #define MSR_K6_EFER 0xc0000080
261 #define MSR_K6_STAR 0xc0000081
262 #define MSR_K6_WHCR 0xc0000082
263 #define MSR_K6_UWCCR 0xc0000085
264 #define MSR_K6_EPMR 0xc0000086
265 #define MSR_K6_PSOR 0xc0000087
266 #define MSR_K6_PFIR 0xc0000088
268 /* Centaur-Hauls/IDT defined MSRs. */
269 #define MSR_IDT_FCR1 0x00000107
270 #define MSR_IDT_FCR2 0x00000108
271 #define MSR_IDT_FCR3 0x00000109
272 #define MSR_IDT_FCR4 0x0000010a
274 #define MSR_IDT_MCR0 0x00000110
275 #define MSR_IDT_MCR1 0x00000111
276 #define MSR_IDT_MCR2 0x00000112
277 #define MSR_IDT_MCR3 0x00000113
278 #define MSR_IDT_MCR4 0x00000114
279 #define MSR_IDT_MCR5 0x00000115
280 #define MSR_IDT_MCR6 0x00000116
281 #define MSR_IDT_MCR7 0x00000117
282 #define MSR_IDT_MCR_CTRL 0x00000120
284 /* VIA Cyrix defined MSRs*/
285 #define MSR_VIA_FCR 0x00001107
286 #define MSR_VIA_LONGHAUL 0x0000110a
287 #define MSR_VIA_RNG 0x0000110b
288 #define MSR_VIA_BCR2 0x00001147
290 /* Transmeta defined MSRs */
291 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
292 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
293 #define MSR_TMTA_LRTI_READOUT 0x80868018
294 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
296 /* Intel defined MSRs. */
297 #define MSR_IA32_P5_MC_ADDR 0x00000000
298 #define MSR_IA32_P5_MC_TYPE 0x00000001
299 #define MSR_IA32_TSC 0x00000010
300 #define MSR_IA32_PLATFORM_ID 0x00000017
301 #define MSR_IA32_EBL_CR_POWERON 0x0000002a
302 #define MSR_IA32_EBC_FREQUENCY_ID 0x0000002c
304 #define MSR_IA32_APICBASE 0x0000001b
305 #define MSR_IA32_APICBASE_BSP (1<<8)
306 #define MSR_IA32_APICBASE_EXTD (1<<10)
307 #define MSR_IA32_APICBASE_ENABLE (1<<11)
308 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
310 #define MSR_IA32_UCODE_WRITE 0x00000079
311 #define MSR_IA32_UCODE_REV 0x0000008b
313 #define MSR_IA32_PERF_STATUS 0x00000198
314 #define MSR_IA32_PERF_CTL 0x00000199
316 #define MSR_IA32_MPERF 0x000000e7
317 #define MSR_IA32_APERF 0x000000e8
319 #define MSR_IA32_THERM_CONTROL 0x0000019a
320 #define MSR_IA32_THERM_INTERRUPT 0x0000019b
321 #define MSR_IA32_THERM_STATUS 0x0000019c
322 #define MSR_IA32_MISC_ENABLE 0x000001a0
323 #define MSR_IA32_MISC_ENABLE_PERF_AVAIL (1<<7)
324 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11)
325 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
326 #define MSR_IA32_MISC_ENABLE_MONITOR_ENABLE (1<<18)
327 #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1<<22)
328 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23)
330 /* Intel Model 6 */
331 #define MSR_P6_EVNTSEL0 0x00000186
332 #define MSR_P6_EVNTSEL1 0x00000187
334 /* P4/Xeon+ specific */
335 #define MSR_IA32_MCG_EAX 0x00000180
336 #define MSR_IA32_MCG_EBX 0x00000181
337 #define MSR_IA32_MCG_ECX 0x00000182
338 #define MSR_IA32_MCG_EDX 0x00000183
339 #define MSR_IA32_MCG_ESI 0x00000184
340 #define MSR_IA32_MCG_EDI 0x00000185
341 #define MSR_IA32_MCG_EBP 0x00000186
342 #define MSR_IA32_MCG_ESP 0x00000187
343 #define MSR_IA32_MCG_EFLAGS 0x00000188
344 #define MSR_IA32_MCG_EIP 0x00000189
345 #define MSR_IA32_MCG_MISC 0x0000018a
346 #define MSR_IA32_MCG_R8 0x00000190
347 #define MSR_IA32_MCG_R9 0x00000191
348 #define MSR_IA32_MCG_R10 0x00000192
349 #define MSR_IA32_MCG_R11 0x00000193
350 #define MSR_IA32_MCG_R12 0x00000194
351 #define MSR_IA32_MCG_R13 0x00000195
352 #define MSR_IA32_MCG_R14 0x00000196
353 #define MSR_IA32_MCG_R15 0x00000197
355 /* Pentium IV performance counter MSRs */
356 #define MSR_P4_BPU_PERFCTR0 0x00000300
357 #define MSR_P4_BPU_PERFCTR1 0x00000301
358 #define MSR_P4_BPU_PERFCTR2 0x00000302
359 #define MSR_P4_BPU_PERFCTR3 0x00000303
360 #define MSR_P4_MS_PERFCTR0 0x00000304
361 #define MSR_P4_MS_PERFCTR1 0x00000305
362 #define MSR_P4_MS_PERFCTR2 0x00000306
363 #define MSR_P4_MS_PERFCTR3 0x00000307
364 #define MSR_P4_FLAME_PERFCTR0 0x00000308
365 #define MSR_P4_FLAME_PERFCTR1 0x00000309
366 #define MSR_P4_FLAME_PERFCTR2 0x0000030a
367 #define MSR_P4_FLAME_PERFCTR3 0x0000030b
368 #define MSR_P4_IQ_PERFCTR0 0x0000030c
369 #define MSR_P4_IQ_PERFCTR1 0x0000030d
370 #define MSR_P4_IQ_PERFCTR2 0x0000030e
371 #define MSR_P4_IQ_PERFCTR3 0x0000030f
372 #define MSR_P4_IQ_PERFCTR4 0x00000310
373 #define MSR_P4_IQ_PERFCTR5 0x00000311
374 #define MSR_P4_BPU_CCCR0 0x00000360
375 #define MSR_P4_BPU_CCCR1 0x00000361
376 #define MSR_P4_BPU_CCCR2 0x00000362
377 #define MSR_P4_BPU_CCCR3 0x00000363
378 #define MSR_P4_MS_CCCR0 0x00000364
379 #define MSR_P4_MS_CCCR1 0x00000365
380 #define MSR_P4_MS_CCCR2 0x00000366
381 #define MSR_P4_MS_CCCR3 0x00000367
382 #define MSR_P4_FLAME_CCCR0 0x00000368
383 #define MSR_P4_FLAME_CCCR1 0x00000369
384 #define MSR_P4_FLAME_CCCR2 0x0000036a
385 #define MSR_P4_FLAME_CCCR3 0x0000036b
386 #define MSR_P4_IQ_CCCR0 0x0000036c
387 #define MSR_P4_IQ_CCCR1 0x0000036d
388 #define MSR_P4_IQ_CCCR2 0x0000036e
389 #define MSR_P4_IQ_CCCR3 0x0000036f
390 #define MSR_P4_IQ_CCCR4 0x00000370
391 #define MSR_P4_IQ_CCCR5 0x00000371
392 #define MSR_P4_ALF_ESCR0 0x000003ca
393 #define MSR_P4_ALF_ESCR1 0x000003cb
394 #define MSR_P4_BPU_ESCR0 0x000003b2
395 #define MSR_P4_BPU_ESCR1 0x000003b3
396 #define MSR_P4_BSU_ESCR0 0x000003a0
397 #define MSR_P4_BSU_ESCR1 0x000003a1
398 #define MSR_P4_CRU_ESCR0 0x000003b8
399 #define MSR_P4_CRU_ESCR1 0x000003b9
400 #define MSR_P4_CRU_ESCR2 0x000003cc
401 #define MSR_P4_CRU_ESCR3 0x000003cd
402 #define MSR_P4_CRU_ESCR4 0x000003e0
403 #define MSR_P4_CRU_ESCR5 0x000003e1
404 #define MSR_P4_DAC_ESCR0 0x000003a8
405 #define MSR_P4_DAC_ESCR1 0x000003a9
406 #define MSR_P4_FIRM_ESCR0 0x000003a4
407 #define MSR_P4_FIRM_ESCR1 0x000003a5
408 #define MSR_P4_FLAME_ESCR0 0x000003a6
409 #define MSR_P4_FLAME_ESCR1 0x000003a7
410 #define MSR_P4_FSB_ESCR0 0x000003a2
411 #define MSR_P4_FSB_ESCR1 0x000003a3
412 #define MSR_P4_IQ_ESCR0 0x000003ba
413 #define MSR_P4_IQ_ESCR1 0x000003bb
414 #define MSR_P4_IS_ESCR0 0x000003b4
415 #define MSR_P4_IS_ESCR1 0x000003b5
416 #define MSR_P4_ITLB_ESCR0 0x000003b6
417 #define MSR_P4_ITLB_ESCR1 0x000003b7
418 #define MSR_P4_IX_ESCR0 0x000003c8
419 #define MSR_P4_IX_ESCR1 0x000003c9
420 #define MSR_P4_MOB_ESCR0 0x000003aa
421 #define MSR_P4_MOB_ESCR1 0x000003ab
422 #define MSR_P4_MS_ESCR0 0x000003c0
423 #define MSR_P4_MS_ESCR1 0x000003c1
424 #define MSR_P4_PMH_ESCR0 0x000003ac
425 #define MSR_P4_PMH_ESCR1 0x000003ad
426 #define MSR_P4_RAT_ESCR0 0x000003bc
427 #define MSR_P4_RAT_ESCR1 0x000003bd
428 #define MSR_P4_SAAT_ESCR0 0x000003ae
429 #define MSR_P4_SAAT_ESCR1 0x000003af
430 #define MSR_P4_SSU_ESCR0 0x000003be
431 #define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
433 #define MSR_P4_TBPU_ESCR0 0x000003c2
434 #define MSR_P4_TBPU_ESCR1 0x000003c3
435 #define MSR_P4_TC_ESCR0 0x000003c4
436 #define MSR_P4_TC_ESCR1 0x000003c5
437 #define MSR_P4_U2L_ESCR0 0x000003b0
438 #define MSR_P4_U2L_ESCR1 0x000003b1
440 /* Netburst (P4) last-branch recording */
441 #define MSR_P4_LER_FROM_LIP 0x000001d7
442 #define MSR_P4_LER_TO_LIP 0x000001d8
443 #define MSR_P4_LASTBRANCH_TOS 0x000001da
444 #define MSR_P4_LASTBRANCH_0 0x000001db
445 #define NUM_MSR_P4_LASTBRANCH 4
446 #define MSR_P4_LASTBRANCH_0_FROM_LIP 0x00000680
447 #define MSR_P4_LASTBRANCH_0_TO_LIP 0x000006c0
448 #define NUM_MSR_P4_LASTBRANCH_FROM_TO 16
450 /* Pentium M (and Core) last-branch recording */
451 #define MSR_PM_LASTBRANCH_TOS 0x000001c9
452 #define MSR_PM_LASTBRANCH_0 0x00000040
453 #define NUM_MSR_PM_LASTBRANCH 8
455 /* Core 2 last-branch recording */
456 #define MSR_C2_LASTBRANCH_TOS 0x000001c9
457 #define MSR_C2_LASTBRANCH_0_FROM_IP 0x00000040
458 #define MSR_C2_LASTBRANCH_0_TO_IP 0x00000060
459 #define NUM_MSR_C2_LASTBRANCH_FROM_TO 4
461 /* Intel Core-based CPU performance counters */
462 #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
463 #define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
464 #define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
465 #define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
466 #define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
467 #define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
468 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
470 /* Geode defined MSRs */
471 #define MSR_GEODE_BUSCONT_CONF0 0x00001900
473 #endif /* __ASM_MSR_INDEX_H */