debuggers.hg

view xen/arch/x86/apic.c @ 4658:caaf9d543bc5

bitkeeper revision 1.1357 (4267c91c8u7H5ttS9RWRyBY5FrTm3g)

Fix APIC setup on legacy systems.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Thu Apr 21 15:39:08 2005 +0000 (2005-04-21)
parents 67c40314aa6e
children 38a02ee9a9c8 65b28c74cec2
line source
1 /*
2 * based on linux-2.6.10/arch/i386/kernel/apic.c
3 *
4 * Local APIC handling, local APIC timers
5 *
6 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
10 * thanks to Eric Gilmore
11 * and Rolf G. Tews
12 * for testing these extensively.
13 * Maciej W. Rozycki : Various updates and fixes.
14 * Mikael Pettersson : Power Management for UP-APIC.
15 * Pavel Machek and
16 * Mikael Pettersson : PM converted to driver model.
17 */
19 #include <xen/config.h>
20 #include <xen/perfc.h>
21 #include <xen/errno.h>
22 #include <xen/init.h>
23 #include <xen/mm.h>
24 #include <xen/sched.h>
25 #include <xen/irq.h>
26 #include <xen/delay.h>
27 #include <xen/smp.h>
28 #include <xen/softirq.h>
29 #include <asm/mc146818rtc.h>
30 #include <asm/msr.h>
31 #include <asm/atomic.h>
32 #include <asm/mpspec.h>
33 #include <asm/flushtlb.h>
34 #include <asm/hardirq.h>
35 #include <asm/apic.h>
36 #include <asm/io_apic.h>
37 #include <asm/mach_apic.h>
38 #include <asm/io_ports.h>
40 /* Using APIC to generate smp_local_timer_interrupt? */
41 int using_apic_timer = 0;
43 static int enabled_via_apicbase;
45 int get_maxlvt(void)
46 {
47 unsigned int v, ver, maxlvt;
49 v = apic_read(APIC_LVR);
50 ver = GET_APIC_VERSION(v);
51 /* 82489DXs do not report # of LVT entries. */
52 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
53 return maxlvt;
54 }
56 void clear_local_APIC(void)
57 {
58 int maxlvt;
59 unsigned long v;
61 maxlvt = get_maxlvt();
63 /*
64 * Masking an LVT entry on a P6 can trigger a local APIC error
65 * if the vector is zero. Mask LVTERR first to prevent this.
66 */
67 if (maxlvt >= 3) {
68 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
69 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
70 }
71 /*
72 * Careful: we have to set masks only first to deassert
73 * any level-triggered sources.
74 */
75 v = apic_read(APIC_LVTT);
76 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
77 v = apic_read(APIC_LVT0);
78 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
79 v = apic_read(APIC_LVT1);
80 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
81 if (maxlvt >= 4) {
82 v = apic_read(APIC_LVTPC);
83 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
84 }
86 /*
87 * Clean APIC state for other OSs:
88 */
89 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
90 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
91 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
92 if (maxlvt >= 3)
93 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
94 if (maxlvt >= 4)
95 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
97 v = GET_APIC_VERSION(apic_read(APIC_LVR));
98 if (APIC_INTEGRATED(v)) { /* !82489DX */
99 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
100 apic_write(APIC_ESR, 0);
101 apic_read(APIC_ESR);
102 }
103 }
105 void __init connect_bsp_APIC(void)
106 {
107 if (pic_mode) {
108 /*
109 * Do not trust the local APIC being empty at bootup.
110 */
111 clear_local_APIC();
112 /*
113 * PIC mode, enable APIC mode in the IMCR, i.e.
114 * connect BSP's local APIC to INT and NMI lines.
115 */
116 printk("leaving PIC mode, enabling APIC mode.\n");
117 outb(0x70, 0x22);
118 outb(0x01, 0x23);
119 }
120 }
122 void disconnect_bsp_APIC(void)
123 {
124 if (pic_mode) {
125 /*
126 * Put the board back into PIC mode (has an effect
127 * only on certain older boards). Note that APIC
128 * interrupts, including IPIs, won't work beyond
129 * this point! The only exception are INIT IPIs.
130 */
131 printk("disabling APIC mode, entering PIC mode.\n");
132 outb(0x70, 0x22);
133 outb(0x00, 0x23);
134 }
135 }
137 void disable_local_APIC(void)
138 {
139 unsigned long value;
141 clear_local_APIC();
143 /*
144 * Disable APIC (implies clearing of registers
145 * for 82489DX!).
146 */
147 value = apic_read(APIC_SPIV);
148 value &= ~APIC_SPIV_APIC_ENABLED;
149 apic_write_around(APIC_SPIV, value);
151 if (enabled_via_apicbase) {
152 unsigned int l, h;
153 rdmsr(MSR_IA32_APICBASE, l, h);
154 l &= ~MSR_IA32_APICBASE_ENABLE;
155 wrmsr(MSR_IA32_APICBASE, l, h);
156 }
157 }
159 /*
160 * This is to verify that we're looking at a real local APIC.
161 * Check these against your board if the CPUs aren't getting
162 * started for no apparent reason.
163 */
164 int __init verify_local_APIC(void)
165 {
166 unsigned int reg0, reg1;
168 /*
169 * The version register is read-only in a real APIC.
170 */
171 reg0 = apic_read(APIC_LVR);
172 Dprintk("Getting VERSION: %x\n", reg0);
173 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
174 reg1 = apic_read(APIC_LVR);
175 Dprintk("Getting VERSION: %x\n", reg1);
177 /*
178 * The two version reads above should print the same
179 * numbers. If the second one is different, then we
180 * poke at a non-APIC.
181 */
182 if (reg1 != reg0)
183 return 0;
185 /*
186 * Check if the version looks reasonably.
187 */
188 reg1 = GET_APIC_VERSION(reg0);
189 if (reg1 == 0x00 || reg1 == 0xff)
190 return 0;
191 reg1 = get_maxlvt();
192 if (reg1 < 0x02 || reg1 == 0xff)
193 return 0;
195 /*
196 * The ID register is read/write in a real APIC.
197 */
198 reg0 = apic_read(APIC_ID);
199 Dprintk("Getting ID: %x\n", reg0);
201 /*
202 * The next two are just to see if we have sane values.
203 * They're only really relevant if we're in Virtual Wire
204 * compatibility mode, but most boxes are anymore.
205 */
206 reg0 = apic_read(APIC_LVT0);
207 Dprintk("Getting LVT0: %x\n", reg0);
208 reg1 = apic_read(APIC_LVT1);
209 Dprintk("Getting LVT1: %x\n", reg1);
211 return 1;
212 }
214 void __init sync_Arb_IDs(void)
215 {
216 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
217 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
218 if (ver >= 0x14) /* P4 or higher */
219 return;
220 /*
221 * Wait for idle.
222 */
223 apic_wait_icr_idle();
225 Dprintk("Synchronizing Arb IDs.\n");
226 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
227 | APIC_DM_INIT);
228 }
230 extern void __error_in_apic_c (void);
232 void __init init_bsp_APIC(void)
233 {
234 unsigned long value, ver;
236 /*
237 * Don't do the setup now if we have a SMP BIOS as the through-I/O-APIC
238 * virtual wire mode might be active.
239 */
240 if (smp_found_config || !cpu_has_apic)
241 return;
243 value = apic_read(APIC_LVR);
244 ver = GET_APIC_VERSION(value);
246 /*
247 * Do not trust the local APIC being empty at bootup.
248 */
249 clear_local_APIC();
251 /*
252 * Enable APIC.
253 */
254 value = apic_read(APIC_SPIV);
255 value &= ~APIC_VECTOR_MASK;
256 value |= APIC_SPIV_APIC_ENABLED;
258 /* This bit is reserved on P4/Xeon and should be cleared */
259 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
260 value &= ~APIC_SPIV_FOCUS_DISABLED;
261 else
262 value |= APIC_SPIV_FOCUS_DISABLED;
263 value |= SPURIOUS_APIC_VECTOR;
264 apic_write_around(APIC_SPIV, value);
266 /*
267 * Set up the virtual wire mode.
268 */
269 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
270 value = APIC_DM_NMI;
271 if (!APIC_INTEGRATED(ver)) /* 82489DX */
272 value |= APIC_LVT_LEVEL_TRIGGER;
273 apic_write_around(APIC_LVT1, value);
274 }
276 void __init setup_local_APIC (void)
277 {
278 unsigned long oldvalue, value, ver, maxlvt;
280 /* Pound the ESR really hard over the head with a big hammer - mbligh */
281 if (esr_disable) {
282 apic_write(APIC_ESR, 0);
283 apic_write(APIC_ESR, 0);
284 apic_write(APIC_ESR, 0);
285 apic_write(APIC_ESR, 0);
286 }
288 value = apic_read(APIC_LVR);
289 ver = GET_APIC_VERSION(value);
291 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
292 __error_in_apic_c();
294 /*
295 * Double-check whether this APIC is really registered.
296 */
297 if (!apic_id_registered())
298 BUG();
300 /*
301 * Intel recommends to set DFR, LDR and TPR before enabling
302 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
303 * document number 292116). So here it goes...
304 */
305 init_apic_ldr();
307 /*
308 * Set Task Priority to 'accept all'. We never change this
309 * later on.
310 */
311 value = apic_read(APIC_TASKPRI);
312 value &= ~APIC_TPRI_MASK;
313 apic_write_around(APIC_TASKPRI, value);
315 /*
316 * Now that we are all set up, enable the APIC
317 */
318 value = apic_read(APIC_SPIV);
319 value &= ~APIC_VECTOR_MASK;
320 /*
321 * Enable APIC
322 */
323 value |= APIC_SPIV_APIC_ENABLED;
325 /*
326 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
327 * certain networking cards. If high frequency interrupts are
328 * happening on a particular IOAPIC pin, plus the IOAPIC routing
329 * entry is masked/unmasked at a high rate as well then sooner or
330 * later IOAPIC line gets 'stuck', no more interrupts are received
331 * from the device. If focus CPU is disabled then the hang goes
332 * away, oh well :-(
333 *
334 * [ This bug can be reproduced easily with a level-triggered
335 * PCI Ne2000 networking cards and PII/PIII processors, dual
336 * BX chipset. ]
337 */
338 /*
339 * Actually disabling the focus CPU check just makes the hang less
340 * frequent as it makes the interrupt distributon model be more
341 * like LRU than MRU (the short-term load is more even across CPUs).
342 * See also the comment in end_level_ioapic_irq(). --macro
343 */
344 #if 1
345 /* Enable focus processor (bit==0) */
346 value &= ~APIC_SPIV_FOCUS_DISABLED;
347 #else
348 /* Disable focus processor (bit==1) */
349 value |= APIC_SPIV_FOCUS_DISABLED;
350 #endif
351 /*
352 * Set spurious IRQ vector
353 */
354 value |= SPURIOUS_APIC_VECTOR;
355 apic_write_around(APIC_SPIV, value);
357 /*
358 * Set up LVT0, LVT1:
359 *
360 * set up through-local-APIC on the BP's LINT0. This is not
361 * strictly necessery in pure symmetric-IO mode, but sometimes
362 * we delegate interrupts to the 8259A.
363 */
364 /*
365 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
366 */
367 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
368 if (!smp_processor_id() && (pic_mode || !value)) {
369 value = APIC_DM_EXTINT;
370 printk("enabled ExtINT on CPU#%d\n", smp_processor_id());
371 } else {
372 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
373 printk("masked ExtINT on CPU#%d\n", smp_processor_id());
374 }
375 apic_write_around(APIC_LVT0, value);
377 /*
378 * only the BP should see the LINT1 NMI signal, obviously.
379 */
380 if (!smp_processor_id())
381 value = APIC_DM_NMI;
382 else
383 value = APIC_DM_NMI | APIC_LVT_MASKED;
384 if (!APIC_INTEGRATED(ver)) /* 82489DX */
385 value |= APIC_LVT_LEVEL_TRIGGER;
386 apic_write_around(APIC_LVT1, value);
388 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
389 maxlvt = get_maxlvt();
390 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
391 apic_write(APIC_ESR, 0);
392 oldvalue = apic_read(APIC_ESR);
394 value = ERROR_APIC_VECTOR; // enables sending errors
395 apic_write_around(APIC_LVTERR, value);
396 /*
397 * spec says clear errors after enabling vector.
398 */
399 if (maxlvt > 3)
400 apic_write(APIC_ESR, 0);
401 value = apic_read(APIC_ESR);
402 if (value != oldvalue)
403 printk("ESR value before enabling vector: 0x%08lx "
404 "after: 0x%08lx\n", oldvalue, value);
405 } else {
406 if (esr_disable)
407 /*
408 * Something untraceble is creating bad interrupts on
409 * secondary quads ... for the moment, just leave the
410 * ESR disabled - we can't do anything useful with the
411 * errors anyway - mbligh
412 */
413 printk("Leaving ESR disabled.\n");
414 else
415 printk("No ESR for 82489DX.\n");
416 }
418 if (nmi_watchdog == NMI_LOCAL_APIC)
419 setup_apic_nmi_watchdog();
420 }
422 /*
423 * Detect and enable local APICs on non-SMP boards.
424 * Original code written by Keir Fraser.
425 */
427 static int __init detect_init_APIC (void)
428 {
429 u32 h, l, features;
430 extern void get_cpu_vendor(struct cpuinfo_x86*);
432 /* Workaround for us being called before identify_cpu(). */
433 get_cpu_vendor(&boot_cpu_data);
435 switch (boot_cpu_data.x86_vendor) {
436 case X86_VENDOR_AMD:
437 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
438 (boot_cpu_data.x86 == 15))
439 break;
440 goto no_apic;
441 case X86_VENDOR_INTEL:
442 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
443 (boot_cpu_data.x86 == 5 && cpu_has_apic))
444 break;
445 goto no_apic;
446 default:
447 goto no_apic;
448 }
450 if (!cpu_has_apic) {
451 /*
452 * Some BIOSes disable the local APIC in the
453 * APIC_BASE MSR. This can only be done in
454 * software for Intel P6 or later and AMD K7
455 * (Model > 1) or later.
456 */
457 rdmsr(MSR_IA32_APICBASE, l, h);
458 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
459 printk("Local APIC disabled by BIOS -- reenabling.\n");
460 l &= ~MSR_IA32_APICBASE_BASE;
461 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
462 wrmsr(MSR_IA32_APICBASE, l, h);
463 enabled_via_apicbase = 1;
464 }
465 }
467 /* The APIC feature bit should now be enabled in `cpuid' */
468 features = cpuid_edx(1);
469 if (!(features & (1 << X86_FEATURE_APIC))) {
470 printk("Could not enable APIC!\n");
471 return -1;
472 }
474 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
475 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
477 /* The BIOS may have set up the APIC at some other address */
478 rdmsr(MSR_IA32_APICBASE, l, h);
479 if (l & MSR_IA32_APICBASE_ENABLE)
480 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
482 if (nmi_watchdog != NMI_NONE)
483 nmi_watchdog = NMI_LOCAL_APIC;
485 printk("Found and enabled local APIC!\n");
487 return 0;
489 no_apic:
490 printk("No local APIC present or hardware disabled\n");
491 return -1;
492 }
494 void __init init_apic_mappings(void)
495 {
496 unsigned long apic_phys;
498 /*
499 * If no local APIC can be found then set up a fake all
500 * zeroes page to simulate the local APIC and another
501 * one for the IO-APIC.
502 */
503 if (!smp_found_config && detect_init_APIC()) {
504 apic_phys = alloc_xenheap_page();
505 apic_phys = __pa(apic_phys);
506 } else
507 apic_phys = mp_lapic_addr;
509 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
510 Dprintk("mapped APIC to %08lx (%08lx)\n", APIC_BASE, apic_phys);
512 /*
513 * Fetch the APIC ID of the BSP in case we have a
514 * default configuration (or the MP table is broken).
515 */
516 if (boot_cpu_physical_apicid == -1U)
517 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
519 #ifdef CONFIG_X86_IO_APIC
520 {
521 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
522 int i;
524 for (i = 0; i < nr_ioapics; i++) {
525 if (smp_found_config) {
526 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
527 if (!ioapic_phys) {
528 printk(KERN_ERR
529 "WARNING: bogus zero IO-APIC "
530 "address found in MPTABLE, "
531 "disabling IO/APIC support!\n");
532 smp_found_config = 0;
533 skip_ioapic_setup = 1;
534 goto fake_ioapic_page;
535 }
536 } else {
537 fake_ioapic_page:
538 ioapic_phys = alloc_xenheap_page();
539 ioapic_phys = __pa(ioapic_phys);
540 }
541 set_fixmap_nocache(idx, ioapic_phys);
542 Dprintk("mapped IOAPIC to %08lx (%08lx)\n",
543 fix_to_virt(idx), ioapic_phys);
544 idx++;
545 }
546 }
547 #endif
548 }
550 /*****************************************************************************
551 * APIC calibration
552 *
553 * The APIC is programmed in bus cycles.
554 * Timeout values should specified in real time units.
555 * The "cheapest" time source is the cyclecounter.
556 *
557 * Thus, we need a mappings from: bus cycles <- cycle counter <- system time
558 *
559 * The calibration is currently a bit shoddy since it requires the external
560 * timer chip to generate periodic timer interupts.
561 *****************************************************************************/
563 /* used for system time scaling */
564 static unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */
565 static u32 bus_cycle; /* length of one bus cycle in pico-seconds */
566 static u32 bus_scale; /* scaling factor convert ns to bus cycles */
568 /*
569 * The timer chip is already set up at HZ interrupts per second here,
570 * but we do not accept timer interrupts yet. We only allow the BP
571 * to calibrate.
572 */
573 static unsigned int __init get_8254_timer_count(void)
574 {
575 /*extern spinlock_t i8253_lock;*/
576 /*unsigned long flags;*/
578 unsigned int count;
580 /*spin_lock_irqsave(&i8253_lock, flags);*/
582 outb_p(0x00, PIT_MODE);
583 count = inb_p(PIT_CH0);
584 count |= inb_p(PIT_CH0) << 8;
586 /*spin_unlock_irqrestore(&i8253_lock, flags);*/
588 return count;
589 }
591 /* next tick in 8254 can be caught by catching timer wraparound */
592 static void __init wait_8254_wraparound(void)
593 {
594 unsigned int curr_count, prev_count=~0;
595 int delta;
597 curr_count = get_8254_timer_count();
599 do {
600 prev_count = curr_count;
601 curr_count = get_8254_timer_count();
602 delta = curr_count-prev_count;
604 /*
605 * This limit for delta seems arbitrary, but it isn't, it's slightly
606 * above the level of error a buggy Mercury/Neptune chipset timer can
607 * cause.
608 */
609 } while (delta < 300);
610 }
612 /*
613 * Default initialization for 8254 timers. If we use other timers like HPET,
614 * we override this later
615 */
616 void (*wait_timer_tick)(void) = wait_8254_wraparound;
618 /*
619 * This function sets up the local APIC timer, with a timeout of
620 * 'clocks' APIC bus clock. During calibration we actually call
621 * this function with a very large value and read the current time after
622 * a well defined period of time as expired.
623 *
624 * Calibration is only performed once, for CPU0!
625 *
626 * We do reads before writes even if unnecessary, to get around the
627 * P5 APIC double write bug.
628 */
630 #define APIC_DIVISOR 1
632 static void __setup_APIC_LVTT(unsigned int clocks)
633 {
634 unsigned int lvtt_value, tmp_value, ver;
636 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
637 /* NB. Xen uses local APIC timer in one-shot mode. */
638 lvtt_value = /*APIC_LVT_TIMER_PERIODIC |*/ LOCAL_TIMER_VECTOR;
639 if (!APIC_INTEGRATED(ver))
640 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
641 apic_write_around(APIC_LVTT, lvtt_value);
643 tmp_value = apic_read(APIC_TDCR);
644 apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
646 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
647 }
649 /*
650 * this is done for every CPU from setup_APIC_clocks() below.
651 * We setup each local APIC with a zero timeout value for now.
652 * Unlike Linux, we don't have to wait for slices etc.
653 */
654 void setup_APIC_timer(void * data)
655 {
656 unsigned long flags;
657 __save_flags(flags);
658 __sti();
659 __setup_APIC_LVTT(0);
660 __restore_flags(flags);
661 }
663 /*
664 * In this function we calibrate APIC bus clocks to the external timer.
665 *
666 * As a result we have the Bus Speed and CPU speed in Hz.
667 *
668 * We want to do the calibration only once (for CPU0). CPUs connected by the
669 * same APIC bus have the very same bus frequency.
670 *
671 * This bit is a bit shoddy since we use the very same periodic timer interrupt
672 * we try to eliminate to calibrate the APIC.
673 */
675 int __init calibrate_APIC_clock(void)
676 {
677 unsigned long long t1 = 0, t2 = 0;
678 long tt1, tt2;
679 long result;
680 int i;
681 const int LOOPS = HZ/10;
683 printk("Calibrating APIC timer for CPU%d...\n", smp_processor_id());
685 /*
686 * Put whatever arbitrary (but long enough) timeout
687 * value into the APIC clock, we just want to get the
688 * counter running for calibration.
689 */
690 __setup_APIC_LVTT(1000000000);
692 /*
693 * The timer chip counts down to zero. Let's wait
694 * for a wraparound to start exact measurement:
695 * (the current tick might have been already half done)
696 */
697 wait_timer_tick();
699 /*
700 * We wrapped around just now. Let's start:
701 */
702 if (cpu_has_tsc)
703 rdtscll(t1);
704 tt1 = apic_read(APIC_TMCCT);
706 /*
707 * Let's wait LOOPS wraprounds:
708 */
709 for (i = 0; i < LOOPS; i++)
710 wait_timer_tick();
712 tt2 = apic_read(APIC_TMCCT);
713 if (cpu_has_tsc)
714 rdtscll(t2);
716 /*
717 * The APIC bus clock counter is 32 bits only, it
718 * might have overflown, but note that we use signed
719 * longs, thus no extra care needed.
720 * [underflown to be exact, as the timer counts down ;)]
721 */
723 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
725 if (cpu_has_tsc)
726 printk("..... CPU clock speed is %ld.%04ld MHz.\n",
727 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
728 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
730 printk("..... host bus clock speed is %ld.%04ld MHz.\n",
731 result/(1000000/HZ),
732 result%(1000000/HZ));
734 /* set up multipliers for accurate timer code */
735 bus_freq = result*HZ;
736 bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */
737 bus_scale = (1000*262144)/bus_cycle;
739 printk("..... bus_scale = 0x%08X\n", bus_scale);
740 /* reset APIC to zero timeout value */
741 __setup_APIC_LVTT(0);
743 return result;
744 }
746 /*
747 * initialise the APIC timers for all CPUs
748 * we start with the first and find out processor frequency and bus speed
749 */
750 void __init setup_APIC_clocks (void)
751 {
752 printk("Using local APIC timer interrupts.\n");
753 using_apic_timer = 1;
754 __cli();
755 /* calibrate CPU0 for CPU speed and BUS speed */
756 bus_freq = calibrate_APIC_clock();
757 /* Now set up the timer for real. */
758 setup_APIC_timer((void *)bus_freq);
759 __sti();
760 /* and update all other cpus */
761 smp_call_function(setup_APIC_timer, (void *)bus_freq, 1, 1);
762 }
764 #undef APIC_DIVISOR
766 /*
767 * reprogram the APIC timer. Timeoutvalue is in ns from start of boot
768 * returns 1 on success
769 * returns 0 if the timeout value is too small or in the past.
770 */
771 int reprogram_ac_timer(s_time_t timeout)
772 {
773 s_time_t now;
774 s_time_t expire;
775 u64 apic_tmict;
777 /*
778 * We use this value because we don't trust zero (we think it may just
779 * cause an immediate interrupt). At least this is guaranteed to hold it
780 * off for ages (esp. since the clock ticks on bus clock, not cpu clock!).
781 */
782 if ( timeout == 0 )
783 {
784 apic_tmict = 0xffffffff;
785 goto reprogram;
786 }
788 now = NOW();
789 expire = timeout - now; /* value from now */
791 if ( expire <= 0 )
792 {
793 Dprintk("APICT[%02d] Timeout in the past 0x%08X%08X > 0x%08X%08X\n",
794 smp_processor_id(), (u32)(now>>32),
795 (u32)now, (u32)(timeout>>32),(u32)timeout);
796 return 0;
797 }
799 /*
800 * If we don't have local APIC then we just poll the timer list off the
801 * PIT interrupt. Cheesy but good enough to work on eg. VMware :-)
802 */
803 if ( !cpu_has_apic )
804 return 1;
806 /* conversion to bus units */
807 apic_tmict = (((u64)bus_scale) * expire)>>18;
809 if ( apic_tmict >= 0xffffffff )
810 {
811 Dprintk("APICT[%02d] Timeout value too large\n", smp_processor_id());
812 apic_tmict = 0xffffffff;
813 }
815 if ( apic_tmict == 0 )
816 {
817 Dprintk("APICT[%02d] timeout value too small\n", smp_processor_id());
818 return 0;
819 }
821 reprogram:
822 /* Program the timer. */
823 apic_write(APIC_TMICT, (unsigned long)apic_tmict);
825 return 1;
826 }
828 void smp_apic_timer_interrupt(struct xen_regs * regs)
829 {
830 ack_APIC_irq();
831 perfc_incrc(apic_timer);
832 raise_softirq(AC_TIMER_SOFTIRQ);
833 }
835 /*
836 * This interrupt should _never_ happen with our APIC/SMP architecture
837 */
838 asmlinkage void smp_spurious_interrupt(struct xen_regs *regs)
839 {
840 unsigned long v;
842 /*
843 * Check if this really is a spurious interrupt and ACK it
844 * if it is a vectored one. Just in case...
845 * Spurious interrupts should not be ACKed.
846 */
847 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
848 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
849 ack_APIC_irq();
851 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
852 printk("spurious APIC interrupt on CPU#%d, should never happen.\n",
853 smp_processor_id());
854 }
856 /*
857 * This interrupt should never happen with our APIC/SMP architecture
858 */
860 asmlinkage void smp_error_interrupt(struct xen_regs *regs)
861 {
862 unsigned long v, v1;
864 /* First tickle the hardware, only then report what went on. -- REW */
865 v = apic_read(APIC_ESR);
866 apic_write(APIC_ESR, 0);
867 v1 = apic_read(APIC_ESR);
868 ack_APIC_irq();
869 atomic_inc(&irq_err_count);
871 /* Here is what the APIC error bits mean:
872 0: Send CS error
873 1: Receive CS error
874 2: Send accept error
875 3: Receive accept error
876 4: Reserved
877 5: Send illegal vector
878 6: Received illegal vector
879 7: Illegal register address
880 */
881 printk("APIC error on CPU%d: %02lx(%02lx)\n",
882 smp_processor_id(), v, v1);
883 }
885 /*
886 * This initializes the IO-APIC and APIC hardware if this is
887 * a UP kernel.
888 */
889 int __init APIC_init_uniprocessor (void)
890 {
891 if (!smp_found_config && !cpu_has_apic)
892 return -1;
894 /*
895 * Complain if the BIOS pretends there is one.
896 */
897 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
898 printk("BIOS bug, local APIC #%d not detected!...\n",
899 boot_cpu_physical_apicid);
900 return -1;
901 }
903 verify_local_APIC();
905 connect_bsp_APIC();
907 #ifdef CONFIG_SMP
908 cpu_online_map = 1;
909 #endif
910 phys_cpu_present_map = 1;
911 apic_write_around(APIC_ID, boot_cpu_physical_apicid);
913 setup_local_APIC();
915 #ifdef CONFIG_X86_IO_APIC
916 if (smp_found_config)
917 if (!skip_ioapic_setup && nr_ioapics)
918 setup_IO_APIC();
919 #endif
920 setup_APIC_clocks();
922 return 0;
923 }