debuggers.hg

view xen/arch/x86/setup.c @ 4658:caaf9d543bc5

bitkeeper revision 1.1357 (4267c91c8u7H5ttS9RWRyBY5FrTm3g)

Fix APIC setup on legacy systems.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Thu Apr 21 15:39:08 2005 +0000 (2005-04-21)
parents d56c3246d889
children 979aa5d4764e 487de0451d2b ddd290cc8f0d
line source
2 #include <xen/config.h>
3 #include <xen/init.h>
4 #include <xen/lib.h>
5 #include <xen/sched.h>
6 #include <xen/pci.h>
7 #include <xen/serial.h>
8 #include <xen/softirq.h>
9 #include <xen/acpi.h>
10 #include <xen/console.h>
11 #include <xen/serial.h>
12 #include <xen/trace.h>
13 #include <xen/multiboot.h>
14 #include <asm/bitops.h>
15 #include <asm/smp.h>
16 #include <asm/processor.h>
17 #include <asm/mpspec.h>
18 #include <asm/apic.h>
19 #include <asm/desc.h>
20 #include <asm/domain_page.h>
21 #include <asm/shadow.h>
22 #include <asm/e820.h>
24 /*
25 * opt_xenheap_megabytes: Size of Xen heap in megabytes, excluding the
26 * pfn_info table and allocation bitmap.
27 */
28 static unsigned int opt_xenheap_megabytes = XENHEAP_DEFAULT_MB;
29 #if defined(__x86_64__)
30 integer_param("xenheap_megabytes", opt_xenheap_megabytes);
31 #endif
33 /* opt_noht: If true, Hyperthreading is ignored. */
34 int opt_noht = 0;
35 boolean_param("noht", opt_noht);
37 /* opt_noacpi: If true, ACPI tables are not parsed. */
38 static int opt_noacpi = 0;
39 boolean_param("noacpi", opt_noacpi);
41 /* opt_nosmp: If true, secondary processors are ignored. */
42 static int opt_nosmp = 0;
43 boolean_param("nosmp", opt_nosmp);
45 /* opt_ignorebiostables: If true, ACPI and MP tables are ignored. */
46 /* NB. This flag implies 'nosmp' and 'noacpi'. */
47 static int opt_ignorebiostables = 0;
48 boolean_param("ignorebiostables", opt_ignorebiostables);
50 /* opt_watchdog: If true, run a watchdog NMI on each processor. */
51 static int opt_watchdog = 0;
52 boolean_param("watchdog", opt_watchdog);
54 int early_boot = 1;
56 unsigned long xenheap_phys_end;
58 extern void arch_init_memory(void);
59 extern void init_IRQ(void);
60 extern void trap_init(void);
61 extern void time_init(void);
62 extern void ac_timer_init(void);
63 extern void initialize_keytable();
64 extern int do_timer_lists_from_pit;
66 char ignore_irq13; /* set if exception 16 works */
67 struct cpuinfo_x86 boot_cpu_data = { 0, 0, 0, 0, -1 };
69 #if defined(__x86_64__)
70 unsigned long mmu_cr4_features = X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE;
71 #else
72 unsigned long mmu_cr4_features = X86_CR4_PSE | X86_CR4_PGE;
73 #endif
74 EXPORT_SYMBOL(mmu_cr4_features);
76 unsigned long wait_init_idle;
78 struct exec_domain *idle_task[NR_CPUS] = { &idle0_exec_domain };
80 #ifdef CONFIG_ACPI_INTERPRETER
81 int acpi_disabled = 0;
82 #else
83 int acpi_disabled = 1;
84 #endif
85 EXPORT_SYMBOL(acpi_disabled);
87 int phys_proc_id[NR_CPUS];
88 int logical_proc_id[NR_CPUS];
90 /* Standard macro to see if a specific flag is changeable. */
91 static inline int flag_is_changeable_p(unsigned long flag)
92 {
93 unsigned long f1, f2;
95 asm("pushf\n\t"
96 "pushf\n\t"
97 "pop %0\n\t"
98 "mov %0,%1\n\t"
99 "xor %2,%0\n\t"
100 "push %0\n\t"
101 "popf\n\t"
102 "pushf\n\t"
103 "pop %0\n\t"
104 "popf\n\t"
105 : "=&r" (f1), "=&r" (f2)
106 : "ir" (flag));
108 return ((f1^f2) & flag) != 0;
109 }
111 /* Probe for the CPUID instruction */
112 static int __init have_cpuid_p(void)
113 {
114 return flag_is_changeable_p(X86_EFLAGS_ID);
115 }
117 void __init get_cpu_vendor(struct cpuinfo_x86 *c)
118 {
119 char *v = c->x86_vendor_id;
121 if (!strcmp(v, "GenuineIntel"))
122 c->x86_vendor = X86_VENDOR_INTEL;
123 else if (!strcmp(v, "AuthenticAMD"))
124 c->x86_vendor = X86_VENDOR_AMD;
125 else if (!strcmp(v, "CyrixInstead"))
126 c->x86_vendor = X86_VENDOR_CYRIX;
127 else if (!strcmp(v, "UMC UMC UMC "))
128 c->x86_vendor = X86_VENDOR_UMC;
129 else if (!strcmp(v, "CentaurHauls"))
130 c->x86_vendor = X86_VENDOR_CENTAUR;
131 else if (!strcmp(v, "NexGenDriven"))
132 c->x86_vendor = X86_VENDOR_NEXGEN;
133 else if (!strcmp(v, "RiseRiseRise"))
134 c->x86_vendor = X86_VENDOR_RISE;
135 else if (!strcmp(v, "GenuineTMx86") ||
136 !strcmp(v, "TransmetaCPU"))
137 c->x86_vendor = X86_VENDOR_TRANSMETA;
138 else
139 c->x86_vendor = X86_VENDOR_UNKNOWN;
140 }
142 static void __init init_intel(struct cpuinfo_x86 *c)
143 {
144 /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it */
145 if ( c->x86 == 6 && c->x86_model < 3 && c->x86_mask < 3 )
146 clear_bit(X86_FEATURE_SEP, &c->x86_capability);
148 #ifdef CONFIG_SMP
149 if ( test_bit(X86_FEATURE_HT, &c->x86_capability) )
150 {
151 u32 eax, ebx, ecx, edx;
152 int initial_apic_id, siblings, cpu = smp_processor_id();
154 cpuid(1, &eax, &ebx, &ecx, &edx);
155 ht_per_core = siblings = (ebx & 0xff0000) >> 16;
157 if ( opt_noht )
158 clear_bit(X86_FEATURE_HT, &c->x86_capability[0]);
160 if ( siblings <= 1 )
161 {
162 printk(KERN_INFO "CPU#%d: Hyper-Threading is disabled\n", cpu);
163 }
164 else if ( siblings > 2 )
165 {
166 panic("We don't support more than two logical CPUs per package!");
167 }
168 else
169 {
170 initial_apic_id = ebx >> 24 & 0xff;
171 phys_proc_id[cpu] = initial_apic_id >> 1;
172 logical_proc_id[cpu] = initial_apic_id & 1;
173 printk(KERN_INFO "CPU#%d: Physical ID: %d, Logical ID: %d\n",
174 cpu, phys_proc_id[cpu], logical_proc_id[cpu]);
175 }
176 }
177 #endif
179 #ifdef CONFIG_VMX
180 start_vmx();
181 #endif
183 }
185 static void __init init_amd(struct cpuinfo_x86 *c)
186 {
187 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
188 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
189 clear_bit(0*32+31, &c->x86_capability);
191 switch(c->x86)
192 {
193 case 5:
194 panic("AMD K6 is not supported.\n");
195 case 6: /* An Athlon/Duron. We can trust the BIOS probably */
196 break;
197 }
198 }
200 /*
201 * This does the hard work of actually picking apart the CPU stuff...
202 */
203 void __init identify_cpu(struct cpuinfo_x86 *c)
204 {
205 int i, cpu = smp_processor_id();
206 u32 xlvl, tfms, junk;
208 phys_proc_id[cpu] = cpu;
209 logical_proc_id[cpu] = 0;
211 c->x86_vendor = X86_VENDOR_UNKNOWN;
212 c->cpuid_level = -1; /* CPUID not detected */
213 c->x86_model = c->x86_mask = 0; /* So far unknown... */
214 c->x86_vendor_id[0] = '\0'; /* Unset */
215 memset(&c->x86_capability, 0, sizeof c->x86_capability);
217 if ( !have_cpuid_p() )
218 panic("Ancient processors not supported\n");
220 /* Get vendor name */
221 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
222 (unsigned int *)&c->x86_vendor_id[0],
223 (unsigned int *)&c->x86_vendor_id[8],
224 (unsigned int *)&c->x86_vendor_id[4]);
226 get_cpu_vendor(c);
228 if ( c->cpuid_level == 0 )
229 panic("Decrepit CPUID not supported\n");
231 cpuid(0x00000001, &tfms, &junk, &junk,
232 &c->x86_capability[0]);
233 c->x86 = (tfms >> 8) & 15;
234 c->x86_model = (tfms >> 4) & 15;
235 c->x86_mask = tfms & 15;
237 /* AMD-defined flags: level 0x80000001 */
238 xlvl = cpuid_eax(0x80000000);
239 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
240 if ( xlvl >= 0x80000001 )
241 c->x86_capability[1] = cpuid_edx(0x80000001);
242 }
244 /* Transmeta-defined flags: level 0x80860001 */
245 xlvl = cpuid_eax(0x80860000);
246 if ( (xlvl & 0xffff0000) == 0x80860000 ) {
247 if ( xlvl >= 0x80860001 )
248 c->x86_capability[2] = cpuid_edx(0x80860001);
249 }
251 printk("CPU%d: Before vendor init, caps: %08x %08x %08x, vendor = %d\n",
252 smp_processor_id(),
253 c->x86_capability[0],
254 c->x86_capability[1],
255 c->x86_capability[2],
256 c->x86_vendor);
258 switch ( c->x86_vendor ) {
259 case X86_VENDOR_INTEL:
260 init_intel(c);
261 break;
262 case X86_VENDOR_AMD:
263 init_amd(c);
264 break;
265 case X86_VENDOR_UNKNOWN: /* Connectix Virtual PC reports this */
266 break;
267 case X86_VENDOR_CENTAUR:
268 break;
269 default:
270 printk("Unknown CPU identifier (%d): continuing anyway, "
271 "but might fail.\n", c->x86_vendor);
272 }
274 printk("CPU caps: %08x %08x %08x %08x\n",
275 c->x86_capability[0],
276 c->x86_capability[1],
277 c->x86_capability[2],
278 c->x86_capability[3]);
280 /*
281 * On SMP, boot_cpu_data holds the common feature set between
282 * all CPUs; so make sure that we indicate which features are
283 * common between the CPUs. The first time this routine gets
284 * executed, c == &boot_cpu_data.
285 */
286 if ( c != &boot_cpu_data ) {
287 /* AND the already accumulated flags with these */
288 for ( i = 0 ; i < NCAPINTS ; i++ )
289 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
290 }
291 }
294 unsigned long cpu_initialized;
295 void __init cpu_init(void)
296 {
297 int nr = smp_processor_id();
298 struct tss_struct *t = &init_tss[nr];
300 if ( test_and_set_bit(nr, &cpu_initialized) )
301 panic("CPU#%d already initialized!!!\n", nr);
302 printk("Initializing CPU#%d\n", nr);
304 SET_GDT_ENTRIES(current, DEFAULT_GDT_ENTRIES);
305 SET_GDT_ADDRESS(current, DEFAULT_GDT_ADDRESS);
306 __asm__ __volatile__ ( "lgdt %0" : "=m" (*current->arch.gdt) );
308 /* No nested task. */
309 __asm__ __volatile__ ( "pushf ; andw $0xbfff,(%"__OP"sp) ; popf" );
311 /* Ensure FPU gets initialised for each domain. */
312 stts();
314 /* Set up and load the per-CPU TSS and LDT. */
315 t->bitmap = IOBMP_INVALID_OFFSET;
316 #if defined(__i386__)
317 t->ss0 = __HYPERVISOR_DS;
318 t->esp0 = get_stack_bottom();
319 #elif defined(__x86_64__)
320 t->rsp0 = get_stack_bottom();
321 #endif
322 set_tss_desc(nr,t);
323 load_TR(nr);
324 __asm__ __volatile__ ( "lldt %%ax" : : "a" (0) );
326 /* Clear all 6 debug registers. */
327 #define CD(register) __asm__ ( "mov %0,%%db" #register : : "r" (0UL) );
328 CD(0); CD(1); CD(2); CD(3); /* no db4 and db5 */; CD(6); CD(7);
329 #undef CD
331 /* Install correct page table. */
332 write_ptbase(current);
334 init_idle_task();
335 }
337 static void __init do_initcalls(void)
338 {
339 initcall_t *call;
340 for ( call = &__initcall_start; call < &__initcall_end; call++ )
341 (*call)();
342 }
344 unsigned long pci_mem_start = 0x10000000;
346 static void __init start_of_day(void)
347 {
348 unsigned long low_mem_size;
350 #ifdef MEMORY_GUARD
351 /* Unmap the first page of CPU0's stack. */
352 extern unsigned long cpu0_stack[];
353 memguard_guard_stack(cpu0_stack);
354 #endif
356 open_softirq(NEW_TLBFLUSH_CLOCK_PERIOD_SOFTIRQ, new_tlbflush_clock_period);
358 if ( opt_watchdog )
359 nmi_watchdog = NMI_LOCAL_APIC;
361 sort_exception_tables();
363 arch_do_createdomain(current);
365 /* Tell the PCI layer not to allocate too close to the RAM area.. */
366 low_mem_size = ((max_page << PAGE_SHIFT) + 0xfffff) & ~0xfffff;
367 if ( low_mem_size > pci_mem_start ) pci_mem_start = low_mem_size;
369 identify_cpu(&boot_cpu_data); /* get CPU type info */
370 if ( cpu_has_fxsr ) set_in_cr4(X86_CR4_OSFXSR);
371 if ( cpu_has_xmm ) set_in_cr4(X86_CR4_OSXMMEXCPT);
372 #ifdef CONFIG_SMP
373 if ( opt_ignorebiostables )
374 {
375 opt_nosmp = 1; /* No SMP without configuration */
376 opt_noacpi = 1; /* ACPI will just confuse matters also */
377 }
378 else
379 {
380 find_smp_config();
381 smp_alloc_memory(); /* trampoline which other CPUs jump at */
382 }
383 #endif
384 paging_init(); /* not much here now, but sets up fixmap */
385 if ( !opt_noacpi )
386 acpi_boot_init();
387 #ifdef CONFIG_SMP
388 if ( smp_found_config )
389 get_smp_config();
390 #endif
391 init_apic_mappings(); /* make APICs addressable in our pagetables. */
392 scheduler_init();
393 init_IRQ(); /* installs simple interrupt wrappers. Starts HZ clock. */
394 trap_init();
395 time_init(); /* installs software handler for HZ clock. */
397 arch_init_memory();
399 #ifndef CONFIG_SMP
400 APIC_init_uniprocessor();
401 #else
402 if ( opt_nosmp )
403 APIC_init_uniprocessor();
404 else
405 smp_boot_cpus();
406 /*
407 * Does loads of stuff, including kicking the local
408 * APIC, and the IO APIC after other CPUs are booted.
409 * Each IRQ is preferably handled by IO-APIC, but
410 * fall thru to 8259A if we have to (but slower).
411 */
412 #endif
414 __sti();
416 initialize_keytable(); /* call back handling for key codes */
418 serial_init_stage2();
420 if ( !cpu_has_apic )
421 {
422 do_timer_lists_from_pit = 1;
423 if ( smp_num_cpus != 1 )
424 panic("We need local APICs on SMP machines!");
425 }
427 ac_timer_init(); /* init accurate timers */
428 init_xen_time(); /* initialise the time */
429 schedulers_start(); /* start scheduler for each CPU */
431 check_nmi_watchdog();
433 #ifdef CONFIG_PCI
434 pci_init();
435 #endif
436 do_initcalls();
438 #ifdef CONFIG_SMP
439 wait_init_idle = cpu_online_map;
440 clear_bit(smp_processor_id(), &wait_init_idle);
441 smp_threads_ready = 1;
442 smp_commence(); /* Tell other CPUs that state of the world is stable. */
443 while ( wait_init_idle != 0 )
444 cpu_relax();
445 #endif
447 watchdog_on = 1;
448 #ifdef __x86_64__ /* x86_32 uses low mappings when building DOM0. */
449 zap_low_mappings();
450 #endif
451 }
453 void __init __start_xen(multiboot_info_t *mbi)
454 {
455 char *cmdline;
456 module_t *mod = (module_t *)__va(mbi->mods_addr);
457 void *heap_start;
458 unsigned long firsthole_start, nr_pages;
459 unsigned long initial_images_start, initial_images_end;
460 struct e820entry e820_raw[E820MAX];
461 int i, e820_raw_nr = 0, bytes = 0;
463 /* Parse the command-line options. */
464 if ( (mbi->flags & MBI_CMDLINE) && (mbi->cmdline != 0) )
465 cmdline_parse(__va(mbi->cmdline));
467 /* Must do this early -- e.g., spinlocks rely on get_current(). */
468 set_current(&idle0_exec_domain);
470 /* We initialise the serial devices very early so we can get debugging. */
471 serial_init_stage1();
473 init_console();
475 /* Check that we have at least one Multiboot module. */
476 if ( !(mbi->flags & MBI_MODULES) || (mbi->mods_count == 0) )
477 {
478 printk("FATAL ERROR: Require at least one Multiboot module.\n");
479 for ( ; ; ) ;
480 }
482 xenheap_phys_end = opt_xenheap_megabytes << 20;
484 if ( mbi->flags & MBI_MEMMAP )
485 {
486 while ( bytes < mbi->mmap_length )
487 {
488 memory_map_t *map = __va(mbi->mmap_addr + bytes);
489 e820_raw[e820_raw_nr].addr =
490 ((u64)map->base_addr_high << 32) | (u64)map->base_addr_low;
491 e820_raw[e820_raw_nr].size =
492 ((u64)map->length_high << 32) | (u64)map->length_low;
493 e820_raw[e820_raw_nr].type =
494 (map->type > E820_SHARED_PAGE) ? E820_RESERVED : map->type;
495 e820_raw_nr++;
496 bytes += map->size + 4;
497 }
498 }
499 else if ( mbi->flags & MBI_MEMLIMITS )
500 {
501 e820_raw[0].addr = 0;
502 e820_raw[0].size = mbi->mem_lower << 10;
503 e820_raw[0].type = E820_RAM;
504 e820_raw[1].addr = 0x100000;
505 e820_raw[1].size = mbi->mem_upper << 10;
506 e820_raw[1].type = E820_RAM;
507 e820_raw_nr = 2;
508 }
509 else
510 {
511 printk("FATAL ERROR: Bootloader provided no memory information.\n");
512 for ( ; ; ) ;
513 }
515 max_page = init_e820(e820_raw, e820_raw_nr);
517 /* Find the first high-memory RAM hole. */
518 for ( i = 0; i < e820.nr_map; i++ )
519 if ( (e820.map[i].type == E820_RAM) &&
520 (e820.map[i].addr >= 0x100000) )
521 break;
522 firsthole_start = e820.map[i].addr + e820.map[i].size;
524 /* Relocate the Multiboot modules. */
525 initial_images_start = xenheap_phys_end;
526 initial_images_end = initial_images_start +
527 (mod[mbi->mods_count-1].mod_end - mod[0].mod_start);
528 if ( initial_images_end > firsthole_start )
529 {
530 printk("Not enough memory to stash the DOM0 kernel image.\n");
531 for ( ; ; ) ;
532 }
533 #if defined(__i386__)
534 memmove((void *)initial_images_start, /* use low mapping */
535 (void *)mod[0].mod_start, /* use low mapping */
536 mod[mbi->mods_count-1].mod_end - mod[0].mod_start);
537 #elif defined(__x86_64__)
538 memmove(__va(initial_images_start),
539 __va(mod[0].mod_start),
540 mod[mbi->mods_count-1].mod_end - mod[0].mod_start);
541 #endif
543 /* Initialise boot-time allocator with all RAM situated after modules. */
544 heap_start = memguard_init(&_end);
545 heap_start = __va(init_boot_allocator(__pa(heap_start)));
546 nr_pages = 0;
547 for ( i = 0; i < e820.nr_map; i++ )
548 {
549 if ( e820.map[i].type != E820_RAM )
550 continue;
551 nr_pages += e820.map[i].size >> PAGE_SHIFT;
552 if ( (e820.map[i].addr + e820.map[i].size) >= initial_images_end )
553 init_boot_pages((e820.map[i].addr < initial_images_end) ?
554 initial_images_end : e820.map[i].addr,
555 e820.map[i].addr + e820.map[i].size);
556 }
558 printk("System RAM: %luMB (%lukB)\n",
559 nr_pages >> (20 - PAGE_SHIFT),
560 nr_pages << (PAGE_SHIFT - 10));
562 init_frametable();
564 end_boot_allocator();
566 init_xenheap_pages(__pa(heap_start), xenheap_phys_end);
567 printk("Xen heap: %luMB (%lukB)\n",
568 (xenheap_phys_end-__pa(heap_start)) >> 20,
569 (xenheap_phys_end-__pa(heap_start)) >> 10);
571 early_boot = 0;
573 start_of_day();
575 grant_table_init();
577 shadow_mode_init();
579 /* Create initial domain 0. */
580 dom0 = do_createdomain(0, 0);
581 if ( dom0 == NULL )
582 panic("Error creating domain 0\n");
584 set_bit(DF_PRIVILEGED, &dom0->d_flags);
586 /* Grab the DOM0 command line. Skip past the image name. */
587 cmdline = (char *)(mod[0].string ? __va(mod[0].string) : NULL);
588 if ( cmdline != NULL )
589 {
590 while ( *cmdline == ' ' ) cmdline++;
591 if ( (cmdline = strchr(cmdline, ' ')) != NULL )
592 while ( *cmdline == ' ' ) cmdline++;
593 }
595 /*
596 * We're going to setup domain0 using the module(s) that we stashed safely
597 * above our heap. The second module, if present, is an initrd ramdisk.
598 */
599 if ( construct_dom0(dom0,
600 initial_images_start,
601 mod[0].mod_end-mod[0].mod_start,
602 (mbi->mods_count == 1) ? 0 :
603 initial_images_start +
604 (mod[1].mod_start-mod[0].mod_start),
605 (mbi->mods_count == 1) ? 0 :
606 mod[mbi->mods_count-1].mod_end - mod[1].mod_start,
607 cmdline) != 0)
608 panic("Could not set up DOM0 guest OS\n");
610 /* Scrub RAM that is still free and so may go to an unprivileged domain. */
611 scrub_heap_pages();
613 init_trace_bufs();
615 /* Give up the VGA console if DOM0 is configured to grab it. */
616 console_endboot(cmdline && strstr(cmdline, "tty0"));
618 /* Hide UART from DOM0 if we're using it */
619 serial_endboot();
621 domain_unpause_by_systemcontroller(current->domain);
622 domain_unpause_by_systemcontroller(dom0);
623 startup_cpu_idle_loop();
624 }
626 /*
627 * Local variables:
628 * mode: C
629 * c-set-style: "BSD"
630 * c-basic-offset: 4
631 * tab-width: 4
632 * indent-tabs-mode: nil
633 * End:
634 */