debuggers.hg

view xen/include/asm-x86/hvm/vmx/intel-iommu.h @ 16380:cb6675149af8

x86, vt-d: Clean up utils code.
Signed-off-by: Weidong Han <weidong.han@intel.com>
author Keir Fraser <keir@xensource.com>
date Thu Nov 08 13:14:03 2007 +0000 (2007-11-08)
parents 5a213170b06e
children f173cd885ffb
line source
1 /*
2 * Copyright (c) 2006, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
16 *
17 * Copyright (C) Ashok Raj <ashok.raj@intel.com>
18 */
20 #ifndef _INTEL_IOMMU_H_
21 #define _INTEL_IOMMU_H_
23 #include <xen/types.h>
25 /*
26 * Intel IOMMU register specification per version 1.0 public spec.
27 */
29 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
30 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
31 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
32 #define DMAR_GCMD_REG 0x18 /* Global command register */
33 #define DMAR_GSTS_REG 0x1c /* Global status register */
34 #define DMAR_RTADDR_REG 0x20 /* Root entry table */
35 #define DMAR_CCMD_REG 0x28 /* Context command reg */
36 #define DMAR_FSTS_REG 0x34 /* Fault Status register */
37 #define DMAR_FECTL_REG 0x38 /* Fault control register */
38 #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
39 #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
40 #define DMAR_FEUADDR_REG 0x44 /* Upper address register */
41 #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
42 #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
43 #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
44 #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
45 #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
46 #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
47 #define DMAR_IQH_REG 0x80 /* invalidation queue head */
48 #define DMAR_IQT_REG 0x88 /* invalidation queue tail */
49 #define DMAR_IQA_REG 0x90 /* invalidation queue addr */
50 #define DMAR_IRTA_REG 0xB8 /* intr remap */
52 #define OFFSET_STRIDE (9)
53 #define dmar_readl(dmar, reg) readl(dmar + reg)
54 #define dmar_writel(dmar, reg, val) writel(val, dmar + reg)
55 #define dmar_readq(dmar, reg) ({ \
56 u32 lo, hi; \
57 lo = dmar_readl(dmar, reg); \
58 hi = dmar_readl(dmar, reg + 4); \
59 (((u64) hi) << 32) + lo; })
60 #define dmar_writeq(dmar, reg, val) do {\
61 dmar_writel(dmar, reg, (u32)val); \
62 dmar_writel(dmar, reg + 4, (u32)((u64) val >> 32)); \
63 } while (0)
65 #define VER_MAJOR(v) (((v) & 0xf0) >> 4)
66 #define VER_MINOR(v) ((v) & 0x0f)
68 /*
69 * Decoding Capability Register
70 */
71 #define cap_read_drain(c) (((c) >> 55) & 1)
72 #define cap_write_drain(c) (((c) >> 54) & 1)
73 #define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
74 #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
75 #define cap_pgsel_inv(c) (((c) >> 39) & 1)
77 #define cap_super_page_val(c) (((c) >> 34) & 0xf)
78 #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
79 * OFFSET_STRIDE) + 21)
81 #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
83 #define cap_isoch(c) (((c) >> 23) & 1)
84 #define cap_qos(c) (((c) >> 22) & 1)
85 #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
86 #define cap_sagaw(c) (((c) >> 8) & 0x1f)
87 #define cap_caching_mode(c) (((c) >> 7) & 1)
88 #define cap_phmr(c) (((c) >> 6) & 1)
89 #define cap_plmr(c) (((c) >> 5) & 1)
90 #define cap_rwbf(c) (((c) >> 4) & 1)
91 #define cap_afl(c) (((c) >> 3) & 1)
92 #define cap_ndoms(c) (2 ^ (4 + 2 * ((c) & 0x7)))
93 /*
94 * Extended Capability Register
95 */
97 #define ecap_niotlb_iunits(e) ((((e) >> 24) & 0xff) + 1)
98 #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
99 #define ecap_coherent(e) ((e >> 0) & 0x1)
100 #define ecap_queued_inval(e) ((e >> 1) & 0x1)
101 #define ecap_dev_iotlb(e) ((e >> 2) & 0x1)
102 #define ecap_intr_remap(e) ((e >> 3) & 0x1)
103 #define ecap_ext_intr(e) ((e >> 4) & 0x1)
104 #define ecap_cache_hints(e) ((e >> 5) & 0x1)
105 #define ecap_pass_thru(e) ((e >> 6) & 0x1)
107 #define PAGE_SHIFT_4K (12)
108 #define PAGE_SIZE_4K (1UL << PAGE_SHIFT_4K)
109 #define PAGE_MASK_4K (((u64)-1) << PAGE_SHIFT_4K)
110 #define PAGE_ALIGN_4K(addr) (((addr) + PAGE_SIZE_4K - 1) & PAGE_MASK_4K)
112 /* IOTLB_REG */
113 #define DMA_TLB_FLUSH_GRANU_OFFSET 60
114 #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
115 #define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
116 #define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
117 #define DMA_TLB_IIRG(x) (((x) >> 60) & 7)
118 #define DMA_TLB_IAIG(val) (((val) >> 57) & 7)
119 #define DMA_TLB_DID(x) (((u64)(x & 0xffff)) << 32)
121 #define DMA_TLB_READ_DRAIN (((u64)1) << 49)
122 #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
123 #define DMA_TLB_IVT (((u64)1) << 63)
125 #define DMA_TLB_IVA_ADDR(x) ((((u64)x) >> 12) << 12)
126 #define DMA_TLB_IVA_HINT(x) ((((u64)x) & 1) << 6)
128 /* GCMD_REG */
129 #define DMA_GCMD_TE (((u64)1) << 31)
130 #define DMA_GCMD_SRTP (((u64)1) << 30)
131 #define DMA_GCMD_SFL (((u64)1) << 29)
132 #define DMA_GCMD_EAFL (((u64)1) << 28)
133 #define DMA_GCMD_WBF (((u64)1) << 27)
134 #define DMA_GCMD_QIE (((u64)1) << 26)
135 #define DMA_GCMD_IRE (((u64)1) << 25)
136 #define DMA_GCMD_SIRTP (((u64)1) << 24)
138 /* GSTS_REG */
139 #define DMA_GSTS_TES (((u64)1) << 31)
140 #define DMA_GSTS_RTPS (((u64)1) << 30)
141 #define DMA_GSTS_FLS (((u64)1) << 29)
142 #define DMA_GSTS_AFLS (((u64)1) << 28)
143 #define DMA_GSTS_WBFS (((u64)1) << 27)
144 #define DMA_GSTS_IRTPS (((u64)1) << 24)
145 #define DMA_GSTS_QIES (((u64)1) <<26)
146 #define DMA_GSTS_IRES (((u64)1) <<25)
148 /* PMEN_REG */
149 #define DMA_PMEN_EPM (((u32)1) << 31)
150 #define DMA_PMEN_PRS (((u32)1) << 0)
152 /* CCMD_REG */
153 #define DMA_CCMD_INVL_GRANU_OFFSET 61
154 #define DMA_CCMD_ICC (((u64)1) << 63)
155 #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
156 #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
157 #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
158 #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
159 #define DMA_CCMD_CIRG(x) ((((u64)3) << 61) & x)
160 #define DMA_CCMD_MASK_NOBIT 0
161 #define DMA_CCMD_MASK_1BIT 1
162 #define DMA_CCMD_MASK_2BIT 2
163 #define DMA_CCMD_MASK_3BIT 3
164 #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
165 #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
167 #define DMA_CCMD_CAIG_MASK(x) (((u64)x) & ((u64) 0x3 << 59))
169 /* FECTL_REG */
170 #define DMA_FECTL_IM (((u64)1) << 31)
172 /* FSTS_REG */
173 #define DMA_FSTS_PPF ((u64)2)
174 #define DMA_FSTS_PFO ((u64)1)
175 #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
177 /* FRCD_REG, 32 bits access */
178 #define DMA_FRCD_F (((u64)1) << 31)
179 #define dma_frcd_type(d) ((d >> 30) & 1)
180 #define dma_frcd_fault_reason(c) (c & 0xff)
181 #define dma_frcd_source_id(c) (c & 0xffff)
182 #define dma_frcd_page_addr(d) (d & (((u64)-1) << 12)) /* low 64 bit */
184 /*
185 * 0: Present
186 * 1-11: Reserved
187 * 12-63: Context Ptr (12 - (haw-1))
188 * 64-127: Reserved
189 */
190 struct root_entry {
191 u64 val;
192 u64 rsvd1;
193 };
194 #define root_present(root) ((root).val & 1)
195 #define set_root_present(root) do {(root).val |= 1;} while(0)
196 #define get_context_addr(root) ((root).val & PAGE_MASK_4K)
197 #define set_root_value(root, value) \
198 do {(root).val |= ((value) & PAGE_MASK_4K);} while(0)
200 struct context_entry {
201 u64 lo;
202 u64 hi;
203 };
204 #define ROOT_ENTRY_NR (PAGE_SIZE_4K/sizeof(struct root_entry))
205 #define context_present(c) ((c).lo & 1)
206 #define context_fault_disable(c) (((c).lo >> 1) & 1)
207 #define context_translation_type(c) (((c).lo >> 2) & 3)
208 #define context_address_root(c) ((c).lo & PAGE_MASK_4K)
209 #define context_address_width(c) ((c).hi & 7)
210 #define context_domain_id(c) (((c).hi >> 8) & ((1 << 16) - 1))
212 #define context_set_present(c) do {(c).lo |= 1;} while(0)
213 #define context_clear_present(c) do {(c).lo &= ~1;} while(0)
214 #define context_set_fault_enable(c) \
215 do {(c).lo &= (((u64)-1) << 2) | 1;} while(0)
217 #define context_set_translation_type(c, val) do { \
218 (c).lo &= (((u64)-1) << 4) | 3; \
219 (c).lo |= (val & 3) << 2; \
220 } while(0)
221 #define CONTEXT_TT_MULTI_LEVEL 0
222 #define CONTEXT_TT_DEV_IOTLB 1
223 #define CONTEXT_TT_PASS_THRU 2
225 #define context_set_address_root(c, val) \
226 do {(c).lo &= 0xfff; (c).lo |= (val) & PAGE_MASK_4K ;} while(0)
227 #define context_set_address_width(c, val) \
228 do {(c).hi &= 0xfffffff8; (c).hi |= (val) & 7;} while(0)
229 #define context_set_domain_id(c, val) \
230 do {(c).hi &= 0xff; (c).hi |= ((val + 1) & ((1 << 16) - 1)) << 8;} while(0)
231 #define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while(0)
233 /* page table handling */
234 #define LEVEL_STRIDE (9)
235 #define LEVEL_MASK ((1 << LEVEL_STRIDE) - 1)
236 #define agaw_to_level(val) ((val) + 2)
237 #define agaw_to_width(val) (30 + val * LEVEL_STRIDE)
238 #define width_to_agaw(w) ((w - 30)/LEVEL_STRIDE)
239 #define level_to_offset_bits(l) (12 + (l - 1) * LEVEL_STRIDE)
240 #define address_level_offset(addr, level) \
241 ((addr >> level_to_offset_bits(level)) & LEVEL_MASK)
242 #define level_mask(l) (((u64)(-1)) << level_to_offset_bits(l))
243 #define level_size(l) (1 << level_to_offset_bits(l))
244 #define align_to_level(addr, l) ((addr + level_size(l) - 1) & level_mask(l))
246 /*
247 * 0: readable
248 * 1: writable
249 * 2-6: reserved
250 * 7: super page
251 * 8-11: available
252 * 12-63: Host physcial address
253 */
254 struct dma_pte {
255 u64 val;
256 };
257 #define dma_clear_pte(p) do {(p).val = 0;} while(0)
258 #define dma_set_pte_readable(p) do {(p).val |= 1;} while(0)
259 #define dma_set_pte_writable(p) do {(p).val |= 2;} while(0)
260 #define dma_set_pte_superpage(p) do {(p).val |= 8;} while(0)
261 #define dma_set_pte_prot(p, prot) do { (p).val = (((p).val >> 2) << 2) | ((prot) & 3);} while (0)
262 #define dma_pte_addr(p) ((p).val & PAGE_MASK_4K)
263 #define dma_set_pte_addr(p, addr) do {(p).val |= ((addr) >> PAGE_SHIFT_4K) << PAGE_SHIFT_4K;} while(0)
264 #define DMA_PTE_READ (1)
265 #define DMA_PTE_WRITE (2)
266 #define dma_pte_present(p) (((p).val & 3) != 0)
268 /* interrupt remap entry */
269 struct iremap_entry {
270 struct {
271 u64 present : 1,
272 fpd : 1,
273 dm : 1,
274 rh : 1,
275 tm : 1,
276 dlm : 3,
277 avail : 4,
278 res_1 : 4,
279 vector : 8,
280 res_2 : 8,
281 dst : 32;
282 }lo;
283 struct {
284 u64 sid : 16,
285 sq : 2,
286 svt : 2,
287 res_1 : 44;
288 }hi;
289 };
290 #define IREMAP_ENTRY_NR (PAGE_SIZE_4K/sizeof(struct iremap_entry))
291 #define iremap_present(v) ((v).lo & 1)
292 #define iremap_fault_disable(v) (((v).lo >> 1) & 1)
294 #define iremap_set_present(v) do {(v).lo |= 1;} while(0)
295 #define iremap_clear_present(v) do {(v).lo &= ~1;} while(0)
297 /* queue invalidation entry */
298 struct qinval_entry {
299 union {
300 struct {
301 struct {
302 u64 type : 4,
303 granu : 2,
304 res_1 : 10,
305 did : 16,
306 sid : 16,
307 fm : 2,
308 res_2 : 14;
309 }lo;
310 struct {
311 u64 res;
312 }hi;
313 }cc_inv_dsc;
314 struct {
315 struct {
316 u64 type : 4,
317 granu : 2,
318 dw : 1,
319 dr : 1,
320 res_1 : 8,
321 did : 16,
322 res_2 : 32;
323 }lo;
324 struct {
325 u64 am : 6,
326 ih : 1,
327 res_1 : 5,
328 addr : 52;
329 }hi;
330 }iotlb_inv_dsc;
331 struct {
332 struct {
333 u64 type : 4,
334 res_1 : 12,
335 max_invs_pend: 5,
336 res_2 : 11,
337 sid : 16,
338 res_3 : 16;
339 }lo;
340 struct {
341 u64 size : 1,
342 res_1 : 11,
343 addr : 52;
344 }hi;
345 }dev_iotlb_inv_dsc;
346 struct {
347 struct {
348 u64 type : 4,
349 granu : 1,
350 res_1 : 22,
351 im : 5,
352 iidx : 16,
353 res_2 : 16;
354 }lo;
355 struct {
356 u64 res;
357 }hi;
358 }iec_inv_dsc;
359 struct {
360 struct {
361 u64 type : 4,
362 iflag : 1,
363 sw : 1,
364 fn : 1,
365 res_1 : 25,
366 sdata : 32;
367 }lo;
368 struct {
369 u64 res_1 : 2,
370 saddr : 62;
371 }hi;
372 }inv_wait_dsc;
373 }q;
374 };
376 struct poll_info {
377 u64 saddr;
378 u32 udata;
379 };
381 #define QINVAL_ENTRY_NR (PAGE_SIZE_4K/sizeof(struct qinval_entry))
382 #define qinval_present(v) ((v).lo & 1)
383 #define qinval_fault_disable(v) (((v).lo >> 1) & 1)
385 #define qinval_set_present(v) do {(v).lo |= 1;} while(0)
386 #define qinval_clear_present(v) do {(v).lo &= ~1;} while(0)
388 #define RESERVED_VAL 0
390 #define TYPE_INVAL_CONTEXT 1
391 #define TYPE_INVAL_IOTLB 2
392 #define TYPE_INVAL_DEVICE_IOTLB 3
393 #define TYPE_INVAL_IEC 4
394 #define TYPE_INVAL_WAIT 5
396 #define NOTIFY_TYPE_POLL 1
397 #define NOTIFY_TYPE_INTR 1
398 #define INTERRUTP_FLAG 1
399 #define STATUS_WRITE 1
400 #define FENCE_FLAG 1
402 #define IEC_GLOBAL_INVL 0
403 #define IEC_INDEX_INVL 1
405 #define VTD_PAGE_TABLE_LEVEL_3 3
406 #define VTD_PAGE_TABLE_LEVEL_4 4
408 typedef paddr_t dma_addr_t;
410 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
411 #define MAX_IOMMUS 32
412 #define MAX_IOMMU_REGS 0xc0
414 extern struct list_head acpi_drhd_units;
415 extern struct list_head acpi_rmrr_units;
416 extern struct list_head acpi_ioapic_units;
418 #endif