debuggers.hg

view tools/ioemu/patches/acpi-timer-support @ 10984:e1a2a8029e9f

[qemu patches] Update patches for changeset 10945:baa6d08e62a0.

Signed-off-by: Christian Limpach <Christian.Limpach@xensource.com>
author chris@kneesaa.uk.xensource.com
date Fri Aug 04 11:36:07 2006 +0100 (2006-08-04)
parents 23166260f6ce
children ec8dd0528fc6
line source
1 Index: ioemu/hw/piix4acpi.c
2 ===================================================================
3 --- ioemu.orig/hw/piix4acpi.c 2006-08-04 10:57:28.922994985 +0100
4 +++ ioemu/hw/piix4acpi.c 2006-08-04 11:35:15.177574467 +0100
5 @@ -24,31 +24,30 @@
6 */
8 #include "vl.h"
9 -#define FREQUENCE_PMTIMER 3753425
10 +#define FREQUENCE_PMTIMER 3579545
11 /* acpi register bit define here */
13 -/* PM1_STS */
14 -#define TMROF_STS (1 << 0)
15 -#define BM_STS (1 << 4)
16 -#define GBL_STS (1 << 5)
17 -#define PWRBTN_STS (1 << 8)
18 -#define RTC_STS (1 << 10)
19 +/* PM1_STS */
20 +#define TMROF_STS (1 << 0)
21 +#define BM_STS (1 << 4)
22 +#define GBL_STS (1 << 5)
23 +#define PWRBTN_STS (1 << 8)
24 +#define RTC_STS (1 << 10)
25 #define PRBTNOR_STS (1 << 11)
26 -#define WAK_STS (1 << 15)
27 -/* PM1_EN */
28 +#define WAK_STS (1 << 15)
29 +/* PM1_EN */
30 #define TMROF_EN (1 << 0)
31 #define GBL_EN (1 << 5)
32 #define PWRBTN_EN (1 << 8)
33 -#define RTC_EN (1 << 10)
34 -/* PM1_CNT */
35 +#define RTC_EN (1 << 10)
36 +/* PM1_CNT */
37 #define SCI_EN (1 << 0)
38 #define GBL_RLS (1 << 2)
39 -#define SLP_EN (1 << 13)
40 +#define SLP_EN (1 << 13)
42 typedef struct AcpiDeviceState AcpiDeviceState;
43 AcpiDeviceState *acpi_device_table;
45 -/* Bits of PM1a register define here */
46 typedef struct PM1Event_BLK {
47 uint16_t pm1_status; /* pm1a_EVT_BLK */
48 uint16_t pm1_enable; /* pm1a_EVT_BLK+2 */
49 @@ -61,17 +60,11 @@
50 uint16_t pm1_enable; /* pm1a_EVT_BLK+2 */
51 uint16_t pm1_control; /* pm1a_ECNT_BLK */
52 uint32_t pm1_timer; /* pmtmr_BLK */
53 + uint64_t old_vmck_ticks; /* using vm_clock counter */
54 } PCIAcpiState;
56 static PCIAcpiState *acpi_state;
58 -static inline void acpi_set_irq(PCIAcpiState *s)
59 -{
60 -/* no real SCI event need for now, so comment the following line out */
61 -/* pic_set_irq(s->irq, 1); */
62 - printf("acpi_set_irq: s->irq %x \n",s->irq);
63 -}
64 -
65 static void acpi_reset(PCIAcpiState *s)
66 {
67 uint8_t *pci_conf;
68 @@ -84,6 +77,7 @@
69 s->pm1_enable = 0x00; /* TMROF_EN should cleared */
70 s->pm1_control = SCI_EN; /* SCI_EN */
71 s->pm1_timer = 0;
72 + s->old_vmck_ticks = qemu_get_clock(vm_clock);
73 }
75 /*byte access */
76 @@ -95,8 +89,8 @@
77 s->pm1_status = s->pm1_status&!TMROF_STS;
79 if ((val&GBL_STS)==GBL_STS)
80 - s->pm1_status = s->pm1_status&!GBL_STS;
81 -
82 + s->pm1_status = s->pm1_status&!GBL_STS;
83 +
84 /* printf("acpiPm1Status_writeb \n addr %x val:%x pm1_status:%x \n", addr, val,s->pm1_status); */
85 }
87 @@ -115,7 +109,7 @@
88 {
89 PCIAcpiState *s = opaque;
91 - s->pm1_status = (val<<8)||(s->pm1_status);
92 + s->pm1_status = (val<<8)||(s->pm1_status);
93 /* printf("acpiPm1StatusP1_writeb \n addr %x val:%x\n", addr, val); */
94 }
96 @@ -220,7 +214,7 @@
97 s->pm1_status = s->pm1_status&!TMROF_STS;
99 if ((val&GBL_STS)==GBL_STS)
100 - s->pm1_status = s->pm1_status&!GBL_STS;
101 + s->pm1_status = s->pm1_status&!GBL_STS;
103 /* printf("acpiPm1Status_writew \n addr %x val:%x pm1_status:%x \n", addr, val,s->pm1_status); */
104 }
105 @@ -288,13 +282,15 @@
107 }
109 -static void acpiPm1Event_readl(void *opaque, uint32_t addr)
110 +static uint32_t acpiPm1Event_readl(void *opaque, uint32_t addr)
111 {
112 PCIAcpiState *s = opaque;
113 uint32_t val;
115 - val=s->pm1_status|(s->pm1_enable<<16);
116 + val = s->pm1_status|(s->pm1_enable<<16);
117 /* printf("acpiPm1Event_readl \n addr %x val:%x\n", addr, val); */
118 +
119 + return val;
120 }
122 static void acpiPm1Timer_writel(void *opaque, uint32_t addr, uint32_t val)
123 @@ -302,17 +298,21 @@
124 PCIAcpiState *s = opaque;
126 s->pm1_timer = val;
127 -/* printf("acpiPm1Timer_writel \n addr %x val:%x\n", addr, val); */
128 + s->old_vmck_ticks = qemu_get_clock(vm_clock) +
129 + muldiv64(val, FREQUENCE_PMTIMER, ticks_per_sec);
130 }
132 static uint32_t acpiPm1Timer_readl(void *opaque, uint32_t addr)
133 {
134 PCIAcpiState *s = opaque;
135 - uint32_t val;
136 + int64_t current_vmck_ticks = qemu_get_clock(vm_clock);
137 + int64_t vmck_ticks_delta = current_vmck_ticks - s->old_vmck_ticks;
139 - val = s->pm1_timer;
140 -/* printf("acpiPm1Timer_readl \n addr %x val:%x\n", addr, val); */
141 - return val;
142 + if (s->old_vmck_ticks)
143 + s->pm1_timer += muldiv64(vmck_ticks_delta, FREQUENCE_PMTIMER,
144 + ticks_per_sec);
145 + s->old_vmck_ticks = current_vmck_ticks;
146 + return s->pm1_timer;
147 }
149 static void acpi_map(PCIDevice *pci_dev, int region_num,
150 @@ -320,7 +320,7 @@
151 {
152 PCIAcpiState *d = (PCIAcpiState *)pci_dev;
154 - printf("register acpi io \n");
155 + printf("register acpi io\n");
157 /* Byte access */
158 register_ioport_write(addr, 1, 1, acpiPm1Status_writeb, d);
159 @@ -336,14 +336,14 @@
160 register_ioport_write(addr + 4, 1, 1, acpiPm1Control_writeb, d);
161 register_ioport_read(addr + 4, 1, 1, acpiPm1Control_readb, d);
162 register_ioport_write(addr + 4 + 1, 1, 1, acpiPm1ControlP1_writeb, d);
163 - register_ioport_read(addr + 4 +1, 1, 1, acpiPm1ControlP1_readb, d);
164 + register_ioport_read(addr + 4 +1, 1, 1, acpiPm1ControlP1_readb, d);
166 /* Word access */
167 register_ioport_write(addr, 2, 2, acpiPm1Status_writew, d);
168 register_ioport_read(addr, 2, 2, acpiPm1Status_readw, d);
170 register_ioport_write(addr + 2, 2, 2, acpiPm1Enable_writew, d);
171 - register_ioport_read(addr + 2, 2, 2, acpiPm1Enable_readw, d);
172 + register_ioport_read(addr + 2, 2, 2, acpiPm1Enable_readw, d);
174 register_ioport_write(addr + 4, 2, 2, acpiPm1Control_writew, d);
175 register_ioport_read(addr + 4, 2, 2, acpiPm1Control_readw, d);
176 @@ -351,11 +351,10 @@
177 /* DWord access */
178 register_ioport_write(addr, 4, 4, acpiPm1Event_writel, d);
179 register_ioport_read(addr, 4, 4, acpiPm1Event_readl, d);
180 -
181 +
182 register_ioport_write(addr + 8, 4, 4, acpiPm1Timer_writel, d);
183 register_ioport_read(addr + 8, 4, 4, acpiPm1Timer_readl, d);
184 }
185 -
187 /* PIIX4 acpi pci configuration space, func 3 */
188 void pci_piix4_acpi_init(PCIBus *bus)
189 @@ -384,5 +383,5 @@
190 pci_register_io_region((PCIDevice *)d, 4, 0x10,
191 PCI_ADDRESS_SPACE_IO, acpi_map);
193 - acpi_reset (d);
194 + acpi_reset(d);
195 }