debuggers.hg

view xen/arch/x86/hvm/rtc.c @ 17986:f2148e532c81

x86 hvm: Fix RTC handling.
1. Clean up initialisation/destruction.
2. Better handle per-domain time-offset changes.
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Jul 02 17:25:05 2008 +0100 (2008-07-02)
parents fd5b2ed9574a
children 71c15dfaa12b
line source
1 /*
2 * QEMU MC146818 RTC emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to
8 * deal in the Software without restriction, including without limitation the
9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
10 * sell copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
25 #include <asm/mc146818rtc.h>
26 #include <asm/hvm/vpt.h>
27 #include <asm/hvm/io.h>
28 #include <asm/hvm/support.h>
29 #include <asm/current.h>
31 #define domain_vrtc(d) (&(d)->arch.hvm_domain.pl_time.vrtc)
32 #define vcpu_vrtc(vcpu) (domain_vrtc((vcpu)->domain))
33 #define vrtc_domain(rtc) (container_of((rtc), struct domain, \
34 arch.hvm_domain.pl_time.vrtc))
35 #define vrtc_vcpu(rtc) (vrtc_domain(rtc)->vcpu[0])
37 static void rtc_periodic_cb(struct vcpu *v, void *opaque)
38 {
39 RTCState *s = opaque;
40 spin_lock(&s->lock);
41 s->hw.cmos_data[RTC_REG_C] |= 0xc0;
42 spin_unlock(&s->lock);
43 }
45 /* Enable/configure/disable the periodic timer based on the RTC_PIE and
46 * RTC_RATE_SELECT settings */
47 static void rtc_timer_update(RTCState *s)
48 {
49 int period_code, period;
50 struct vcpu *v = vrtc_vcpu(s);
52 ASSERT(spin_is_locked(&s->lock));
54 period_code = s->hw.cmos_data[RTC_REG_A] & RTC_RATE_SELECT;
55 if ( (period_code != 0) && (s->hw.cmos_data[RTC_REG_B] & RTC_PIE) )
56 {
57 if ( period_code <= 2 )
58 period_code += 7;
60 period = 1 << (period_code - 1); /* period in 32 Khz cycles */
61 period = DIV_ROUND((period * 1000000000ULL), 32768); /* period in ns */
62 create_periodic_time(v, &s->pt, period, RTC_IRQ,
63 0, rtc_periodic_cb, s);
64 }
65 else
66 {
67 destroy_periodic_time(&s->pt);
68 }
69 }
71 static void rtc_set_time(RTCState *s);
73 static int rtc_ioport_write(void *opaque, uint32_t addr, uint32_t data)
74 {
75 RTCState *s = opaque;
77 spin_lock(&s->lock);
79 if ( (addr & 1) == 0 )
80 {
81 data &= 0x7f;
82 s->hw.cmos_index = data;
83 spin_unlock(&s->lock);
84 return (data < RTC_CMOS_SIZE);
85 }
87 if ( s->hw.cmos_index >= RTC_CMOS_SIZE )
88 {
89 spin_unlock(&s->lock);
90 return 0;
91 }
93 switch ( s->hw.cmos_index )
94 {
95 case RTC_SECONDS_ALARM:
96 case RTC_MINUTES_ALARM:
97 case RTC_HOURS_ALARM:
98 s->hw.cmos_data[s->hw.cmos_index] = data;
99 break;
100 case RTC_SECONDS:
101 case RTC_MINUTES:
102 case RTC_HOURS:
103 case RTC_DAY_OF_WEEK:
104 case RTC_DAY_OF_MONTH:
105 case RTC_MONTH:
106 case RTC_YEAR:
107 s->hw.cmos_data[s->hw.cmos_index] = data;
108 /* if in set mode, do not update the time */
109 if ( !(s->hw.cmos_data[RTC_REG_B] & RTC_SET) )
110 rtc_set_time(s);
111 break;
112 case RTC_REG_A:
113 /* UIP bit is read only */
114 s->hw.cmos_data[RTC_REG_A] = (data & ~RTC_UIP) |
115 (s->hw.cmos_data[RTC_REG_A] & RTC_UIP);
116 rtc_timer_update(s);
117 break;
118 case RTC_REG_B:
119 if ( data & RTC_SET )
120 {
121 /* set mode: reset UIP mode */
122 s->hw.cmos_data[RTC_REG_A] &= ~RTC_UIP;
123 }
124 else
125 {
126 /* if disabling set mode, update the time */
127 if ( s->hw.cmos_data[RTC_REG_B] & RTC_SET )
128 rtc_set_time(s);
129 }
130 s->hw.cmos_data[RTC_REG_B] = data;
131 rtc_timer_update(s);
132 break;
133 case RTC_REG_C:
134 case RTC_REG_D:
135 /* cannot write to them */
136 break;
137 }
139 spin_unlock(&s->lock);
141 return 1;
142 }
144 static inline int to_bcd(RTCState *s, int a)
145 {
146 if ( s->hw.cmos_data[RTC_REG_B] & 0x04 )
147 return a;
148 else
149 return ((a / 10) << 4) | (a % 10);
150 }
152 static inline int from_bcd(RTCState *s, int a)
153 {
154 if ( s->hw.cmos_data[RTC_REG_B] & 0x04 )
155 return a;
156 else
157 return ((a >> 4) * 10) + (a & 0x0f);
158 }
160 static void rtc_set_time(RTCState *s)
161 {
162 struct tm *tm = &s->current_tm;
163 unsigned long before, after; /* XXX s_time_t */
165 ASSERT(spin_is_locked(&s->lock));
167 before = mktime(tm->tm_year, tm->tm_mon, tm->tm_mday,
168 tm->tm_hour, tm->tm_min, tm->tm_sec);
170 tm->tm_sec = from_bcd(s, s->hw.cmos_data[RTC_SECONDS]);
171 tm->tm_min = from_bcd(s, s->hw.cmos_data[RTC_MINUTES]);
172 tm->tm_hour = from_bcd(s, s->hw.cmos_data[RTC_HOURS] & 0x7f);
173 if ( !(s->hw.cmos_data[RTC_REG_B] & 0x02) &&
174 (s->hw.cmos_data[RTC_HOURS] & 0x80) )
175 tm->tm_hour += 12;
176 tm->tm_wday = from_bcd(s, s->hw.cmos_data[RTC_DAY_OF_WEEK]);
177 tm->tm_mday = from_bcd(s, s->hw.cmos_data[RTC_DAY_OF_MONTH]);
178 tm->tm_mon = from_bcd(s, s->hw.cmos_data[RTC_MONTH]) - 1;
179 tm->tm_year = from_bcd(s, s->hw.cmos_data[RTC_YEAR]) + 100;
181 after = mktime(tm->tm_year, tm->tm_mon, tm->tm_mday,
182 tm->tm_hour, tm->tm_min, tm->tm_sec);
183 send_timeoffset_req(after - before);
184 }
186 static void rtc_copy_date(RTCState *s)
187 {
188 const struct tm *tm = &s->current_tm;
190 ASSERT(spin_is_locked(&s->lock));
192 s->hw.cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
193 s->hw.cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
194 if ( s->hw.cmos_data[RTC_REG_B] & RTC_24H )
195 {
196 /* 24 hour format */
197 s->hw.cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
198 }
199 else
200 {
201 /* 12 hour format */
202 s->hw.cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
203 if ( tm->tm_hour >= 12 )
204 s->hw.cmos_data[RTC_HOURS] |= 0x80;
205 }
206 s->hw.cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday);
207 s->hw.cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
208 s->hw.cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
209 s->hw.cmos_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
210 }
212 /* month is between 0 and 11. */
213 static int get_days_in_month(int month, int year)
214 {
215 static const int days_tab[12] = {
216 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
217 };
218 int d;
219 if ( (unsigned)month >= 12 )
220 return 31;
221 d = days_tab[month];
222 if ( month == 1 )
223 if ( (year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0) )
224 d++;
225 return d;
226 }
228 /* update 'tm' to the next second */
229 static void rtc_next_second(RTCState *s)
230 {
231 struct tm *tm = &s->current_tm;
232 int days_in_month;
234 ASSERT(spin_is_locked(&s->lock));
236 tm->tm_sec++;
237 if ( (unsigned)tm->tm_sec >= 60 )
238 {
239 tm->tm_sec = 0;
240 tm->tm_min++;
241 if ( (unsigned)tm->tm_min >= 60 )
242 {
243 tm->tm_min = 0;
244 tm->tm_hour++;
245 if ( (unsigned)tm->tm_hour >= 24 )
246 {
247 tm->tm_hour = 0;
248 /* next day */
249 tm->tm_wday++;
250 if ( (unsigned)tm->tm_wday >= 7 )
251 tm->tm_wday = 0;
252 days_in_month = get_days_in_month(tm->tm_mon,
253 tm->tm_year + 1900);
254 tm->tm_mday++;
255 if ( tm->tm_mday < 1 )
256 {
257 tm->tm_mday = 1;
258 }
259 else if ( tm->tm_mday > days_in_month )
260 {
261 tm->tm_mday = 1;
262 tm->tm_mon++;
263 if ( tm->tm_mon >= 12 )
264 {
265 tm->tm_mon = 0;
266 tm->tm_year++;
267 }
268 }
269 }
270 }
271 }
272 }
274 static void rtc_update_second(void *opaque)
275 {
276 RTCState *s = opaque;
278 spin_lock(&s->lock);
280 /* if the oscillator is not in normal operation, we do not update */
281 if ( (s->hw.cmos_data[RTC_REG_A] & RTC_DIV_CTL) != RTC_REF_CLCK_32KHZ )
282 {
283 s->next_second_time += 1000000000ULL;
284 set_timer(&s->second_timer, s->next_second_time);
285 }
286 else
287 {
288 rtc_next_second(s);
290 if ( !(s->hw.cmos_data[RTC_REG_B] & RTC_SET) )
291 s->hw.cmos_data[RTC_REG_A] |= RTC_UIP;
293 /* Delay time before update cycle */
294 set_timer(&s->second_timer2, s->next_second_time + 244000);
295 }
297 spin_unlock(&s->lock);
298 }
300 static void rtc_update_second2(void *opaque)
301 {
302 RTCState *s = opaque;
303 struct domain *d = vrtc_domain(s);
305 spin_lock(&s->lock);
307 if ( !(s->hw.cmos_data[RTC_REG_B] & RTC_SET) )
308 rtc_copy_date(s);
310 /* check alarm */
311 if ( s->hw.cmos_data[RTC_REG_B] & RTC_AIE )
312 {
313 if ( ((s->hw.cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
314 from_bcd(s, s->hw.cmos_data[RTC_SECONDS_ALARM]) ==
315 s->current_tm.tm_sec) &&
316 ((s->hw.cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
317 from_bcd(s, s->hw.cmos_data[RTC_MINUTES_ALARM]) ==
318 s->current_tm.tm_min) &&
319 ((s->hw.cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
320 from_bcd(s, s->hw.cmos_data[RTC_HOURS_ALARM]) ==
321 s->current_tm.tm_hour) )
322 {
323 s->hw.cmos_data[RTC_REG_C] |= 0xa0;
324 hvm_isa_irq_deassert(d, RTC_IRQ);
325 hvm_isa_irq_assert(d, RTC_IRQ);
326 }
327 }
329 /* update ended interrupt */
330 if ( (s->hw.cmos_data[RTC_REG_B] & (RTC_UIE|RTC_SET)) == RTC_UIE )
331 {
332 s->hw.cmos_data[RTC_REG_C] |= 0x90;
333 hvm_isa_irq_deassert(d, RTC_IRQ);
334 hvm_isa_irq_assert(d, RTC_IRQ);
335 }
337 /* clear update in progress bit */
338 s->hw.cmos_data[RTC_REG_A] &= ~RTC_UIP;
340 s->next_second_time += 1000000000ULL;
341 set_timer(&s->second_timer, s->next_second_time);
343 spin_unlock(&s->lock);
344 }
346 static uint32_t rtc_ioport_read(RTCState *s, uint32_t addr)
347 {
348 int ret;
350 if ( (addr & 1) == 0 )
351 return 0xff;
353 spin_lock(&s->lock);
355 switch ( s->hw.cmos_index )
356 {
357 case RTC_SECONDS:
358 case RTC_MINUTES:
359 case RTC_HOURS:
360 case RTC_DAY_OF_WEEK:
361 case RTC_DAY_OF_MONTH:
362 case RTC_MONTH:
363 case RTC_YEAR:
364 ret = s->hw.cmos_data[s->hw.cmos_index];
365 break;
366 case RTC_REG_A:
367 ret = s->hw.cmos_data[s->hw.cmos_index];
368 break;
369 case RTC_REG_C:
370 ret = s->hw.cmos_data[s->hw.cmos_index];
371 hvm_isa_irq_deassert(vrtc_domain(s), RTC_IRQ);
372 s->hw.cmos_data[RTC_REG_C] = 0x00;
373 break;
374 default:
375 ret = s->hw.cmos_data[s->hw.cmos_index];
376 break;
377 }
379 spin_unlock(&s->lock);
381 return ret;
382 }
384 static int handle_rtc_io(
385 int dir, uint32_t port, uint32_t bytes, uint32_t *val)
386 {
387 struct RTCState *vrtc = vcpu_vrtc(current);
389 if ( bytes != 1 )
390 {
391 gdprintk(XENLOG_WARNING, "HVM_RTC bas access\n");
392 return X86EMUL_OKAY;
393 }
395 if ( dir == IOREQ_WRITE )
396 {
397 if ( rtc_ioport_write(vrtc, port, (uint8_t)*val) )
398 return X86EMUL_OKAY;
399 }
400 else if ( vrtc->hw.cmos_index < RTC_CMOS_SIZE )
401 {
402 *val = rtc_ioport_read(vrtc, port);
403 return X86EMUL_OKAY;
404 }
406 return X86EMUL_UNHANDLEABLE;
407 }
409 void rtc_migrate_timers(struct vcpu *v)
410 {
411 RTCState *s = vcpu_vrtc(v);
413 if ( v->vcpu_id == 0 )
414 {
415 migrate_timer(&s->second_timer, v->processor);
416 migrate_timer(&s->second_timer2, v->processor);
417 }
418 }
420 /* Save RTC hardware state */
421 static int rtc_save(struct domain *d, hvm_domain_context_t *h)
422 {
423 RTCState *s = domain_vrtc(d);
424 int rc;
425 spin_lock(&s->lock);
426 rc = hvm_save_entry(RTC, 0, h, &s->hw);
427 spin_unlock(&s->lock);
428 return rc;
429 }
431 /* Reload the hardware state from a saved domain */
432 static int rtc_load(struct domain *d, hvm_domain_context_t *h)
433 {
434 RTCState *s = domain_vrtc(d);
436 spin_lock(&s->lock);
438 /* Restore the registers */
439 if ( hvm_load_entry(RTC, h, &s->hw) != 0 )
440 {
441 spin_unlock(&s->lock);
442 return -EINVAL;
443 }
445 /* Reset the wall-clock time. In normal running, this runs with host
446 * time, so let's keep doing that. */
447 s->current_tm = gmtime(get_localtime(d));
448 rtc_copy_date(s);
449 s->next_second_time = NOW() + 1000000000ULL;
450 stop_timer(&s->second_timer);
451 set_timer(&s->second_timer2, s->next_second_time);
453 /* Reset the periodic interrupt timer based on the registers */
454 rtc_timer_update(s);
456 spin_unlock(&s->lock);
458 return 0;
459 }
461 HVM_REGISTER_SAVE_RESTORE(RTC, rtc_save, rtc_load, 1, HVMSR_PER_DOM);
463 void rtc_reset(struct domain *d)
464 {
465 RTCState *s = domain_vrtc(d);
467 destroy_periodic_time(&s->pt);
468 s->pt.source = PTSRC_isa;
469 }
471 void rtc_init(struct domain *d)
472 {
473 RTCState *s = domain_vrtc(d);
475 spin_lock_init(&s->lock);
477 init_timer(&s->second_timer, rtc_update_second, s, smp_processor_id());
478 init_timer(&s->second_timer2, rtc_update_second2, s, smp_processor_id());
480 register_portio_handler(d, RTC_PORT(0), 2, handle_rtc_io);
482 rtc_reset(d);
484 spin_lock(&s->lock);
486 s->hw.cmos_data[RTC_REG_A] = RTC_REF_CLCK_32KHZ | 6; /* ~1kHz */
487 s->hw.cmos_data[RTC_REG_B] = RTC_24H;
488 s->hw.cmos_data[RTC_REG_C] = 0;
489 s->hw.cmos_data[RTC_REG_D] = RTC_VRT;
491 s->current_tm = gmtime(get_localtime(d));
493 rtc_copy_date(s);
495 s->next_second_time = NOW() + 1000000000ULL;
496 stop_timer(&s->second_timer);
497 set_timer(&s->second_timer2, s->next_second_time);
499 spin_unlock(&s->lock);
500 }
502 void rtc_deinit(struct domain *d)
503 {
504 RTCState *s = domain_vrtc(d);
506 spin_barrier(&s->lock);
508 destroy_periodic_time(&s->pt);
509 kill_timer(&s->second_timer);
510 kill_timer(&s->second_timer2);
511 }
513 void rtc_update_clock(struct domain *d)
514 {
515 RTCState *s = domain_vrtc(d);
517 spin_lock(&s->lock);
518 s->current_tm = gmtime(get_localtime(d));
519 spin_unlock(&s->lock);
520 }