debuggers.hg

view xen/arch/x86/apic.c @ 3674:fb875591fd72

bitkeeper revision 1.1159.223.63 (42028527-fv-d9BM0_LRp8UKGP19gQ)

Fix NMI deferral.
Signed-off-by: keir.fraser@cl.cam.ac.uk
author kaf24@scramble.cl.cam.ac.uk
date Thu Feb 03 20:10:15 2005 +0000 (2005-02-03)
parents 61a55dee09d8
children 0a4b76b6b5a0
line source
1 /*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 */
16 #include <xen/config.h>
17 #include <xen/ac_timer.h>
18 #include <xen/perfc.h>
19 #include <xen/errno.h>
20 #include <xen/init.h>
21 #include <xen/mm.h>
22 #include <xen/sched.h>
23 #include <xen/irq.h>
24 #include <xen/delay.h>
25 #include <xen/smp.h>
26 #include <xen/softirq.h>
27 #include <asm/mc146818rtc.h>
28 #include <asm/msr.h>
29 #include <asm/atomic.h>
30 #include <asm/mpspec.h>
31 #include <asm/flushtlb.h>
32 #include <asm/hardirq.h>
33 #include <asm/apic.h>
34 #include <asm/io_apic.h>
37 /* Using APIC to generate smp_local_timer_interrupt? */
38 int using_apic_timer = 0;
40 static int enabled_via_apicbase;
42 int get_maxlvt(void)
43 {
44 unsigned int v, ver, maxlvt;
46 v = apic_read(APIC_LVR);
47 ver = GET_APIC_VERSION(v);
48 /* 82489DXs do not report # of LVT entries. */
49 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
50 return maxlvt;
51 }
53 void clear_local_APIC(void)
54 {
55 int maxlvt;
56 unsigned long v;
58 maxlvt = get_maxlvt();
60 /*
61 * Masking an LVT entry on a P6 can trigger a local APIC error
62 * if the vector is zero. Mask LVTERR first to prevent this.
63 */
64 if (maxlvt >= 3) {
65 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
66 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
67 }
68 /*
69 * Careful: we have to set masks only first to deassert
70 * any level-triggered sources.
71 */
72 v = apic_read(APIC_LVTT);
73 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
74 v = apic_read(APIC_LVT0);
75 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
76 v = apic_read(APIC_LVT1);
77 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
78 if (maxlvt >= 4) {
79 v = apic_read(APIC_LVTPC);
80 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
81 }
83 /*
84 * Clean APIC state for other OSs:
85 */
86 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
87 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
88 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
89 if (maxlvt >= 3)
90 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
91 if (maxlvt >= 4)
92 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
93 v = GET_APIC_VERSION(apic_read(APIC_LVR));
94 if (APIC_INTEGRATED(v)) { /* !82489DX */
95 if (maxlvt > 3)
96 apic_write(APIC_ESR, 0);
97 apic_read(APIC_ESR);
98 }
99 }
101 void __init connect_bsp_APIC(void)
102 {
103 if (pic_mode) {
104 /*
105 * Do not trust the local APIC being empty at bootup.
106 */
107 clear_local_APIC();
108 /*
109 * PIC mode, enable APIC mode in the IMCR, i.e.
110 * connect BSP's local APIC to INT and NMI lines.
111 */
112 printk("leaving PIC mode, enabling APIC mode.\n");
113 outb(0x70, 0x22);
114 outb(0x01, 0x23);
115 }
116 }
118 void disconnect_bsp_APIC(void)
119 {
120 if (pic_mode) {
121 /*
122 * Put the board back into PIC mode (has an effect
123 * only on certain older boards). Note that APIC
124 * interrupts, including IPIs, won't work beyond
125 * this point! The only exception are INIT IPIs.
126 */
127 printk("disabling APIC mode, entering PIC mode.\n");
128 outb(0x70, 0x22);
129 outb(0x00, 0x23);
130 }
131 }
133 void disable_local_APIC(void)
134 {
135 unsigned long value;
137 clear_local_APIC();
139 /*
140 * Disable APIC (implies clearing of registers
141 * for 82489DX!).
142 */
143 value = apic_read(APIC_SPIV);
144 value &= ~APIC_SPIV_APIC_ENABLED;
145 apic_write_around(APIC_SPIV, value);
147 if (enabled_via_apicbase) {
148 unsigned int l, h;
149 rdmsr(MSR_IA32_APICBASE, l, h);
150 l &= ~MSR_IA32_APICBASE_ENABLE;
151 wrmsr(MSR_IA32_APICBASE, l, h);
152 }
153 }
155 /*
156 * This is to verify that we're looking at a real local APIC.
157 * Check these against your board if the CPUs aren't getting
158 * started for no apparent reason.
159 */
160 int __init verify_local_APIC(void)
161 {
162 unsigned int reg0, reg1;
164 /*
165 * The version register is read-only in a real APIC.
166 */
167 reg0 = apic_read(APIC_LVR);
168 Dprintk("Getting VERSION: %x\n", reg0);
169 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
170 reg1 = apic_read(APIC_LVR);
171 Dprintk("Getting VERSION: %x\n", reg1);
173 /*
174 * The two version reads above should print the same
175 * numbers. If the second one is different, then we
176 * poke at a non-APIC.
177 */
178 if (reg1 != reg0)
179 return 0;
181 /*
182 * Check if the version looks reasonably.
183 */
184 reg1 = GET_APIC_VERSION(reg0);
185 if (reg1 == 0x00 || reg1 == 0xff)
186 return 0;
187 reg1 = get_maxlvt();
188 if (reg1 < 0x02 || reg1 == 0xff)
189 return 0;
191 /*
192 * The ID register is read/write in a real APIC.
193 */
194 reg0 = apic_read(APIC_ID);
195 Dprintk("Getting ID: %x\n", reg0);
196 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
197 reg1 = apic_read(APIC_ID);
198 Dprintk("Getting ID: %x\n", reg1);
199 apic_write(APIC_ID, reg0);
200 if (reg1 != (reg0 ^ APIC_ID_MASK))
201 return 0;
203 /*
204 * The next two are just to see if we have sane values.
205 * They're only really relevant if we're in Virtual Wire
206 * compatibility mode, but most boxes are anymore.
207 */
208 reg0 = apic_read(APIC_LVT0);
209 Dprintk("Getting LVT0: %x\n", reg0);
210 reg1 = apic_read(APIC_LVT1);
211 Dprintk("Getting LVT1: %x\n", reg1);
213 return 1;
214 }
216 void __init sync_Arb_IDs(void)
217 {
218 /*
219 * Wait for idle.
220 */
221 apic_wait_icr_idle();
223 Dprintk("Synchronizing Arb IDs.\n");
224 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
225 | APIC_DM_INIT);
226 }
228 extern void __error_in_apic_c (void);
230 /*
231 * WAS: An initial setup of the virtual wire mode.
232 * NOW: We don't bother doing anything. All we need at this point
233 * is to receive timer ticks, so that 'jiffies' is incremented.
234 * If we're SMP, then we can assume BIOS did setup for us.
235 * If we're UP, then the APIC should be disabled (it is at reset).
236 * If we're UP and APIC is enabled, then BIOS is clever and has
237 * probably done initial interrupt routing for us.
238 */
239 void __init init_bsp_APIC(void)
240 {
241 }
243 static unsigned long calculate_ldr(unsigned long old)
244 {
245 unsigned long id = 1UL << smp_processor_id();
246 return (old & ~APIC_LDR_MASK)|SET_APIC_LOGICAL_ID(id);
247 }
249 void __init setup_local_APIC (void)
250 {
251 unsigned long value, ver, maxlvt;
253 value = apic_read(APIC_LVR);
254 ver = GET_APIC_VERSION(value);
256 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
257 __error_in_apic_c();
259 /* Double-check wether this APIC is really registered. */
260 if (!test_bit(GET_APIC_ID(apic_read(APIC_ID)), &phys_cpu_present_map))
261 BUG();
263 /*
264 * Intel recommends to set DFR, LDR and TPR before enabling
265 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
266 * document number 292116). So here it goes...
267 */
269 /*
270 * In clustered apic mode, the firmware does this for us
271 * Put the APIC into flat delivery mode.
272 * Must be "all ones" explicitly for 82489DX.
273 */
274 apic_write_around(APIC_DFR, APIC_DFR_FLAT);
276 /*
277 * Set up the logical destination ID.
278 */
279 value = apic_read(APIC_LDR);
280 apic_write_around(APIC_LDR, calculate_ldr(value));
282 /*
283 * Set Task Priority to 'accept all'. We never change this
284 * later on.
285 */
286 value = apic_read(APIC_TASKPRI);
287 value &= ~APIC_TPRI_MASK;
288 apic_write_around(APIC_TASKPRI, value);
290 /*
291 * Now that we are all set up, enable the APIC
292 */
293 value = apic_read(APIC_SPIV);
294 value &= ~APIC_VECTOR_MASK;
295 /*
296 * Enable APIC
297 */
298 value |= APIC_SPIV_APIC_ENABLED;
300 /* Enable focus processor (bit==0) */
301 value &= ~APIC_SPIV_FOCUS_DISABLED;
303 /* Set spurious IRQ vector */
304 value |= SPURIOUS_APIC_VECTOR;
305 apic_write_around(APIC_SPIV, value);
307 /*
308 * Set up LVT0, LVT1:
309 *
310 * set up through-local-APIC on the BP's LINT0. This is not
311 * strictly necessery in pure symmetric-IO mode, but sometimes
312 * we delegate interrupts to the 8259A.
313 */
314 /*
315 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
316 */
317 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
318 if (!smp_processor_id()) {
319 value = APIC_DM_EXTINT;
320 printk("enabled ExtINT on CPU#%d\n", smp_processor_id());
321 } else {
322 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
323 printk("masked ExtINT on CPU#%d\n", smp_processor_id());
324 }
325 apic_write_around(APIC_LVT0, value);
327 /*
328 * only the BP should see the LINT1 NMI signal, obviously.
329 */
330 if (!smp_processor_id())
331 value = APIC_DM_NMI;
332 else
333 value = APIC_DM_NMI | APIC_LVT_MASKED;
334 if (!APIC_INTEGRATED(ver)) /* 82489DX */
335 value |= APIC_LVT_LEVEL_TRIGGER;
336 apic_write_around(APIC_LVT1, value);
338 if (APIC_INTEGRATED(ver)) { /* !82489DX */
339 maxlvt = get_maxlvt();
340 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
341 apic_write(APIC_ESR, 0);
342 value = apic_read(APIC_ESR);
343 printk("ESR value before enabling vector: %08lx\n", value);
345 value = ERROR_APIC_VECTOR; /* enables sending errors */
346 apic_write_around(APIC_LVTERR, value);
347 /* spec says clear errors after enabling vector. */
348 if (maxlvt > 3)
349 apic_write(APIC_ESR, 0);
350 value = apic_read(APIC_ESR);
351 printk("ESR value after enabling vector: %08lx\n", value);
352 } else {
353 printk("No ESR for 82489DX.\n");
354 }
356 if ( (smp_processor_id() == 0) && (nmi_watchdog == NMI_LOCAL_APIC) )
357 setup_apic_nmi_watchdog();
358 }
361 static inline void apic_pm_init1(void) { }
362 static inline void apic_pm_init2(void) { }
365 /*
366 * Detect and enable local APICs on non-SMP boards.
367 * Original code written by Keir Fraser.
368 */
370 static int __init detect_init_APIC (void)
371 {
372 u32 h, l, features;
373 extern void get_cpu_vendor(struct cpuinfo_x86*);
375 /* Workaround for us being called before identify_cpu(). */
376 get_cpu_vendor(&boot_cpu_data);
378 switch (boot_cpu_data.x86_vendor) {
379 case X86_VENDOR_AMD:
380 if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1)
381 break;
382 if (boot_cpu_data.x86 == 15 && cpu_has_apic)
383 break;
384 goto no_apic;
385 case X86_VENDOR_INTEL:
386 if (boot_cpu_data.x86 == 6 ||
387 (boot_cpu_data.x86 == 15 && cpu_has_apic) ||
388 (boot_cpu_data.x86 == 5 && cpu_has_apic))
389 break;
390 goto no_apic;
391 default:
392 goto no_apic;
393 }
395 if (!cpu_has_apic) {
396 /*
397 * Some BIOSes disable the local APIC in the
398 * APIC_BASE MSR. This can only be done in
399 * software for Intel P6 and AMD K7 (Model > 1).
400 */
401 rdmsr(MSR_IA32_APICBASE, l, h);
402 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
403 printk("Local APIC disabled by BIOS -- reenabling.\n");
404 l &= ~MSR_IA32_APICBASE_BASE;
405 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
406 wrmsr(MSR_IA32_APICBASE, l, h);
407 enabled_via_apicbase = 1;
408 }
409 }
411 /* The APIC feature bit should now be enabled in `cpuid' */
412 features = cpuid_edx(1);
413 if (!(features & (1 << X86_FEATURE_APIC))) {
414 printk("Could not enable APIC!\n");
415 return -1;
416 }
418 set_bit(X86_FEATURE_APIC, &boot_cpu_data.x86_capability);
419 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
420 boot_cpu_physical_apicid = 0;
422 /* The BIOS may have set up the APIC at some other address */
423 rdmsr(MSR_IA32_APICBASE, l, h);
424 if (l & MSR_IA32_APICBASE_ENABLE)
425 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
427 if (nmi_watchdog != NMI_NONE)
428 nmi_watchdog = NMI_LOCAL_APIC;
430 printk("Found and enabled local APIC!\n");
431 apic_pm_init1();
432 return 0;
434 no_apic:
435 printk("No local APIC present or hardware disabled\n");
436 return -1;
437 }
439 void __init init_apic_mappings(void)
440 {
441 unsigned long apic_phys = 0;
443 /*
444 * If no local APIC can be found then set up a fake all zeroes page to
445 * simulate the local APIC and another one for the IO-APIC.
446 */
447 if (!smp_found_config && detect_init_APIC()) {
448 apic_phys = alloc_xenheap_page();
449 apic_phys = __pa(apic_phys);
450 } else
451 apic_phys = mp_lapic_addr;
453 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
454 Dprintk("mapped APIC to %08lx (%08lx)\n", APIC_BASE, apic_phys);
456 /*
457 * Fetch the APIC ID of the BSP in case we have a
458 * default configuration (or the MP table is broken).
459 */
460 if (boot_cpu_physical_apicid == -1U)
461 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
463 #ifdef CONFIG_X86_IO_APIC
464 {
465 unsigned long ioapic_phys = 0, idx = FIX_IO_APIC_BASE_0;
466 int i;
468 for (i = 0; i < nr_ioapics; i++) {
469 if (smp_found_config)
470 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
471 set_fixmap_nocache(idx, ioapic_phys);
472 Dprintk("mapped IOAPIC to %08lx (%08lx)\n",
473 fix_to_virt(idx), ioapic_phys);
474 idx++;
475 }
476 }
477 #endif
478 }
480 /*****************************************************************************
481 * APIC calibration
482 *
483 * The APIC is programmed in bus cycles.
484 * Timeout values should specified in real time units.
485 * The "cheapest" time source is the cyclecounter.
486 *
487 * Thus, we need a mappings from: bus cycles <- cycle counter <- system time
488 *
489 * The calibration is currently a bit shoddy since it requires the external
490 * timer chip to generate periodic timer interupts.
491 *****************************************************************************/
493 /* used for system time scaling */
494 static unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */
495 static u32 bus_cycle; /* length of one bus cycle in pico-seconds */
496 static u32 bus_scale; /* scaling factor convert ns to bus cycles */
498 /*
499 * The timer chip is already set up at HZ interrupts per second here,
500 * but we do not accept timer interrupts yet. We only allow the BP
501 * to calibrate.
502 */
503 static unsigned int __init get_8254_timer_count(void)
504 {
505 /*extern spinlock_t i8253_lock;*/
506 /*unsigned long flags;*/
507 unsigned int count;
508 /*spin_lock_irqsave(&i8253_lock, flags);*/
509 outb_p(0x00, 0x43);
510 count = inb_p(0x40);
511 count |= inb_p(0x40) << 8;
512 /*spin_unlock_irqrestore(&i8253_lock, flags);*/
513 return count;
514 }
516 void __init wait_8254_wraparound(void)
517 {
518 unsigned int curr_count, prev_count=~0;
519 int delta;
520 curr_count = get_8254_timer_count();
521 do {
522 prev_count = curr_count;
523 curr_count = get_8254_timer_count();
524 delta = curr_count-prev_count;
525 /*
526 * This limit for delta seems arbitrary, but it isn't, it's slightly
527 * above the level of error a buggy Mercury/Neptune chipset timer can
528 * cause.
529 */
530 } while (delta < 300);
531 }
533 /*
534 * This function sets up the local APIC timer, with a timeout of
535 * 'clocks' APIC bus clock. During calibration we actually call
536 * this function with a very large value and read the current time after
537 * a well defined period of time as expired.
538 *
539 * Calibration is only performed once, for CPU0!
540 *
541 * We do reads before writes even if unnecessary, to get around the
542 * P5 APIC double write bug.
543 */
544 #define APIC_DIVISOR 1
545 static void __setup_APIC_LVTT(unsigned int clocks)
546 {
547 unsigned int lvtt1_value, tmp_value;
548 lvtt1_value = SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV)|LOCAL_TIMER_VECTOR;
549 apic_write_around(APIC_LVTT, lvtt1_value);
550 tmp_value = apic_read(APIC_TDCR);
551 apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
552 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
553 }
555 /*
556 * this is done for every CPU from setup_APIC_clocks() below.
557 * We setup each local APIC with a zero timeout value for now.
558 * Unlike Linux, we don't have to wait for slices etc.
559 */
560 void setup_APIC_timer(void * data)
561 {
562 unsigned long flags;
563 __save_flags(flags);
564 __sti();
565 __setup_APIC_LVTT(0);
566 __restore_flags(flags);
567 }
569 /*
570 * In this function we calibrate APIC bus clocks to the external timer.
571 *
572 * As a result we have the Bys Speed and CPU speed in Hz.
573 *
574 * We want to do the calibration only once (for CPU0). CPUs connected by the
575 * same APIC bus have the very same bus frequency.
576 *
577 * This bit is a bit shoddy since we use the very same periodic timer interrupt
578 * we try to eliminate to calibrate the APIC.
579 */
581 int __init calibrate_APIC_clock(void)
582 {
583 unsigned long long t1 = 0, t2 = 0;
584 long tt1, tt2;
585 long result;
586 int i;
587 const int LOOPS = HZ/10;
589 printk("Calibrating APIC timer for CPU%d...\n", smp_processor_id());
591 /* Put whatever arbitrary (but long enough) timeout
592 * value into the APIC clock, we just want to get the
593 * counter running for calibration. */
594 __setup_APIC_LVTT(1000000000);
596 /* The timer chip counts down to zero. Let's wait
597 * for a wraparound to start exact measurement:
598 * (the current tick might have been already half done) */
599 wait_8254_wraparound();
601 /* We wrapped around just now. Let's start: */
602 rdtscll(t1);
603 tt1 = apic_read(APIC_TMCCT);
605 /* Let's wait LOOPS wraprounds: */
606 for (i = 0; i < LOOPS; i++)
607 wait_8254_wraparound();
609 tt2 = apic_read(APIC_TMCCT);
610 rdtscll(t2);
612 /* The APIC bus clock counter is 32 bits only, it
613 * might have overflown, but note that we use signed
614 * longs, thus no extra care needed.
615 * underflown to be exact, as the timer counts down ;) */
616 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
618 printk("..... CPU speed is %ld.%04ld MHz.\n",
619 ((long)(t2-t1)/LOOPS) / (1000000/HZ),
620 ((long)(t2-t1)/LOOPS) % (1000000/HZ));
622 printk("..... Bus speed is %ld.%04ld MHz.\n",
623 result / (1000000/HZ),
624 result % (1000000/HZ));
626 /*
627 * KAF: Moved this to time.c where it's calculated relative to the TSC.
628 * Therefore works on machines with no local APIC.
629 */
630 /*cpu_freq = (u64)(((t2-t1)/LOOPS)*HZ);*/
632 /* set up multipliers for accurate timer code */
633 bus_freq = result*HZ;
634 bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */
635 bus_scale = (1000*262144)/bus_cycle;
637 printk("..... bus_scale = 0x%08X\n", bus_scale);
638 /* reset APIC to zero timeout value */
639 __setup_APIC_LVTT(0);
640 return result;
641 }
643 /*
644 * initialise the APIC timers for all CPUs
645 * we start with the first and find out processor frequency and bus speed
646 */
647 void __init setup_APIC_clocks (void)
648 {
649 printk("Using local APIC timer interrupts.\n");
650 using_apic_timer = 1;
651 __cli();
652 /* calibrate CPU0 for CPU speed and BUS speed */
653 bus_freq = calibrate_APIC_clock();
654 /* Now set up the timer for real. */
655 setup_APIC_timer((void *)bus_freq);
656 __sti();
657 /* and update all other cpus */
658 smp_call_function(setup_APIC_timer, (void *)bus_freq, 1, 1);
659 }
661 #undef APIC_DIVISOR
663 /*
664 * reprogram the APIC timer. Timeoutvalue is in ns from start of boot
665 * returns 1 on success
666 * returns 0 if the timeout value is too small or in the past.
667 */
668 int reprogram_ac_timer(s_time_t timeout)
669 {
670 s_time_t now;
671 s_time_t expire;
672 u64 apic_tmict;
674 /*
675 * We use this value because we don't trust zero (we think it may just
676 * cause an immediate interrupt). At least this is guaranteed to hold it
677 * off for ages (esp. since the clock ticks on bus clock, not cpu clock!).
678 */
679 if ( timeout == 0 )
680 {
681 apic_tmict = 0xffffffff;
682 goto reprogram;
683 }
685 now = NOW();
686 expire = timeout - now; /* value from now */
688 if ( expire <= 0 )
689 {
690 Dprintk("APICT[%02d] Timeout in the past 0x%08X%08X > 0x%08X%08X\n",
691 smp_processor_id(), (u32)(now>>32),
692 (u32)now, (u32)(timeout>>32),(u32)timeout);
693 return 0;
694 }
696 /*
697 * If we don't have local APIC then we just poll the timer list off the
698 * PIT interrupt. Cheesy but good enough to work on eg. VMware :-)
699 */
700 if ( !cpu_has_apic )
701 return 1;
703 /* conversion to bus units */
704 apic_tmict = (((u64)bus_scale) * expire)>>18;
706 if ( apic_tmict >= 0xffffffff )
707 {
708 Dprintk("APICT[%02d] Timeout value too large\n", smp_processor_id());
709 apic_tmict = 0xffffffff;
710 }
712 if ( apic_tmict == 0 )
713 {
714 Dprintk("APICT[%02d] timeout value too small\n", smp_processor_id());
715 return 0;
716 }
718 reprogram:
719 /* Program the timer. */
720 apic_write(APIC_TMICT, (unsigned long)apic_tmict);
722 return 1;
723 }
725 unsigned int apic_timer_irqs [NR_CPUS];
727 void smp_apic_timer_interrupt(struct xen_regs * regs)
728 {
729 ack_APIC_irq();
731 apic_timer_irqs[smp_processor_id()]++;
732 perfc_incrc(apic_timer);
734 raise_softirq(AC_TIMER_SOFTIRQ);
735 }
737 /*
738 * This interrupt should _never_ happen with our APIC/SMP architecture
739 */
740 asmlinkage void smp_spurious_interrupt(void)
741 {
742 unsigned long v;
744 /*
745 * Check if this really is a spurious interrupt and ACK it
746 * if it is a vectored one. Just in case...
747 * Spurious interrupts should not be ACKed.
748 */
749 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
750 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
751 ack_APIC_irq();
753 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
754 printk("spurious APIC interrupt on CPU#%d, should never happen.\n",
755 smp_processor_id());
756 }
758 /*
759 * This interrupt should never happen with our APIC/SMP architecture
760 */
762 asmlinkage void smp_error_interrupt(void)
763 {
764 unsigned long v, v1;
766 /* First tickle the hardware, only then report what went on. -- REW */
767 v = apic_read(APIC_ESR);
768 apic_write(APIC_ESR, 0);
769 v1 = apic_read(APIC_ESR);
770 ack_APIC_irq();
771 atomic_inc(&irq_err_count);
773 /* Here is what the APIC error bits mean:
774 0: Send CS error
775 1: Receive CS error
776 2: Send accept error
777 3: Receive accept error
778 4: Reserved
779 5: Send illegal vector
780 6: Received illegal vector
781 7: Illegal register address
782 */
783 printk ("APIC error on CPU%d: %02lx(%02lx)\n",
784 smp_processor_id(), v , v1);
785 }
787 /*
788 * This initializes the IO-APIC and APIC hardware if this is
789 * a UP kernel.
790 */
791 int __init APIC_init_uniprocessor (void)
792 {
793 if (!smp_found_config && !cpu_has_apic)
794 return -1;
796 /*
797 * Complain if the BIOS pretends there is one.
798 */
799 if (!cpu_has_apic&&APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]))
800 {
801 printk("BIOS bug, local APIC #%d not detected!...\n",
802 boot_cpu_physical_apicid);
803 return -1;
804 }
806 verify_local_APIC();
808 connect_bsp_APIC();
810 #ifdef CONFIG_SMP
811 cpu_online_map = 1;
812 #endif
813 phys_cpu_present_map = 1;
814 apic_write_around(APIC_ID, boot_cpu_physical_apicid);
816 apic_pm_init2();
818 setup_local_APIC();
820 #ifdef CONFIG_X86_IO_APIC
821 if (smp_found_config && nr_ioapics)
822 setup_IO_APIC();
823 #endif
824 setup_APIC_clocks();
826 return 0;
827 }