debuggers.hg

view xen/arch/x86/io_apic.c @ 3674:fb875591fd72

bitkeeper revision 1.1159.223.63 (42028527-fv-d9BM0_LRp8UKGP19gQ)

Fix NMI deferral.
Signed-off-by: keir.fraser@cl.cam.ac.uk
author kaf24@scramble.cl.cam.ac.uk
date Thu Feb 03 20:10:15 2005 +0000 (2005-02-03)
parents 60e5912b6b28
children b2fa96909734
line source
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
23 #include <xen/config.h>
24 #include <xen/init.h>
25 #include <xen/irq.h>
26 #include <xen/delay.h>
27 #include <xen/sched.h>
28 #include <xen/config.h>
29 #include <asm/mc146818rtc.h>
30 #include <asm/io.h>
31 #include <asm/mpspec.h>
32 #include <asm/io_apic.h>
33 #include <asm/smp.h>
34 #include <asm/desc.h>
35 #include <asm/smpboot.h>
37 #ifdef CONFIG_X86_IO_APIC
39 #undef APIC_LOCKUP_DEBUG
41 #define APIC_LOCKUP_DEBUG
43 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
45 unsigned int int_dest_addr_mode = APIC_DEST_LOGICAL;
46 unsigned char int_delivery_mode = dest_LowestPrio;
49 /*
50 * # of IRQ routing registers
51 */
52 int nr_ioapic_registers[MAX_IO_APICS];
54 /*
55 * Rough estimation of how many shared IRQs there are, can
56 * be changed anytime.
57 */
58 #define MAX_PLUS_SHARED_IRQS NR_IRQS
59 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
61 /*
62 * This is performance-critical, we want to do it O(1)
63 *
64 * the indexing order of this array favors 1:1 mappings
65 * between pins and IRQs.
66 */
68 static struct irq_pin_list {
69 int apic, pin, next;
70 } irq_2_pin[PIN_MAP_SIZE];
72 /*
73 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
74 * shared ISA-space IRQs, so we have to support them. We are super
75 * fast in the common case, and fast for shared ISA-space IRQs.
76 */
77 static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
78 {
79 static int first_free_entry = NR_IRQS;
80 struct irq_pin_list *entry = irq_2_pin + irq;
82 while (entry->next)
83 entry = irq_2_pin + entry->next;
85 if (entry->pin != -1) {
86 entry->next = first_free_entry;
87 entry = irq_2_pin + entry->next;
88 if (++first_free_entry >= PIN_MAP_SIZE)
89 panic("io_apic.c: whoops");
90 }
91 entry->apic = apic;
92 entry->pin = pin;
93 }
95 /*
96 * Reroute an IRQ to a different pin.
97 */
98 static void __init replace_pin_at_irq(unsigned int irq,
99 int oldapic, int oldpin,
100 int newapic, int newpin)
101 {
102 struct irq_pin_list *entry = irq_2_pin + irq;
104 while (1) {
105 if (entry->apic == oldapic && entry->pin == oldpin) {
106 entry->apic = newapic;
107 entry->pin = newpin;
108 }
109 if (!entry->next)
110 break;
111 entry = irq_2_pin + entry->next;
112 }
113 }
115 #define __DO_ACTION(R, ACTION, FINAL) \
116 \
117 { \
118 int pin; \
119 struct irq_pin_list *entry = irq_2_pin + irq; \
120 \
121 for (;;) { \
122 unsigned int reg; \
123 pin = entry->pin; \
124 if (pin == -1) \
125 break; \
126 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
127 reg ACTION; \
128 io_apic_write(entry->apic, 0x10 + R + pin*2, reg); \
129 if (!entry->next) \
130 break; \
131 entry = irq_2_pin + entry->next; \
132 } \
133 FINAL; \
134 }
136 #define DO_ACTION(name,R,ACTION, FINAL) \
137 \
138 static void name##_IO_APIC_irq (unsigned int irq) \
139 __DO_ACTION(R, ACTION, FINAL)
141 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
142 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
143 DO_ACTION( __edge, 0, &= 0xffff7fff, )
144 DO_ACTION( __level, 0, |= 0x00008000, )
146 static void mask_IO_APIC_irq (unsigned int irq)
147 {
148 unsigned long flags;
150 spin_lock_irqsave(&ioapic_lock, flags);
151 __mask_IO_APIC_irq(irq);
152 spin_unlock_irqrestore(&ioapic_lock, flags);
153 }
155 static void unmask_IO_APIC_irq (unsigned int irq)
156 {
157 unsigned long flags;
159 spin_lock_irqsave(&ioapic_lock, flags);
160 __unmask_IO_APIC_irq(irq);
161 spin_unlock_irqrestore(&ioapic_lock, flags);
162 }
164 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
165 {
166 struct IO_APIC_route_entry entry;
167 unsigned long flags;
169 /* Check delivery_mode to be sure we're not clearing an SMI pin */
170 spin_lock_irqsave(&ioapic_lock, flags);
171 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
172 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
173 spin_unlock_irqrestore(&ioapic_lock, flags);
174 if (entry.delivery_mode == dest_SMI)
175 return;
177 /*
178 * Disable it in the IO-APIC irq-routing table:
179 */
180 memset(&entry, 0, sizeof(entry));
181 entry.mask = 1;
182 spin_lock_irqsave(&ioapic_lock, flags);
183 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
184 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
185 spin_unlock_irqrestore(&ioapic_lock, flags);
186 }
188 static void clear_IO_APIC (void)
189 {
190 int apic, pin;
192 for (apic = 0; apic < nr_ioapics; apic++)
193 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
194 clear_IO_APIC_pin(apic, pin);
195 }
197 static void set_ioapic_affinity (unsigned int irq, unsigned long mask)
198 {
199 unsigned long flags;
201 /*
202 * Only the first 8 bits are valid.
203 */
204 mask = mask << 24;
205 spin_lock_irqsave(&ioapic_lock, flags);
206 __DO_ACTION(1, = mask, )
207 spin_unlock_irqrestore(&ioapic_lock, flags);
208 }
210 #define balance_irq(_irq) ((void)0)
212 /*
213 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
214 * specific CPU-side IRQs.
215 */
217 #define MAX_PIRQS 8
218 int pirq_entries [MAX_PIRQS];
219 int pirqs_enabled;
221 int skip_ioapic_setup;
222 #if 0
224 static int __init noioapic_setup(char *str)
225 {
226 skip_ioapic_setup = 1;
227 return 1;
228 }
230 __setup("noapic", noioapic_setup);
232 static int __init ioapic_setup(char *str)
233 {
234 skip_ioapic_setup = 0;
235 return 1;
236 }
238 __setup("apic", ioapic_setup);
242 static int __init ioapic_pirq_setup(char *str)
243 {
244 int i, max;
245 int ints[MAX_PIRQS+1];
247 get_options(str, ARRAY_SIZE(ints), ints);
249 for (i = 0; i < MAX_PIRQS; i++)
250 pirq_entries[i] = -1;
252 pirqs_enabled = 1;
253 printk(KERN_INFO "PIRQ redirection, working around broken MP-BIOS.\n");
254 max = MAX_PIRQS;
255 if (ints[0] < MAX_PIRQS)
256 max = ints[0];
258 for (i = 0; i < max; i++) {
259 printk(KERN_DEBUG "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
260 /*
261 * PIRQs are mapped upside down, usually.
262 */
263 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
264 }
265 return 1;
266 }
268 __setup("pirq=", ioapic_pirq_setup);
270 #endif
272 /*
273 * Find the IRQ entry number of a certain pin.
274 */
275 static int __init find_irq_entry(int apic, int pin, int type)
276 {
277 int i;
279 for (i = 0; i < mp_irq_entries; i++)
280 if (mp_irqs[i].mpc_irqtype == type &&
281 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
282 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
283 mp_irqs[i].mpc_dstirq == pin)
284 return i;
286 return -1;
287 }
289 /*
290 * Find the pin to which IRQ[irq] (ISA) is connected
291 */
292 static int __init find_isa_irq_pin(int irq, int type)
293 {
294 int i;
296 for (i = 0; i < mp_irq_entries; i++) {
297 int lbus = mp_irqs[i].mpc_srcbus;
299 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
300 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
301 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
302 (mp_irqs[i].mpc_irqtype == type) &&
303 (mp_irqs[i].mpc_srcbusirq == irq))
305 return mp_irqs[i].mpc_dstirq;
306 }
307 return -1;
308 }
310 /*
311 * Find a specific PCI IRQ entry.
312 * Not an __init, possibly needed by modules
313 */
314 static int pin_2_irq(int idx, int apic, int pin);
316 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
317 {
318 int apic, i, best_guess = -1;
320 Dprintk("querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
321 bus, slot, pin);
322 if ((mp_bus_id_to_pci_bus==NULL) || (mp_bus_id_to_pci_bus[bus] == -1)) {
323 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
324 return -1;
325 }
326 for (i = 0; i < mp_irq_entries; i++) {
327 int lbus = mp_irqs[i].mpc_srcbus;
329 for (apic = 0; apic < nr_ioapics; apic++)
330 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
331 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
332 break;
334 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
335 !mp_irqs[i].mpc_irqtype &&
336 (bus == lbus) &&
337 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
338 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
340 if (!(apic || IO_APIC_IRQ(irq)))
341 continue;
343 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
344 return irq;
345 /*
346 * Use the first all-but-pin matching entry as a
347 * best-guess fuzzy result for broken mptables.
348 */
349 if (best_guess < 0)
350 best_guess = irq;
351 }
352 }
353 return best_guess;
354 }
356 /*
357 * EISA Edge/Level control register, ELCR
358 */
359 static int __init EISA_ELCR(unsigned int irq)
360 {
361 if (irq < 16) {
362 unsigned int port = 0x4d0 + (irq >> 3);
363 return (inb(port) >> (irq & 7)) & 1;
364 }
365 printk(KERN_INFO "Broken MPtable reports ISA irq %d\n", irq);
366 return 0;
367 }
369 /* EISA interrupts are always polarity zero and can be edge or level
370 * trigger depending on the ELCR value. If an interrupt is listed as
371 * EISA conforming in the MP table, that means its trigger type must
372 * be read in from the ELCR */
374 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
375 #define default_EISA_polarity(idx) (0)
377 /* ISA interrupts are always polarity zero edge triggered,
378 * when listed as conforming in the MP table. */
380 #define default_ISA_trigger(idx) (0)
381 #define default_ISA_polarity(idx) (0)
383 /* PCI interrupts are always polarity one level triggered,
384 * when listed as conforming in the MP table. */
386 #define default_PCI_trigger(idx) (1)
387 #define default_PCI_polarity(idx) (1)
389 /* MCA interrupts are always polarity zero level triggered,
390 * when listed as conforming in the MP table. */
392 #define default_MCA_trigger(idx) (1)
393 #define default_MCA_polarity(idx) (0)
395 static int __init MPBIOS_polarity(int idx)
396 {
397 int bus = mp_irqs[idx].mpc_srcbus;
398 int polarity;
400 /*
401 * Determine IRQ line polarity (high active or low active):
402 */
403 switch (mp_irqs[idx].mpc_irqflag & 3)
404 {
405 case 0: /* conforms, ie. bus-type dependent polarity */
406 {
407 switch (mp_bus_id_to_type[bus])
408 {
409 case MP_BUS_ISA: /* ISA pin */
410 {
411 polarity = default_ISA_polarity(idx);
412 break;
413 }
414 case MP_BUS_EISA: /* EISA pin */
415 {
416 polarity = default_EISA_polarity(idx);
417 break;
418 }
419 case MP_BUS_PCI: /* PCI pin */
420 {
421 polarity = default_PCI_polarity(idx);
422 break;
423 }
424 case MP_BUS_MCA: /* MCA pin */
425 {
426 polarity = default_MCA_polarity(idx);
427 break;
428 }
429 default:
430 {
431 printk(KERN_WARNING "broken BIOS!!\n");
432 polarity = 1;
433 break;
434 }
435 }
436 break;
437 }
438 case 1: /* high active */
439 {
440 polarity = 0;
441 break;
442 }
443 case 2: /* reserved */
444 {
445 printk(KERN_WARNING "broken BIOS!!\n");
446 polarity = 1;
447 break;
448 }
449 case 3: /* low active */
450 {
451 polarity = 1;
452 break;
453 }
454 default: /* invalid */
455 {
456 printk(KERN_WARNING "broken BIOS!!\n");
457 polarity = 1;
458 break;
459 }
460 }
461 return polarity;
462 }
464 static int __init MPBIOS_trigger(int idx)
465 {
466 int bus = mp_irqs[idx].mpc_srcbus;
467 int trigger;
469 /*
470 * Determine IRQ trigger mode (edge or level sensitive):
471 */
472 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
473 {
474 case 0: /* conforms, ie. bus-type dependent */
475 {
476 switch (mp_bus_id_to_type[bus])
477 {
478 case MP_BUS_ISA: /* ISA pin */
479 {
480 trigger = default_ISA_trigger(idx);
481 break;
482 }
483 case MP_BUS_EISA: /* EISA pin */
484 {
485 trigger = default_EISA_trigger(idx);
486 break;
487 }
488 case MP_BUS_PCI: /* PCI pin */
489 {
490 trigger = default_PCI_trigger(idx);
491 break;
492 }
493 case MP_BUS_MCA: /* MCA pin */
494 {
495 trigger = default_MCA_trigger(idx);
496 break;
497 }
498 default:
499 {
500 printk(KERN_WARNING "broken BIOS!!\n");
501 trigger = 1;
502 break;
503 }
504 }
505 break;
506 }
507 case 1: /* edge */
508 {
509 trigger = 0;
510 break;
511 }
512 case 2: /* reserved */
513 {
514 printk(KERN_WARNING "broken BIOS!!\n");
515 trigger = 1;
516 break;
517 }
518 case 3: /* level */
519 {
520 trigger = 1;
521 break;
522 }
523 default: /* invalid */
524 {
525 printk(KERN_WARNING "broken BIOS!!\n");
526 trigger = 0;
527 break;
528 }
529 }
530 return trigger;
531 }
533 static inline int irq_polarity(int idx)
534 {
535 return MPBIOS_polarity(idx);
536 }
538 static inline int irq_trigger(int idx)
539 {
540 return MPBIOS_trigger(idx);
541 }
543 static int pin_2_irq(int idx, int apic, int pin)
544 {
545 int irq, i;
546 int bus = mp_irqs[idx].mpc_srcbus;
548 /*
549 * Debugging check, we are in big trouble if this message pops up!
550 */
551 if (mp_irqs[idx].mpc_dstirq != pin)
552 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
554 switch (mp_bus_id_to_type[bus])
555 {
556 case MP_BUS_ISA: /* ISA pin */
557 case MP_BUS_EISA:
558 case MP_BUS_MCA:
559 {
560 irq = mp_irqs[idx].mpc_srcbusirq;
561 break;
562 }
563 case MP_BUS_PCI: /* PCI pin */
564 {
565 /*
566 * PCI IRQs are mapped in order
567 */
568 i = irq = 0;
569 while (i < apic)
570 irq += nr_ioapic_registers[i++];
571 irq += pin;
572 break;
573 }
574 default:
575 {
576 printk(KERN_ERR "unknown bus type %d.\n",bus);
577 irq = 0;
578 break;
579 }
580 }
582 /*
583 * PCI IRQ command line redirection. Yes, limits are hardcoded.
584 */
585 if ((pin >= 16) && (pin <= 23)) {
586 if (pirq_entries[pin-16] != -1) {
587 if (!pirq_entries[pin-16]) {
588 printk(KERN_DEBUG "disabling PIRQ%d\n", pin-16);
589 } else {
590 irq = pirq_entries[pin-16];
591 printk(KERN_DEBUG "using PIRQ%d -> IRQ %d\n",
592 pin-16, irq);
593 }
594 }
595 }
596 return irq;
597 }
599 static inline int IO_APIC_irq_trigger(int irq)
600 {
601 int apic, idx, pin;
603 for (apic = 0; apic < nr_ioapics; apic++) {
604 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
605 idx = find_irq_entry(apic,pin,mp_INT);
606 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
607 return irq_trigger(idx);
608 }
609 }
610 /*
611 * nonexistent IRQs are edge default
612 */
613 return 0;
614 }
616 int irq_vector[NR_IRQS] = { FIRST_DEVICE_VECTOR , 0 };
618 static int __init assign_irq_vector(int irq)
619 {
620 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
621 if (IO_APIC_VECTOR(irq) > 0)
622 return IO_APIC_VECTOR(irq);
623 next:
624 current_vector += 8;
626 /* Skip the hypercall vector. */
627 if (current_vector == HYPERCALL_VECTOR) goto next;
628 /* Skip the Linux/BSD fast-trap vector. */
629 if (current_vector == 0x80) goto next;
631 if (current_vector > FIRST_SYSTEM_VECTOR) {
632 offset++;
633 current_vector = FIRST_DEVICE_VECTOR + offset;
634 }
636 if (current_vector == FIRST_SYSTEM_VECTOR)
637 panic("ran out of interrupt sources!");
639 IO_APIC_VECTOR(irq) = current_vector;
640 return current_vector;
641 }
643 extern void (*interrupt[NR_IRQS])(void);
645 /*
646 * Level and edge triggered IO-APIC interrupts need different handling,
647 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
648 * handled with the level-triggered descriptor, but that one has slightly
649 * more overhead. Level-triggered interrupts cannot be handled with the
650 * edge-triggered handler, without risking IRQ storms and other ugly
651 * races.
652 */
654 static unsigned int startup_edge_ioapic_irq(unsigned int irq);
655 #define shutdown_edge_ioapic_irq disable_edge_ioapic_irq
656 #define enable_edge_ioapic_irq unmask_IO_APIC_irq
657 static void disable_edge_ioapic_irq (unsigned int irq);
658 static void ack_edge_ioapic_irq(unsigned int irq);
659 static void end_edge_ioapic_irq (unsigned int i);
660 static struct hw_interrupt_type ioapic_edge_irq_type = {
661 "IO-APIC-edge",
662 startup_edge_ioapic_irq,
663 shutdown_edge_ioapic_irq,
664 enable_edge_ioapic_irq,
665 disable_edge_ioapic_irq,
666 ack_edge_ioapic_irq,
667 end_edge_ioapic_irq,
668 set_ioapic_affinity,
669 };
671 static unsigned int startup_level_ioapic_irq (unsigned int irq);
672 #define shutdown_level_ioapic_irq mask_IO_APIC_irq
673 #define enable_level_ioapic_irq unmask_IO_APIC_irq
674 #define disable_level_ioapic_irq mask_IO_APIC_irq
675 static void mask_and_ack_level_ioapic_irq (unsigned int irq);
676 static void end_level_ioapic_irq (unsigned int irq);
677 static struct hw_interrupt_type ioapic_level_irq_type = {
678 "IO-APIC-level",
679 startup_level_ioapic_irq,
680 shutdown_level_ioapic_irq,
681 enable_level_ioapic_irq,
682 disable_level_ioapic_irq,
683 mask_and_ack_level_ioapic_irq,
684 end_level_ioapic_irq,
685 set_ioapic_affinity,
686 };
688 void __init setup_IO_APIC_irqs(void)
689 {
690 struct IO_APIC_route_entry entry;
691 int apic, pin, idx, irq, vector;
692 unsigned long flags;
694 printk(KERN_DEBUG "init IO_APIC IRQs\n");
696 for (apic = 0; apic < nr_ioapics; apic++) {
697 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
699 /*
700 * add it to the IO-APIC irq-routing table:
701 */
702 memset(&entry,0,sizeof(entry));
704 entry.delivery_mode = INT_DELIVERY_MODE;
705 entry.dest_mode = (INT_DEST_ADDR_MODE != 0);
706 entry.mask = 0; /* enable IRQ */
707 entry.dest.logical.logical_dest = target_cpus();
709 idx = find_irq_entry(apic,pin,mp_INT);
710 if (idx == -1)
711 continue;
713 entry.trigger = irq_trigger(idx);
714 entry.polarity = irq_polarity(idx);
716 if (irq_trigger(idx)) {
717 entry.trigger = 1;
718 entry.mask = 1;
719 }
721 irq = pin_2_irq(idx, apic, pin);
722 /*
723 * skip adding the timer int on secondary nodes, which causes
724 * a small but painful rift in the time-space continuum
725 */
726 if ((clustered_apic_mode == CLUSTERED_APIC_NUMAQ)
727 && (apic != 0) && (irq == 0))
728 continue;
729 else
730 add_pin_to_irq(irq, apic, pin);
732 if (!apic && !IO_APIC_IRQ(irq))
733 continue;
735 if (IO_APIC_IRQ(irq)) {
736 vector = assign_irq_vector(irq);
737 entry.vector = vector;
739 if (IO_APIC_irq_trigger(irq))
740 irq_desc[irq].handler = &ioapic_level_irq_type;
741 else
742 irq_desc[irq].handler = &ioapic_edge_irq_type;
744 set_intr_gate(vector, interrupt[irq]);
746 if (!apic && (irq < 16))
747 disable_8259A_irq(irq);
748 }
749 spin_lock_irqsave(&ioapic_lock, flags);
750 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
751 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
752 spin_unlock_irqrestore(&ioapic_lock, flags);
753 }
754 }
755 }
757 /*
758 * Set up the 8259A-master output pin as broadcast to all
759 * CPUs.
760 */
761 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
762 {
763 struct IO_APIC_route_entry entry;
764 unsigned long flags;
766 memset(&entry,0,sizeof(entry));
768 disable_8259A_irq(0);
770 /* mask LVT0 */
771 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
773 /*
774 * We use logical delivery to get the timer IRQ
775 * to the first CPU.
776 */
777 entry.dest_mode = (INT_DEST_ADDR_MODE != 0);
778 entry.mask = 0; /* unmask IRQ now */
779 entry.dest.logical.logical_dest = target_cpus();
780 entry.delivery_mode = INT_DELIVERY_MODE;
781 entry.polarity = 0;
782 entry.trigger = 0;
783 entry.vector = vector;
785 /*
786 * The timer IRQ doesn't have to know that behind the
787 * scene we have a 8259A-master in AEOI mode ...
788 */
789 irq_desc[0].handler = &ioapic_edge_irq_type;
791 /*
792 * Add it to the IO-APIC irq-routing table:
793 */
794 spin_lock_irqsave(&ioapic_lock, flags);
795 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
796 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
797 spin_unlock_irqrestore(&ioapic_lock, flags);
799 enable_8259A_irq(0);
800 }
802 void __init UNEXPECTED_IO_APIC(void)
803 {
804 printk(KERN_WARNING
805 "An unexpected IO-APIC was found. If this kernel release is less than\n"
806 "three months old please report this to linux-smp@vger.kernel.org\n");
807 }
809 void __init print_IO_APIC(void)
810 {
811 #ifdef VERBOSE
812 int apic, i;
813 struct IO_APIC_reg_00 reg_00;
814 struct IO_APIC_reg_01 reg_01;
815 struct IO_APIC_reg_02 reg_02;
816 struct IO_APIC_reg_03 reg_03;
817 unsigned long flags;
819 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
820 for (i = 0; i < nr_ioapics; i++)
821 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
822 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
824 /*
825 * We are a bit conservative about what we expect. We have to
826 * know about every hardware change ASAP.
827 */
828 printk(KERN_INFO "testing the IO APIC.......................\n");
830 for (apic = 0; apic < nr_ioapics; apic++) {
832 spin_lock_irqsave(&ioapic_lock, flags);
833 *(int *)&reg_00 = io_apic_read(apic, 0);
834 *(int *)&reg_01 = io_apic_read(apic, 1);
835 if (reg_01.version >= 0x10)
836 *(int *)&reg_02 = io_apic_read(apic, 2);
837 if (reg_01.version >= 0x20)
838 *(int *)&reg_03 = io_apic_read(apic, 3);
839 spin_unlock_irqrestore(&ioapic_lock, flags);
841 printk("\n");
842 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
843 printk(KERN_DEBUG ".... register #00: %08X\n", *(int *)&reg_00);
844 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.ID);
845 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.delivery_type);
846 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.LTS);
847 if (reg_00.__reserved_0 || reg_00.__reserved_1 || reg_00.__reserved_2)
848 UNEXPECTED_IO_APIC();
850 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
851 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.entries);
852 if ( (reg_01.entries != 0x0f) && /* older (Neptune) boards */
853 (reg_01.entries != 0x17) && /* typical ISA+PCI boards */
854 (reg_01.entries != 0x1b) && /* Compaq Proliant boards */
855 (reg_01.entries != 0x1f) && /* dual Xeon boards */
856 (reg_01.entries != 0x22) && /* bigger Xeon boards */
857 (reg_01.entries != 0x2E) &&
858 (reg_01.entries != 0x3F)
859 )
860 UNEXPECTED_IO_APIC();
862 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.PRQ);
863 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.version);
864 if ( (reg_01.version != 0x01) && /* 82489DX IO-APICs */
865 (reg_01.version != 0x02) && /* VIA */
866 (reg_01.version != 0x03) && /* later VIA */
867 (reg_01.version != 0x10) && /* oldest IO-APICs */
868 (reg_01.version != 0x11) && /* Pentium/Pro IO-APICs */
869 (reg_01.version != 0x13) && /* Xeon IO-APICs */
870 (reg_01.version != 0x20) /* Intel P64H (82806 AA) */
871 )
872 UNEXPECTED_IO_APIC();
873 if (reg_01.__reserved_1 || reg_01.__reserved_2)
874 UNEXPECTED_IO_APIC();
876 /*
877 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
878 * but the value of reg_02 is read as the previous read register
879 * value, so ignore it if reg_02 == reg_01.
880 */
881 if (reg_01.version >= 0x10 && *(int *)&reg_02 != *(int *)&reg_01) {
882 printk(KERN_DEBUG ".... register #02: %08X\n", *(int *)&reg_02);
883 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.arbitration);
884 if (reg_02.__reserved_1 || reg_02.__reserved_2)
885 UNEXPECTED_IO_APIC();
886 }
888 /*
889 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
890 * or reg_03, but the value of reg_0[23] is read as the previous read
891 * register value, so ignore it if reg_03 == reg_0[12].
892 */
893 if (reg_01.version >= 0x20 && *(int *)&reg_03 != *(int *)&reg_02 &&
894 *(int *)&reg_03 != *(int *)&reg_01) {
895 printk(KERN_DEBUG ".... register #03: %08X\n", *(int *)&reg_03);
896 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.boot_DT);
897 if (reg_03.__reserved_1)
898 UNEXPECTED_IO_APIC();
899 }
901 printk(KERN_DEBUG ".... IRQ redirection table:\n");
903 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
904 " Stat Dest Deli Vect: \n");
906 for (i = 0; i <= reg_01.entries; i++) {
907 struct IO_APIC_route_entry entry;
909 spin_lock_irqsave(&ioapic_lock, flags);
910 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
911 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
912 spin_unlock_irqrestore(&ioapic_lock, flags);
914 printk(KERN_DEBUG " %02x %03X %02X ",
915 i,
916 entry.dest.logical.logical_dest,
917 entry.dest.physical.physical_dest
918 );
920 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
921 entry.mask,
922 entry.trigger,
923 entry.irr,
924 entry.polarity,
925 entry.delivery_status,
926 entry.dest_mode,
927 entry.delivery_mode,
928 entry.vector
929 );
930 }
931 }
932 printk(KERN_DEBUG "IRQ to pin mappings:\n");
933 for (i = 0; i < NR_IRQS; i++) {
934 struct irq_pin_list *entry = irq_2_pin + i;
935 if (entry->pin < 0)
936 continue;
937 printk(KERN_DEBUG "IRQ%d ", i);
938 for (;;) {
939 printk("-> %d:%d", entry->apic, entry->pin);
940 if (!entry->next)
941 break;
942 entry = irq_2_pin + entry->next;
943 }
944 printk("\n");
945 }
947 printk(KERN_INFO ".................................... done.\n");
948 #endif
949 }
952 #if 0 /* Maybe useful for debugging, but not currently used anywhere. */
954 static void print_APIC_bitfield (int base)
955 {
956 unsigned int v;
957 int i, j;
959 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
960 for (i = 0; i < 8; i++) {
961 v = apic_read(base + i*0x10);
962 for (j = 0; j < 32; j++) {
963 if (v & (1<<j))
964 printk("1");
965 else
966 printk("0");
967 }
968 printk("\n");
969 }
970 }
973 void /*__init*/ print_local_APIC(void * dummy)
974 {
975 unsigned int v, ver, maxlvt;
977 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
978 smp_processor_id(), hard_smp_processor_id());
979 v = apic_read(APIC_ID);
980 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
981 v = apic_read(APIC_LVR);
982 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
983 ver = GET_APIC_VERSION(v);
984 maxlvt = get_maxlvt();
986 v = apic_read(APIC_TASKPRI);
987 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
989 if (APIC_INTEGRATED(ver)) { /* !82489DX */
990 v = apic_read(APIC_ARBPRI);
991 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
992 v & APIC_ARBPRI_MASK);
993 v = apic_read(APIC_PROCPRI);
994 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
995 }
997 v = apic_read(APIC_EOI);
998 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
999 v = apic_read(APIC_RRR);
1000 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1001 v = apic_read(APIC_LDR);
1002 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1003 v = apic_read(APIC_DFR);
1004 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1005 v = apic_read(APIC_SPIV);
1006 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1008 printk(KERN_DEBUG "... APIC ISR field:\n");
1009 print_APIC_bitfield(APIC_ISR);
1010 printk(KERN_DEBUG "... APIC TMR field:\n");
1011 print_APIC_bitfield(APIC_TMR);
1012 printk(KERN_DEBUG "... APIC IRR field:\n");
1013 print_APIC_bitfield(APIC_IRR);
1015 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1016 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1017 apic_write(APIC_ESR, 0);
1018 v = apic_read(APIC_ESR);
1019 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1022 v = apic_read(APIC_ICR);
1023 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1024 v = apic_read(APIC_ICR2);
1025 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1027 v = apic_read(APIC_LVTT);
1028 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1030 if (maxlvt > 3) { /* PC is LVT#4. */
1031 v = apic_read(APIC_LVTPC);
1032 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1034 v = apic_read(APIC_LVT0);
1035 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1036 v = apic_read(APIC_LVT1);
1037 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1039 if (maxlvt > 2) { /* ERR is LVT#3. */
1040 v = apic_read(APIC_LVTERR);
1041 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1044 v = apic_read(APIC_TMICT);
1045 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1046 v = apic_read(APIC_TMCCT);
1047 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1048 v = apic_read(APIC_TDCR);
1049 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1050 printk("\n");
1053 void print_all_local_APICs (void)
1055 smp_call_function(print_local_APIC, NULL, 1, 1);
1056 print_local_APIC(NULL);
1059 void /*__init*/ print_PIC(void)
1061 extern spinlock_t i8259A_lock;
1062 unsigned int v, flags;
1064 printk(KERN_DEBUG "\nprinting PIC contents\n");
1066 spin_lock_irqsave(&i8259A_lock, flags);
1068 v = inb(0xa1) << 8 | inb(0x21);
1069 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1071 v = inb(0xa0) << 8 | inb(0x20);
1072 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1074 outb(0x0b,0xa0);
1075 outb(0x0b,0x20);
1076 v = inb(0xa0) << 8 | inb(0x20);
1077 outb(0x0a,0xa0);
1078 outb(0x0a,0x20);
1080 spin_unlock_irqrestore(&i8259A_lock, flags);
1082 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1084 v = inb(0x4d1) << 8 | inb(0x4d0);
1085 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1088 #endif /* 0 */
1091 static void __init enable_IO_APIC(void)
1093 struct IO_APIC_reg_01 reg_01;
1094 int i;
1095 unsigned long flags;
1097 for (i = 0; i < PIN_MAP_SIZE; i++) {
1098 irq_2_pin[i].pin = -1;
1099 irq_2_pin[i].next = 0;
1101 if (!pirqs_enabled)
1102 for (i = 0; i < MAX_PIRQS; i++)
1103 pirq_entries[i] = -1;
1105 /*
1106 * The number of IO-APIC IRQ registers (== #pins):
1107 */
1108 for (i = 0; i < nr_ioapics; i++) {
1109 spin_lock_irqsave(&ioapic_lock, flags);
1110 *(int *)&reg_01 = io_apic_read(i, 1);
1111 spin_unlock_irqrestore(&ioapic_lock, flags);
1112 nr_ioapic_registers[i] = reg_01.entries+1;
1115 /*
1116 * Do not trust the IO-APIC being empty at bootup
1117 */
1118 clear_IO_APIC();
1121 /*
1122 * Not an __init, needed by the reboot code
1123 */
1124 void disable_IO_APIC(void)
1126 /*
1127 * Clear the IO-APIC before rebooting:
1128 */
1129 clear_IO_APIC();
1131 disconnect_bsp_APIC();
1134 /*
1135 * function to set the IO-APIC physical IDs based on the
1136 * values stored in the MPC table.
1138 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1139 */
1141 static void __init setup_ioapic_ids_from_mpc (void)
1143 struct IO_APIC_reg_00 reg_00;
1144 unsigned long phys_id_present_map = phys_cpu_present_map;
1145 int apic;
1146 int i;
1147 unsigned char old_id;
1148 unsigned long flags;
1150 if (clustered_apic_mode)
1151 /* We don't have a good way to do this yet - hack */
1152 phys_id_present_map = (u_long) 0xf;
1153 /*
1154 * Set the IOAPIC ID to the value stored in the MPC table.
1155 */
1156 for (apic = 0; apic < nr_ioapics; apic++) {
1158 /* Read the register 0 value */
1159 spin_lock_irqsave(&ioapic_lock, flags);
1160 *(int *)&reg_00 = io_apic_read(apic, 0);
1161 spin_unlock_irqrestore(&ioapic_lock, flags);
1163 old_id = mp_ioapics[apic].mpc_apicid;
1165 if (mp_ioapics[apic].mpc_apicid >= apic_broadcast_id) {
1166 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1167 apic, mp_ioapics[apic].mpc_apicid);
1168 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1169 reg_00.ID);
1170 mp_ioapics[apic].mpc_apicid = reg_00.ID;
1173 /*
1174 * Sanity check, is the ID really free? Every APIC in a
1175 * system must have a unique ID or we get lots of nice
1176 * 'stuck on smp_invalidate_needed IPI wait' messages.
1177 * I/O APIC IDs no longer have any meaning for xAPICs and SAPICs.
1178 */
1179 if ((clustered_apic_mode != CLUSTERED_APIC_XAPIC) &&
1180 (phys_id_present_map & (1 << mp_ioapics[apic].mpc_apicid))) {
1181 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1182 apic, mp_ioapics[apic].mpc_apicid);
1183 for (i = 0; i < 0xf; i++)
1184 if (!(phys_id_present_map & (1 << i)))
1185 break;
1186 if (i >= apic_broadcast_id)
1187 panic("Max APIC ID exceeded!\n");
1188 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1189 i);
1190 phys_id_present_map |= 1 << i;
1191 mp_ioapics[apic].mpc_apicid = i;
1192 } else {
1193 printk("Setting %d in the phys_id_present_map\n", mp_ioapics[apic].mpc_apicid);
1194 phys_id_present_map |= 1 << mp_ioapics[apic].mpc_apicid;
1198 /*
1199 * We need to adjust the IRQ routing table
1200 * if the ID changed.
1201 */
1202 if (old_id != mp_ioapics[apic].mpc_apicid)
1203 for (i = 0; i < mp_irq_entries; i++)
1204 if (mp_irqs[i].mpc_dstapic == old_id)
1205 mp_irqs[i].mpc_dstapic
1206 = mp_ioapics[apic].mpc_apicid;
1208 /*
1209 * Read the right value from the MPC table and
1210 * write it into the ID register.
1211 */
1212 printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1213 mp_ioapics[apic].mpc_apicid);
1215 reg_00.ID = mp_ioapics[apic].mpc_apicid;
1216 spin_lock_irqsave(&ioapic_lock, flags);
1217 io_apic_write(apic, 0, *(int *)&reg_00);
1218 spin_unlock_irqrestore(&ioapic_lock, flags);
1220 /*
1221 * Sanity check
1222 */
1223 spin_lock_irqsave(&ioapic_lock, flags);
1224 *(int *)&reg_00 = io_apic_read(apic, 0);
1225 spin_unlock_irqrestore(&ioapic_lock, flags);
1226 if (reg_00.ID != mp_ioapics[apic].mpc_apicid)
1227 panic("could not set ID!\n");
1228 else
1229 printk(" ok.\n");
1233 /*
1234 * There is a nasty bug in some older SMP boards, their mptable lies
1235 * about the timer IRQ. We do the following to work around the situation:
1237 * - timer IRQ defaults to IO-APIC IRQ
1238 * - if this function detects that timer IRQs are defunct, then we fall
1239 * back to ISA timer IRQs
1240 */
1241 static int __init timer_irq_works(void)
1243 unsigned int t1 = jiffies;
1245 __sti();
1246 /* Let ten ticks pass... */
1247 mdelay((10 * 1000) / HZ);
1249 /*
1250 * Expect a few ticks at least, to be sure some possible
1251 * glue logic does not lock up after one or two first
1252 * ticks in a non-ExtINT mode. Also the local APIC
1253 * might have cached one ExtINT interrupt. Finally, at
1254 * least one tick may be lost due to delays.
1255 */
1256 if (jiffies - t1 > 4)
1257 return 1;
1259 return 0;
1262 static void disable_edge_ioapic_irq (unsigned int irq) { /* nothing */ }
1264 /*
1265 * Starting up a edge-triggered IO-APIC interrupt is
1266 * nasty - we need to make sure that we get the edge.
1267 * If it is already asserted for some reason, we need
1268 * return 1 to indicate that is was pending.
1270 * This is not complete - we should be able to fake
1271 * an edge even if it isn't on the 8259A...
1272 */
1274 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1276 int was_pending = 0;
1277 unsigned long flags;
1279 spin_lock_irqsave(&ioapic_lock, flags);
1280 if (irq < 16) {
1281 disable_8259A_irq(irq);
1282 if (i8259A_irq_pending(irq))
1283 was_pending = 1;
1285 __unmask_IO_APIC_irq(irq);
1286 spin_unlock_irqrestore(&ioapic_lock, flags);
1288 return was_pending;
1291 /*
1292 * Once we have recorded IRQ_PENDING already, we can mask the
1293 * interrupt for real. This prevents IRQ storms from unhandled
1294 * devices.
1295 */
1296 static void ack_edge_ioapic_irq(unsigned int irq)
1298 balance_irq(irq);
1299 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1300 == (IRQ_PENDING | IRQ_DISABLED))
1301 mask_IO_APIC_irq(irq);
1302 ack_APIC_irq();
1305 static void end_edge_ioapic_irq (unsigned int i) { /* nothing */ }
1308 /*
1309 * Level triggered interrupts can just be masked,
1310 * and shutting down and starting up the interrupt
1311 * is the same as enabling and disabling them -- except
1312 * with a startup need to return a "was pending" value.
1314 * Level triggered interrupts are special because we
1315 * do not touch any IO-APIC register while handling
1316 * them. We ack the APIC in the end-IRQ handler, not
1317 * in the start-IRQ-handler. Protection against reentrance
1318 * from the same interrupt is still provided, both by the
1319 * generic IRQ layer and by the fact that an unacked local
1320 * APIC does not accept IRQs.
1321 */
1322 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1324 unmask_IO_APIC_irq(irq);
1326 return 0; /* don't check for pending */
1329 static void mask_and_ack_level_ioapic_irq(unsigned int irq)
1331 unsigned long v;
1332 int i;
1334 balance_irq(irq);
1336 mask_IO_APIC_irq(irq);
1338 /*
1339 * It appears there is an erratum which affects at least version 0x11
1340 * of I/O APIC (that's the 82093AA and cores integrated into various
1341 * chipsets). Under certain conditions a level-triggered interrupt is
1342 * erroneously delivered as edge-triggered one but the respective IRR
1343 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1344 * message but it will never arrive and further interrupts are blocked
1345 * from the source. The exact reason is so far unknown, but the
1346 * phenomenon was observed when two consecutive interrupt requests
1347 * from a given source get delivered to the same CPU and the source is
1348 * temporarily disabled in between.
1350 * A workaround is to simulate an EOI message manually. We achieve it
1351 * by setting the trigger mode to edge and then to level when the edge
1352 * trigger mode gets detected in the TMR of a local APIC for a
1353 * level-triggered interrupt. We mask the source for the time of the
1354 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1355 * The idea is from Manfred Spraul. --macro
1356 */
1357 i = IO_APIC_VECTOR(irq);
1358 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1360 ack_APIC_irq();
1362 if (!(v & (1 << (i & 0x1f)))) {
1363 #ifdef APIC_LOCKUP_DEBUG
1364 struct irq_pin_list *entry;
1365 #endif
1367 #ifdef APIC_MISMATCH_DEBUG
1368 atomic_inc(&irq_mis_count);
1369 #endif
1370 spin_lock(&ioapic_lock);
1371 __edge_IO_APIC_irq(irq);
1372 #ifdef APIC_LOCKUP_DEBUG
1373 for (entry = irq_2_pin + irq;;) {
1374 unsigned int reg;
1376 if (entry->pin == -1)
1377 break;
1378 reg = io_apic_read(entry->apic, 0x10 + entry->pin * 2);
1379 if (reg & 0x00004000)
1380 printk(KERN_CRIT "Aieee!!! Remote IRR"
1381 " still set after unlock!\n");
1382 if (!entry->next)
1383 break;
1384 entry = irq_2_pin + entry->next;
1386 #endif
1387 __level_IO_APIC_irq(irq);
1388 spin_unlock(&ioapic_lock);
1392 static void end_level_ioapic_irq(unsigned int irq)
1394 unmask_IO_APIC_irq(irq);
1397 static inline void init_IO_APIC_traps(void)
1399 int irq;
1401 /*
1402 * NOTE! The local APIC isn't very good at handling
1403 * multiple interrupts at the same interrupt level.
1404 * As the interrupt level is determined by taking the
1405 * vector number and shifting that right by 4, we
1406 * want to spread these out a bit so that they don't
1407 * all fall in the same interrupt level.
1409 * Also, we've got to be careful not to trash gate
1410 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1411 */
1412 for (irq = 0; irq < NR_IRQS ; irq++) {
1413 if (IO_APIC_IRQ(irq) && !IO_APIC_VECTOR(irq)) {
1414 /*
1415 * Hmm.. We don't have an entry for this,
1416 * so default to an old-fashioned 8259
1417 * interrupt if we can..
1418 */
1419 if (irq < 16)
1420 make_8259A_irq(irq);
1421 else
1422 /* Strange. Oh, well.. */
1423 irq_desc[irq].handler = &no_irq_type;
1428 static void enable_lapic_irq (unsigned int irq)
1430 unsigned long v;
1432 v = apic_read(APIC_LVT0);
1433 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1436 static void disable_lapic_irq (unsigned int irq)
1438 unsigned long v;
1440 v = apic_read(APIC_LVT0);
1441 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1444 static void ack_lapic_irq (unsigned int irq)
1446 ack_APIC_irq();
1449 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1451 static struct hw_interrupt_type lapic_irq_type = {
1452 "local-APIC-edge",
1453 NULL, /* startup_irq() not used for IRQ0 */
1454 NULL, /* shutdown_irq() not used for IRQ0 */
1455 enable_lapic_irq,
1456 disable_lapic_irq,
1457 ack_lapic_irq,
1458 end_lapic_irq
1459 };
1461 /*
1462 * This looks a bit hackish but it's about the only one way of sending
1463 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1464 * not support the ExtINT mode, unfortunately. We need to send these
1465 * cycles as some i82489DX-based boards have glue logic that keeps the
1466 * 8259A interrupt line asserted until INTA. --macro
1467 */
1468 static inline void unlock_ExtINT_logic(void)
1470 int pin, i;
1471 struct IO_APIC_route_entry entry0, entry1;
1472 unsigned char save_control, save_freq_select;
1473 unsigned long flags;
1475 pin = find_isa_irq_pin(8, mp_INT);
1476 if (pin == -1)
1477 return;
1479 spin_lock_irqsave(&ioapic_lock, flags);
1480 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1481 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1482 spin_unlock_irqrestore(&ioapic_lock, flags);
1483 clear_IO_APIC_pin(0, pin);
1485 memset(&entry1, 0, sizeof(entry1));
1487 entry1.dest_mode = 0; /* physical delivery */
1488 entry1.mask = 0; /* unmask IRQ now */
1489 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1490 entry1.delivery_mode = dest_ExtINT;
1491 entry1.polarity = entry0.polarity;
1492 entry1.trigger = 0;
1493 entry1.vector = 0;
1495 spin_lock_irqsave(&ioapic_lock, flags);
1496 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1497 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1498 spin_unlock_irqrestore(&ioapic_lock, flags);
1500 save_control = CMOS_READ(RTC_CONTROL);
1501 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1502 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1503 RTC_FREQ_SELECT);
1504 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1506 i = 100;
1507 while (i-- > 0) {
1508 mdelay(10);
1509 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1510 i -= 10;
1513 CMOS_WRITE(save_control, RTC_CONTROL);
1514 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1515 clear_IO_APIC_pin(0, pin);
1517 spin_lock_irqsave(&ioapic_lock, flags);
1518 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1519 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1520 spin_unlock_irqrestore(&ioapic_lock, flags);
1523 /*
1524 * This code may look a bit paranoid, but it's supposed to cooperate with
1525 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1526 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1527 * fanatically on his truly buggy board.
1528 */
1529 static inline void check_timer(void)
1531 extern int timer_ack;
1532 int pin1, pin2;
1533 int vector;
1535 /*
1536 * get/set the timer IRQ vector:
1537 */
1538 disable_8259A_irq(0);
1539 vector = assign_irq_vector(0);
1540 set_intr_gate(vector, interrupt[0]);
1542 /*
1543 * Subtle, code in do_timer_interrupt() expects an AEOI
1544 * mode for the 8259A whenever interrupts are routed
1545 * through I/O APICs. Also IRQ0 has to be enabled in
1546 * the 8259A which implies the virtual wire has to be
1547 * disabled in the local APIC.
1548 */
1549 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1550 init_8259A(1);
1551 timer_ack = 1;
1552 enable_8259A_irq(0);
1554 pin1 = find_isa_irq_pin(0, mp_INT);
1555 pin2 = find_isa_irq_pin(0, mp_ExtINT);
1557 printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1559 if (pin1 != -1) {
1560 /*
1561 * Ok, does IRQ0 through the IOAPIC work?
1562 */
1563 unmask_IO_APIC_irq(0);
1564 if (timer_irq_works())
1565 return;
1566 clear_IO_APIC_pin(0, pin1);
1567 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1570 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1571 if (pin2 != -1) {
1572 printk("\n..... (found pin %d) ...", pin2);
1573 /*
1574 * legacy devices should be connected to IO APIC #0
1575 */
1576 setup_ExtINT_IRQ0_pin(pin2, vector);
1577 if (timer_irq_works()) {
1578 printk("works.\n");
1579 if (pin1 != -1)
1580 replace_pin_at_irq(0, 0, pin1, 0, pin2);
1581 else
1582 add_pin_to_irq(0, 0, pin2);
1583 return;
1585 /*
1586 * Cleanup, just in case ...
1587 */
1588 clear_IO_APIC_pin(0, pin2);
1590 printk(" failed.\n");
1592 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1594 disable_8259A_irq(0);
1595 irq_desc[0].handler = &lapic_irq_type;
1596 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1597 enable_8259A_irq(0);
1599 if (timer_irq_works()) {
1600 printk(" works.\n");
1601 return;
1603 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1604 printk(" failed.\n");
1606 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1608 init_8259A(0);
1609 make_8259A_irq(0);
1610 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1612 unlock_ExtINT_logic();
1614 if (timer_irq_works()) {
1615 printk(" works.\n");
1616 return;
1618 printk(" failed :(.\n");
1619 panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
1622 /*
1624 * IRQ's that are handled by the old PIC in all cases:
1625 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1626 * Linux doesn't really care, as it's not actually used
1627 * for any interrupt handling anyway.
1628 * - There used to be IRQ13 here as well, but all
1629 * MPS-compliant must not use it for FPU coupling and we
1630 * want to use exception 16 anyway. And there are
1631 * systems who connect it to an I/O APIC for other uses.
1632 * Thus we don't mark it special any longer.
1634 * Additionally, something is definitely wrong with irq9
1635 * on PIIX4 boards.
1636 */
1637 #define PIC_IRQS (1<<2)
1639 void __init setup_IO_APIC(void)
1641 enable_IO_APIC();
1643 io_apic_irqs = ~PIC_IRQS;
1644 printk("ENABLING IO-APIC IRQs\n");
1646 /*
1647 * Set up IO-APIC IRQ routing.
1648 */
1649 if (!acpi_ioapic)
1650 setup_ioapic_ids_from_mpc();
1651 sync_Arb_IDs();
1652 setup_IO_APIC_irqs();
1653 init_IO_APIC_traps();
1654 check_timer();
1655 if (!acpi_ioapic)
1656 print_IO_APIC();
1659 #endif /* CONFIG_X86_IO_APIC */
1663 /* --------------------------------------------------------------------------
1664 ACPI-based IOAPIC Configuration
1665 -------------------------------------------------------------------------- */
1667 #ifdef CONFIG_ACPI_BOOT
1669 #define IO_APIC_MAX_ID 15
1671 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1673 struct IO_APIC_reg_00 reg_00;
1674 static unsigned long apic_id_map = 0;
1675 unsigned long flags;
1676 int i = 0;
1678 /*
1679 * The P4 platform supports up to 256 APIC IDs on two separate APIC
1680 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1681 * supports up to 16 on one shared APIC bus.
1683 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1684 * advantage of new APIC bus architecture.
1685 */
1687 if (!apic_id_map)
1688 apic_id_map = phys_cpu_present_map;
1690 spin_lock_irqsave(&ioapic_lock, flags);
1691 *(int *)&reg_00 = io_apic_read(ioapic, 0);
1692 spin_unlock_irqrestore(&ioapic_lock, flags);
1694 if (apic_id >= IO_APIC_MAX_ID) {
1695 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1696 "%d\n", ioapic, apic_id, reg_00.ID);
1697 apic_id = reg_00.ID;
1700 /* XAPICs do not need unique IDs */
1701 if (clustered_apic_mode == CLUSTERED_APIC_XAPIC){
1702 printk(KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n",
1703 ioapic, apic_id);
1704 return apic_id;
1707 /*
1708 * Every APIC in a system must have a unique ID or we get lots of nice
1709 * 'stuck on smp_invalidate_needed IPI wait' messages.
1710 */
1711 if (apic_id_map & (1 << apic_id)) {
1713 for (i = 0; i < IO_APIC_MAX_ID; i++) {
1714 if (!(apic_id_map & (1 << i)))
1715 break;
1718 if (i == IO_APIC_MAX_ID)
1719 panic("Max apic_id exceeded!\n");
1721 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1722 "trying %d\n", ioapic, apic_id, i);
1724 apic_id = i;
1727 apic_id_map |= (1 << apic_id);
1729 if (reg_00.ID != apic_id) {
1730 reg_00.ID = apic_id;
1732 spin_lock_irqsave(&ioapic_lock, flags);
1733 io_apic_write(ioapic, 0, *(int *)&reg_00);
1734 *(int *)&reg_00 = io_apic_read(ioapic, 0);
1735 spin_unlock_irqrestore(&ioapic_lock, flags);
1737 /* Sanity check */
1738 if (reg_00.ID != apic_id)
1739 panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
1742 printk(KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
1744 return apic_id;
1748 int __init io_apic_get_version (int ioapic)
1750 struct IO_APIC_reg_01 reg_01;
1751 unsigned long flags;
1753 spin_lock_irqsave(&ioapic_lock, flags);
1754 *(int *)&reg_01 = io_apic_read(ioapic, 1);
1755 spin_unlock_irqrestore(&ioapic_lock, flags);
1757 return reg_01.version;
1761 int __init io_apic_get_redir_entries (int ioapic)
1763 struct IO_APIC_reg_01 reg_01;
1764 unsigned long flags;
1766 spin_lock_irqsave(&ioapic_lock, flags);
1767 *(int *)&reg_01 = io_apic_read(ioapic, 1);
1768 spin_unlock_irqrestore(&ioapic_lock, flags);
1770 return reg_01.entries;
1774 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1776 struct IO_APIC_route_entry entry;
1777 unsigned long flags;
1779 if (!IO_APIC_IRQ(irq)) {
1780 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0/n",
1781 ioapic);
1782 return -EINVAL;
1785 /*
1786 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1787 * Note that we mask (disable) IRQs now -- these get enabled when the
1788 * corresponding device driver registers for this IRQ.
1789 */
1791 memset(&entry,0,sizeof(entry));
1793 entry.delivery_mode = dest_LowestPrio;
1794 entry.dest_mode = INT_DELIVERY_MODE;
1795 entry.dest.logical.logical_dest = target_cpus();
1796 entry.mask = 1; /* Disabled (masked) */
1797 entry.trigger = edge_level;
1798 entry.polarity = active_high_low;
1800 /*
1801 * IRQs < 16 are already in the irq_2_pin[] map
1802 */
1803 if (irq >= 16)
1804 add_pin_to_irq(irq, ioapic, pin);
1806 entry.vector = assign_irq_vector(irq);
1808 printk(KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1809 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1810 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, edge_level, active_high_low);
1812 if (edge_level) {
1813 irq_desc[irq].handler = &ioapic_level_irq_type;
1814 } else {
1815 irq_desc[irq].handler = &ioapic_edge_irq_type;
1818 set_intr_gate(entry.vector, interrupt[irq]);
1820 if (!ioapic && (irq < 16))
1821 disable_8259A_irq(irq);
1823 spin_lock_irqsave(&ioapic_lock, flags);
1824 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1825 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1826 spin_unlock_irqrestore(&ioapic_lock, flags);
1828 return 0;
1831 #endif /*CONFIG_ACPI_BOOT*/
1833 /* opt_leveltrigger, opt_edgetrigger: Force an IO-APIC-routed IRQ to be */
1834 /* level- or edge-triggered. */
1835 /* Example: 'leveltrigger=4,5,6,20 edgetrigger=21'. */
1836 static char opt_leveltrigger[30] = "", opt_edgetrigger[30] = "";
1837 string_param("leveltrigger", opt_leveltrigger);
1838 string_param("edgetrigger", opt_edgetrigger);
1840 static int __init ioapic_trigger_setup(void)
1842 char *p;
1843 irq_desc_t *desc;
1844 long irq;
1846 p = opt_leveltrigger;
1847 while ( *p != '\0' )
1849 irq = simple_strtol(p, &p, 10);
1850 if ( (irq <= 0) || (irq >= NR_IRQS) )
1852 printk("IRQ '%ld' out of range in level-trigger list '%s'\n",
1853 irq, opt_leveltrigger);
1854 break;
1857 printk("Forcing IRQ %ld to level-trigger: ", irq);
1859 desc = &irq_desc[irq];
1860 spin_lock_irq(&desc->lock);
1862 if ( desc->handler == &ioapic_level_irq_type )
1864 printk("already level-triggered (no force applied).\n");
1866 else if ( desc->handler != &ioapic_edge_irq_type )
1868 printk("cannot force (can only force IO-APIC-edge IRQs).\n");
1870 else
1872 desc->handler = &ioapic_level_irq_type;
1873 __mask_IO_APIC_irq(irq);
1874 __level_IO_APIC_irq(irq);
1875 printk("done.\n");
1878 spin_unlock_irq(&desc->lock);
1880 if ( *p == '\0' )
1881 break;
1883 if ( *p != ',' )
1885 printk("Unexpected character '%c' in level-trigger list '%s'\n",
1886 *p, opt_leveltrigger);
1887 break;
1890 p++;
1893 p = opt_edgetrigger;
1894 while ( *p != '\0' )
1896 irq = simple_strtol(p, &p, 10);
1897 if ( (irq <= 0) || (irq >= NR_IRQS) )
1899 printk("IRQ '%ld' out of range in edge-trigger list '%s'\n",
1900 irq, opt_edgetrigger);
1901 break;
1904 printk("Forcing IRQ %ld to edge-trigger: ", irq);
1906 desc = &irq_desc[irq];
1907 spin_lock_irq(&desc->lock);
1909 if ( desc->handler == &ioapic_edge_irq_type )
1911 printk("already edge-triggered (no force applied).\n");
1913 else if ( desc->handler != &ioapic_level_irq_type )
1915 printk("cannot force (can only force IO-APIC-level IRQs).\n");
1917 else
1919 desc->handler = &ioapic_edge_irq_type;
1920 __edge_IO_APIC_irq(irq);
1921 desc->status |= IRQ_PENDING; /* may have lost a masked edge */
1922 printk("done.\n");
1925 spin_unlock_irq(&desc->lock);
1927 if ( *p == '\0' )
1928 break;
1930 if ( *p != ',' )
1932 printk("Unexpected character '%c' in edge-trigger list '%s'\n",
1933 *p, opt_edgetrigger);
1934 break;
1937 p++;
1940 return 0;
1943 __initcall(ioapic_trigger_setup);