debuggers.hg

view xen/arch/x86/pci-irq.c @ 3674:fb875591fd72

bitkeeper revision 1.1159.223.63 (42028527-fv-d9BM0_LRp8UKGP19gQ)

Fix NMI deferral.
Signed-off-by: keir.fraser@cl.cam.ac.uk
author kaf24@scramble.cl.cam.ac.uk
date Thu Feb 03 20:10:15 2005 +0000 (2005-02-03)
parents 4f0616f9dffe
children 0a4b76b6b5a0
line source
1 /*
2 * Low-Level PCI Support for PC -- Routing of Interrupts
3 *
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
5 */
7 #include <xen/config.h>
8 #include <xen/types.h>
9 #include <xen/kernel.h>
10 #include <xen/pci.h>
11 #include <xen/init.h>
12 #include <xen/slab.h>
13 #include <xen/irq.h>
14 #include <asm/io.h>
15 #include <asm/smp.h>
16 #include <asm/io_apic.h>
17 #include "pci-x86.h"
19 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
20 #define PIRQ_VERSION 0x0100
22 int broken_hp_bios_irq9;
24 static struct irq_routing_table *pirq_table;
26 /*
27 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
28 * Avoid using: 13, 14 and 15 (FP error and IDE).
29 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
30 */
31 unsigned int pcibios_irq_mask = 0xfff8;
33 static int pirq_penalty[16] = {
34 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
35 0, 0, 0, 0, 1000, 100000, 100000, 100000
36 };
38 struct irq_router {
39 char *name;
40 u16 vendor, device;
41 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
42 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new);
43 };
45 struct irq_router_handler {
46 u16 vendor;
47 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
48 };
50 /*
51 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
52 */
54 static struct irq_routing_table * __init pirq_find_routing_table(void)
55 {
56 u8 *addr;
57 struct irq_routing_table *rt;
58 int i;
59 u8 sum;
61 for(addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
62 rt = (struct irq_routing_table *) addr;
63 if (rt->signature != PIRQ_SIGNATURE ||
64 rt->version != PIRQ_VERSION ||
65 rt->size % 16 ||
66 rt->size < sizeof(struct irq_routing_table))
67 continue;
68 sum = 0;
69 for(i=0; i<rt->size; i++)
70 sum += addr[i];
71 if (!sum) {
72 DBG("PCI: Interrupt Routing Table found at 0x%p\n", rt);
73 return rt;
74 }
75 }
76 return NULL;
77 }
79 /*
80 * If we have a IRQ routing table, use it to search for peer host
81 * bridges. It's a gross hack, but since there are no other known
82 * ways how to get a list of buses, we have to go this way.
83 */
85 static void __init pirq_peer_trick(void)
86 {
87 struct irq_routing_table *rt = pirq_table;
88 u8 busmap[256];
89 int i;
90 struct irq_info *e;
92 memset(busmap, 0, sizeof(busmap));
93 for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
94 e = &rt->slots[i];
95 #ifdef DEBUG
96 {
97 int j;
98 DBG("%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
99 for(j=0; j<4; j++)
100 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
101 DBG("\n");
102 }
103 #endif
104 busmap[e->bus] = 1;
105 }
106 for(i=1; i<256; i++)
107 /*
108 * It might be a secondary bus, but in this case its parent is already
109 * known (ascending bus order) and therefore pci_scan_bus returns immediately.
110 */
111 if (busmap[i] && pci_scan_bus(i, pci_root_bus->ops, NULL))
112 printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i);
113 pcibios_last_bus = -1;
114 }
116 /*
117 * Code for querying and setting of IRQ routes on various interrupt routers.
118 */
120 void eisa_set_level_irq(unsigned int irq)
121 {
122 unsigned char mask = 1 << (irq & 7);
123 unsigned int port = 0x4d0 + (irq >> 3);
124 unsigned char val = inb(port);
126 if (!(val & mask)) {
127 DBG(" -> edge");
128 outb(val | mask, port);
129 }
130 }
132 /*
133 * Common IRQ routing practice: nybbles in config space,
134 * offset by some magic constant.
135 */
136 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
137 {
138 u8 x;
139 unsigned reg = offset + (nr >> 1);
141 pci_read_config_byte(router, reg, &x);
142 return (nr & 1) ? (x >> 4) : (x & 0xf);
143 }
145 static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val)
146 {
147 u8 x;
148 unsigned reg = offset + (nr >> 1);
150 pci_read_config_byte(router, reg, &x);
151 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
152 pci_write_config_byte(router, reg, x);
153 }
155 /*
156 * ALI pirq entries are damn ugly, and completely undocumented.
157 * This has been figured out from pirq tables, and it's not a pretty
158 * picture.
159 */
160 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
161 {
162 static unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
164 return irqmap[read_config_nybble(router, 0x48, pirq-1)];
165 }
167 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
168 {
169 static unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
170 unsigned int val = irqmap[irq];
172 if (val) {
173 write_config_nybble(router, 0x48, pirq-1, val);
174 return 1;
175 }
176 return 0;
177 }
179 /*
180 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
181 * just a pointer to the config space.
182 */
183 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
184 {
185 u8 x;
187 pci_read_config_byte(router, pirq, &x);
188 return (x < 16) ? x : 0;
189 }
191 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
192 {
193 pci_write_config_byte(router, pirq, irq);
194 return 1;
195 }
197 /*
198 * The VIA pirq rules are nibble-based, like ALI,
199 * but without the ugly irq number munging.
200 * However, PIRQD is in the upper instead of lower nibble.
201 */
202 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
203 {
204 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
205 }
207 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
208 {
209 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
210 return 1;
211 }
213 /*
214 * ITE 8330G pirq rules are nibble-based
215 * FIXME: pirqmap may be { 1, 0, 3, 2 },
216 * 2+3 are both mapped to irq 9 on my system
217 */
218 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
219 {
220 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
221 return read_config_nybble(router,0x43, pirqmap[pirq-1]);
222 }
224 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
225 {
226 static unsigned char pirqmap[4] = { 1, 0, 2, 3 };
227 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
228 return 1;
229 }
231 /*
232 * OPTI: high four bits are nibble pointer..
233 * I wonder what the low bits do?
234 */
235 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
236 {
237 return read_config_nybble(router, 0xb8, pirq >> 4);
238 }
240 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
241 {
242 write_config_nybble(router, 0xb8, pirq >> 4, irq);
243 return 1;
244 }
246 /*
247 * Cyrix: nibble offset 0x5C
248 */
249 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
250 {
251 return read_config_nybble(router, 0x5C, (pirq-1)^1);
252 }
254 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
255 {
256 write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
257 return 1;
258 }
260 /*
261 * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
262 * We have to deal with the following issues here:
263 * - vendors have different ideas about the meaning of link values
264 * - some onboard devices (integrated in the chipset) have special
265 * links and are thus routed differently (i.e. not via PCI INTA-INTD)
266 * - different revision of the router have a different layout for
267 * the routing registers, particularly for the onchip devices
268 *
269 * For all routing registers the common thing is we have one byte
270 * per routeable link which is defined as:
271 * bit 7 IRQ mapping enabled (0) or disabled (1)
272 * bits [6:4] reserved (sometimes used for onchip devices)
273 * bits [3:0] IRQ to map to
274 * allowed: 3-7, 9-12, 14-15
275 * reserved: 0, 1, 2, 8, 13
276 *
277 * The config-space registers located at 0x41/0x42/0x43/0x44 are
278 * always used to route the normal PCI INT A/B/C/D respectively.
279 * Apparently there are systems implementing PCI routing table using
280 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
281 * We try our best to handle both link mappings.
282 *
283 * Currently (2003-05-21) it appears most SiS chipsets follow the
284 * definition of routing registers from the SiS-5595 southbridge.
285 * According to the SiS 5595 datasheets the revision id's of the
286 * router (ISA-bridge) should be 0x01 or 0xb0.
287 *
288 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
289 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
290 * They seem to work with the current routing code. However there is
291 * some concern because of the two USB-OHCI HCs (original SiS 5595
292 * had only one). YMMV.
293 *
294 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
295 *
296 * 0x61: IDEIRQ:
297 * bits [6:5] must be written 01
298 * bit 4 channel-select primary (0), secondary (1)
299 *
300 * 0x62: USBIRQ:
301 * bit 6 OHCI function disabled (0), enabled (1)
302 *
303 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
304 *
305 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
306 *
307 * We support USBIRQ (in addition to INTA-INTD) and keep the
308 * IDE, ACPI and DAQ routing untouched as set by the BIOS.
309 *
310 * Currently the only reported exception is the new SiS 65x chipset
311 * which includes the SiS 69x southbridge. Here we have the 85C503
312 * router revision 0x04 and there are changes in the register layout
313 * mostly related to the different USB HCs with USB 2.0 support.
314 *
315 * Onchip routing for router rev-id 0x04 (try-and-error observation)
316 *
317 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
318 * bit 6-4 are probably unused, not like 5595
319 */
321 #define PIRQ_SIS_IRQ_MASK 0x0f
322 #define PIRQ_SIS_IRQ_DISABLE 0x80
323 #define PIRQ_SIS_USB_ENABLE 0x40
324 #define PIRQ_SIS_DETECT_REGISTER 0x40
326 /* return value:
327 * -1 on error
328 * 0 for PCI INTA-INTD
329 * 0 or enable bit mask to check or set for onchip functions
330 */
331 static inline int pirq_sis5595_onchip(int pirq, int *reg)
332 {
333 int ret = -1;
335 *reg = pirq;
336 switch(pirq) {
337 case 0x01:
338 case 0x02:
339 case 0x03:
340 case 0x04:
341 *reg += 0x40;
342 case 0x41:
343 case 0x42:
344 case 0x43:
345 case 0x44:
346 ret = 0;
347 break;
349 case 0x62:
350 ret = PIRQ_SIS_USB_ENABLE; /* documented for 5595 */
351 break;
353 case 0x61:
354 case 0x6a:
355 case 0x7e:
356 printk(KERN_INFO "SiS pirq: IDE/ACPI/DAQ mapping not implemented: (%u)\n",
357 (unsigned) pirq);
358 /* fall thru */
359 default:
360 printk(KERN_INFO "SiS router unknown request: (%u)\n",
361 (unsigned) pirq);
362 break;
363 }
364 return ret;
365 }
367 /* return value:
368 * -1 on error
369 * 0 for PCI INTA-INTD
370 * 0 or enable bit mask to check or set for onchip functions
371 */
372 static inline int pirq_sis96x_onchip(int pirq, int *reg)
373 {
374 int ret = -1;
376 *reg = pirq;
377 switch(pirq) {
378 case 0x01:
379 case 0x02:
380 case 0x03:
381 case 0x04:
382 *reg += 0x40;
383 case 0x41:
384 case 0x42:
385 case 0x43:
386 case 0x44:
387 case 0x60:
388 case 0x61:
389 case 0x62:
390 case 0x63:
391 ret = 0;
392 break;
394 default:
395 printk(KERN_INFO "SiS router unknown request: (%u)\n",
396 (unsigned) pirq);
397 break;
398 }
399 return ret;
400 }
403 static int pirq_sis5595_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
404 {
405 u8 x;
406 int reg, check;
408 check = pirq_sis5595_onchip(pirq, &reg);
409 if (check < 0)
410 return 0;
412 pci_read_config_byte(router, reg, &x);
413 if (check != 0 && !(x & check))
414 return 0;
416 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
417 }
419 static int pirq_sis96x_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
420 {
421 u8 x;
422 int reg, check;
424 check = pirq_sis96x_onchip(pirq, &reg);
425 if (check < 0)
426 return 0;
428 pci_read_config_byte(router, reg, &x);
429 if (check != 0 && !(x & check))
430 return 0;
432 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
433 }
435 static int pirq_sis5595_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
436 {
437 u8 x;
438 int reg, set;
440 set = pirq_sis5595_onchip(pirq, &reg);
441 if (set < 0)
442 return 0;
444 x = (irq & PIRQ_SIS_IRQ_MASK);
445 if (x == 0)
446 x = PIRQ_SIS_IRQ_DISABLE;
447 else
448 x |= set;
450 pci_write_config_byte(router, reg, x);
452 return 1;
453 }
455 static int pirq_sis96x_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
456 {
457 u8 x;
458 int reg, set;
460 set = pirq_sis96x_onchip(pirq, &reg);
461 if (set < 0)
462 return 0;
464 x = (irq & PIRQ_SIS_IRQ_MASK);
465 if (x == 0)
466 x = PIRQ_SIS_IRQ_DISABLE;
467 else
468 x |= set;
470 pci_write_config_byte(router, reg, x);
472 return 1;
473 }
476 /*
477 * VLSI: nibble offset 0x74 - educated guess due to routing table and
478 * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
479 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
480 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
481 * for the busbridge to the docking station.
482 */
484 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
485 {
486 if (pirq > 8) {
487 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
488 return 0;
489 }
490 return read_config_nybble(router, 0x74, pirq-1);
491 }
493 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
494 {
495 if (pirq > 8) {
496 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq);
497 return 0;
498 }
499 write_config_nybble(router, 0x74, pirq-1, irq);
500 return 1;
501 }
503 /*
504 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
505 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
506 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
507 * register is a straight binary coding of desired PIC IRQ (low nibble).
508 *
509 * The 'link' value in the PIRQ table is already in the correct format
510 * for the Index register. There are some special index values:
511 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
512 * and 0x03 for SMBus.
513 */
514 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
515 {
516 outb_p(pirq, 0xc00);
517 return inb(0xc01) & 0xf;
518 }
520 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
521 {
522 outb_p(pirq, 0xc00);
523 outb_p(irq, 0xc01);
524 return 1;
525 }
527 /* Support for AMD756 PCI IRQ Routing
528 * Jhon H. Caicedo <jhcaiced@osso.org.co>
529 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
530 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
531 * The AMD756 pirq rules are nibble-based
532 * offset 0x56 0-3 PIRQA 4-7 PIRQB
533 * offset 0x57 0-3 PIRQC 4-7 PIRQD
534 */
535 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
536 {
537 u8 irq;
538 irq = 0;
539 if (pirq <= 4)
540 {
541 irq = read_config_nybble(router, 0x56, pirq - 1);
542 }
543 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n",
544 dev->vendor, dev->device, pirq, irq);
545 return irq;
546 }
548 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
549 {
550 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n",
551 dev->vendor, dev->device, pirq, irq);
552 if (pirq <= 4)
553 {
554 write_config_nybble(router, 0x56, pirq - 1, irq);
555 }
556 return 1;
557 }
559 #ifdef CONFIG_PCI_BIOS
561 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
562 {
563 struct pci_dev *bridge;
564 int pin = pci_get_interrupt_pin(dev, &bridge);
565 return pcibios_set_irq_routing(bridge, pin, irq);
566 }
568 #endif
571 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
572 {
573 /* We must not touch 440GX even if we have tables. 440GX has
574 different IRQ routing weirdness */
575 if(pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0, NULL) ||
576 pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2, NULL))
577 return 0;
578 switch(device)
579 {
580 case PCI_DEVICE_ID_INTEL_82371FB_0:
581 case PCI_DEVICE_ID_INTEL_82371SB_0:
582 case PCI_DEVICE_ID_INTEL_82371AB_0:
583 case PCI_DEVICE_ID_INTEL_82371MX:
584 case PCI_DEVICE_ID_INTEL_82443MX_0:
585 case PCI_DEVICE_ID_INTEL_82801AA_0:
586 case PCI_DEVICE_ID_INTEL_82801AB_0:
587 case PCI_DEVICE_ID_INTEL_82801BA_0:
588 case PCI_DEVICE_ID_INTEL_82801BA_10:
589 case PCI_DEVICE_ID_INTEL_82801CA_0:
590 case PCI_DEVICE_ID_INTEL_82801CA_12:
591 case PCI_DEVICE_ID_INTEL_82801DB_0:
592 case PCI_DEVICE_ID_INTEL_82801E_0:
593 case PCI_DEVICE_ID_INTEL_82801EB_0:
594 case PCI_DEVICE_ID_INTEL_ESB_0:
595 case PCI_DEVICE_ID_INTEL_ICH6_0:
596 r->name = "PIIX/ICH";
597 r->get = pirq_piix_get;
598 r->set = pirq_piix_set;
599 return 1;
600 }
601 return 0;
602 }
604 static __init int via_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
605 {
606 /* FIXME: We should move some of the quirk fixup stuff here */
607 switch(device)
608 {
609 case PCI_DEVICE_ID_VIA_82C586_0:
610 case PCI_DEVICE_ID_VIA_82C596:
611 case PCI_DEVICE_ID_VIA_82C686:
612 case PCI_DEVICE_ID_VIA_8231:
613 /* FIXME: add new ones for 8233/5 */
614 r->name = "VIA";
615 r->get = pirq_via_get;
616 r->set = pirq_via_set;
617 return 1;
618 }
619 return 0;
620 }
622 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
623 {
624 switch(device)
625 {
626 case PCI_DEVICE_ID_VLSI_82C534:
627 r->name = "VLSI 82C534";
628 r->get = pirq_vlsi_get;
629 r->set = pirq_vlsi_set;
630 return 1;
631 }
632 return 0;
633 }
636 static __init int serverworks_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
637 {
638 switch(device)
639 {
640 case PCI_DEVICE_ID_SERVERWORKS_OSB4:
641 case PCI_DEVICE_ID_SERVERWORKS_CSB5:
642 r->name = "ServerWorks";
643 r->get = pirq_serverworks_get;
644 r->set = pirq_serverworks_set;
645 return 1;
646 }
647 return 0;
648 }
650 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
651 {
652 u8 reg;
653 u16 devid;
655 if (device != PCI_DEVICE_ID_SI_503)
656 return 0;
658 /*
659 * In case of SiS south bridge, we need to detect the two
660 * kinds of routing tables we have seen so far (5595 and 96x).
661 * Since the maintain the same device ID, we need to do poke
662 * the PCI configuration space to find the router type we are
663 * dealing with.
664 */
666 /*
667 * Factoid: writing bit6 of register 0x40 of the router config space
668 * will make the SB to show up 0x096x inside the device id. Note,
669 * we need to restore register 0x40 after the device id poke.
670 */
672 pci_read_config_byte(router, PIRQ_SIS_DETECT_REGISTER, &reg);
673 pci_write_config_byte(router, PIRQ_SIS_DETECT_REGISTER, reg | (1 << 6));
674 pci_read_config_word(router, PCI_DEVICE_ID, &devid);
675 pci_write_config_byte(router, PIRQ_SIS_DETECT_REGISTER, reg);
677 if ((devid & 0xfff0) == 0x0960) {
678 r->name = "SIS96x";
679 r->get = pirq_sis96x_get;
680 r->set = pirq_sis96x_set;
681 DBG("PCI: Detecting SiS router at %02x:%02x : SiS096x detected\n",
682 rt->rtr_bus, rt->rtr_devfn);
683 } else {
684 r->name = "SIS5595";
685 r->get = pirq_sis5595_get;
686 r->set = pirq_sis5595_set;
687 DBG("PCI: Detecting SiS router at %02x:%02x : SiS5595 detected\n",
688 rt->rtr_bus, rt->rtr_devfn);
689 }
690 return 1;
691 }
693 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
694 {
695 switch(device)
696 {
697 case PCI_DEVICE_ID_CYRIX_5520:
698 r->name = "NatSemi";
699 r->get = pirq_cyrix_get;
700 r->set = pirq_cyrix_set;
701 return 1;
702 }
703 return 0;
704 }
706 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
707 {
708 switch(device)
709 {
710 case PCI_DEVICE_ID_OPTI_82C700:
711 r->name = "OPTI";
712 r->get = pirq_opti_get;
713 r->set = pirq_opti_set;
714 return 1;
715 }
716 return 0;
717 }
719 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
720 {
721 switch(device)
722 {
723 case PCI_DEVICE_ID_ITE_IT8330G_0:
724 r->name = "ITE";
725 r->get = pirq_ite_get;
726 r->set = pirq_ite_set;
727 return 1;
728 }
729 return 0;
730 }
732 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
733 {
734 switch(device)
735 {
736 case PCI_DEVICE_ID_AL_M1533:
737 r->name = "ALI";
738 r->get = pirq_ali_get;
739 r->set = pirq_ali_set;
740 return 1;
741 /* Should add 156x some day */
742 }
743 return 0;
744 }
746 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
747 {
748 switch(device)
749 {
750 case PCI_DEVICE_ID_AMD_VIPER_740B:
751 r->name = "AMD756";
752 break;
753 case PCI_DEVICE_ID_AMD_VIPER_7413:
754 r->name = "AMD766";
755 break;
756 case PCI_DEVICE_ID_AMD_VIPER_7443:
757 r->name = "AMD768";
758 break;
759 default:
760 return 0;
761 }
762 r->get = pirq_amd756_get;
763 r->set = pirq_amd756_set;
764 return 1;
765 }
767 static __initdata struct irq_router_handler pirq_routers[] = {
768 { PCI_VENDOR_ID_INTEL, intel_router_probe },
769 { PCI_VENDOR_ID_AL, ali_router_probe },
770 { PCI_VENDOR_ID_ITE, ite_router_probe },
771 { PCI_VENDOR_ID_VIA, via_router_probe },
772 { PCI_VENDOR_ID_OPTI, opti_router_probe },
773 { PCI_VENDOR_ID_SI, sis_router_probe },
774 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
775 { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
776 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
777 { PCI_VENDOR_ID_AMD, amd_router_probe },
778 /* Someone with docs needs to add the ATI Radeon IGP */
779 { 0, NULL }
780 };
781 static struct irq_router pirq_router;
782 static struct pci_dev *pirq_router_dev;
784 /*
785 * FIXME: should we have an option to say "generic for
786 * chipset" ?
787 */
789 static void __init pirq_find_router(struct irq_router *r)
790 {
791 struct irq_routing_table *rt = pirq_table;
792 struct irq_router_handler *h;
794 #ifdef CONFIG_PCI_BIOS
795 if (!rt->signature) {
796 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
797 r->set = pirq_bios_set;
798 r->name = "BIOS";
799 return;
800 }
801 #endif
803 /* Default unless a driver reloads it */
804 r->name = "default";
805 r->get = NULL;
806 r->set = NULL;
808 DBG("PCI: Attempting to find IRQ router for %04x:%04x\n",
809 rt->rtr_vendor, rt->rtr_device);
811 pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn);
812 if (!pirq_router_dev) {
813 DBG("PCI: Interrupt router not found at %02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
814 return;
815 }
817 for( h = pirq_routers; h->vendor; h++) {
818 /* First look for a router match */
819 if (rt->rtr_vendor == h->vendor && h->probe(r, pirq_router_dev, rt->rtr_device))
820 break;
821 /* Fall back to a device match */
822 if (pirq_router_dev->vendor == h->vendor && h->probe(r, pirq_router_dev, pirq_router_dev->device))
823 break;
824 }
825 printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n",
826 pirq_router.name,
827 pirq_router_dev->vendor,
828 pirq_router_dev->device,
829 pirq_router_dev->slot_name);
830 }
832 static struct irq_info *pirq_get_info(struct pci_dev *dev)
833 {
834 struct irq_routing_table *rt = pirq_table;
835 int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info);
836 struct irq_info *info;
838 for (info = rt->slots; entries--; info++)
839 if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
840 return info;
841 return NULL;
842 }
844 static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
845 {
846 u8 pin;
847 struct irq_info *info;
848 int i, pirq, newirq;
849 int irq = 0;
850 u32 mask;
851 struct irq_router *r = &pirq_router;
852 struct pci_dev *dev2;
853 char *msg = NULL;
855 if (!pirq_table)
856 return 0;
858 /* Find IRQ routing entry */
859 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
860 if (!pin) {
861 DBG(" -> no interrupt pin\n");
862 return 0;
863 }
864 pin = pin - 1;
866 DBG("IRQ for %s:%d", dev->slot_name, pin);
867 info = pirq_get_info(dev);
868 if (!info) {
869 DBG(" -> not found in routing table\n");
870 return 0;
871 }
872 pirq = info->irq[pin].link;
873 mask = info->irq[pin].bitmap;
874 if (!pirq) {
875 DBG(" -> not routed\n");
876 return 0;
877 }
878 DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs);
879 mask &= pcibios_irq_mask;
881 /* Work around broken HP Pavilion Notebooks which assign USB to
882 IRQ 9 even though it is actually wired to IRQ 11 */
884 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
885 dev->irq = 11;
886 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
887 r->set(pirq_router_dev, dev, pirq, 11);
888 }
890 /*
891 * Find the best IRQ to assign: use the one
892 * reported by the device if possible.
893 */
894 newirq = dev->irq;
895 if (!newirq && assign) {
896 for (i = 0; i < 16; i++) {
897 if (!(mask & (1 << i)))
898 continue;
899 if (pirq_penalty[i] < pirq_penalty[newirq] &&
900 pirq_guest_bindable(i,1))
901 newirq = i;
902 }
903 }
904 DBG(" -> newirq=%d", newirq);
906 /* Check if it is hardcoded */
907 if ((pirq & 0xf0) == 0xf0) {
908 irq = pirq & 0xf;
909 DBG(" -> hardcoded IRQ %d\n", irq);
910 msg = "Hardcoded";
911 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq))) {
912 DBG(" -> got IRQ %d\n", irq);
913 msg = "Found";
914 } else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
915 DBG(" -> assigning IRQ %d", newirq);
916 if (r->set(pirq_router_dev, dev, pirq, newirq)) {
917 eisa_set_level_irq(newirq);
918 DBG(" ... OK\n");
919 msg = "Assigned";
920 irq = newirq;
921 }
922 }
924 if (!irq) {
925 DBG(" ... failed\n");
926 if (newirq && mask == (1 << newirq)) {
927 msg = "Guessed";
928 irq = newirq;
929 } else
930 return 0;
931 }
932 printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, dev->slot_name);
934 /* Update IRQ for all devices with the same pirq value */
935 pci_for_each_dev(dev2) {
936 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
937 if (!pin)
938 continue;
939 pin--;
940 info = pirq_get_info(dev2);
941 if (!info)
942 continue;
943 if (info->irq[pin].link == pirq) {
944 /* We refuse to override the dev->irq information. Give a warning! */
945 if (dev2->irq && dev2->irq != irq) {
946 printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
947 dev2->slot_name, dev2->irq, irq);
948 continue;
949 }
950 dev2->irq = irq;
951 pirq_penalty[irq]++;
952 if (dev != dev2)
953 printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, dev2->slot_name);
954 }
955 }
956 return 1;
957 }
959 void __init pcibios_irq_init(void)
960 {
961 DBG("PCI: IRQ init\n");
962 pirq_table = pirq_find_routing_table();
963 #ifdef CONFIG_PCI_BIOS
964 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
965 pirq_table = pcibios_get_irq_routing_table();
966 #endif
967 if (pirq_table) {
968 pirq_peer_trick();
969 pirq_find_router(&pirq_router);
970 if (pirq_table->exclusive_irqs) {
971 int i;
972 for (i=0; i<16; i++)
973 if (!(pirq_table->exclusive_irqs & (1 << i)))
974 pirq_penalty[i] += 100;
975 }
976 /* If we're using the I/O APIC, avoid using the PCI IRQ routing table */
977 if (io_apic_assign_pci_irqs)
978 pirq_table = NULL;
979 }
980 }
982 void __init pcibios_fixup_irqs(void)
983 {
984 struct pci_dev *dev;
985 u8 pin;
987 DBG("PCI: IRQ fixup\n");
988 pci_for_each_dev(dev) {
989 /*
990 * If the BIOS has set an out of range IRQ number, just ignore it.
991 * Also keep track of which IRQ's are already in use.
992 */
993 if (dev->irq >= 16) {
994 DBG("%s: ignoring bogus IRQ %d\n", dev->slot_name, dev->irq);
995 dev->irq = 0;
996 }
997 /* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */
998 if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000)
999 pirq_penalty[dev->irq] = 0;
1000 pirq_penalty[dev->irq]++;
1003 pci_for_each_dev(dev) {
1004 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1005 #ifdef CONFIG_X86_IO_APIC
1006 /*
1007 * Recalculate IRQ numbers if we use the I/O APIC.
1008 */
1009 if (io_apic_assign_pci_irqs)
1011 int irq;
1013 if (pin) {
1014 pin--; /* interrupt pins are numbered starting from 1 */
1015 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin);
1016 /*
1017 * Busses behind bridges are typically not listed in the MP-table.
1018 * In this case we have to look up the IRQ based on the parent bus,
1019 * parent slot, and pin number. The SMP code detects such bridged
1020 * busses itself so we should get into this branch reliably.
1021 */
1022 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */
1023 struct pci_dev * bridge = dev->bus->self;
1025 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
1026 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
1027 PCI_SLOT(bridge->devfn), pin);
1028 if (irq >= 0)
1029 printk(KERN_WARNING "PCI: using PPB(B%d,I%d,P%d) to get irq %d\n",
1030 bridge->bus->number, PCI_SLOT(bridge->devfn), pin, irq);
1032 if (irq >= 0) {
1033 printk(KERN_INFO "PCI->APIC IRQ transform: (B%d,I%d,P%d) -> %d\n",
1034 dev->bus->number, PCI_SLOT(dev->devfn), pin, irq);
1035 dev->irq = irq;
1039 #endif
1040 /*
1041 * Still no IRQ? Try to lookup one...
1042 */
1043 if (pin && !dev->irq)
1044 pcibios_lookup_irq(dev, 0);
1048 void pcibios_penalize_isa_irq(int irq)
1050 /*
1051 * If any ISAPnP device reports an IRQ in its list of possible
1052 * IRQ's, we try to avoid assigning it to PCI devices.
1053 */
1054 pirq_penalty[irq] += 100;
1057 void pcibios_enable_irq(struct pci_dev *dev)
1059 u8 pin;
1060 extern int interrupt_line_quirk;
1062 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1063 if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) {
1064 char *msg;
1066 /* With IDE legacy devices the IRQ lookup failure is not a problem.. */
1067 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && !(dev->class & 0x5))
1068 return;
1070 if (io_apic_assign_pci_irqs)
1071 msg = " Probably buggy MP table.";
1072 else if (pci_probe & PCI_BIOS_IRQ_SCAN)
1073 msg = "";
1074 else
1075 msg = " Please try using pci=biosirq.";
1076 printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n",
1077 'A' + pin - 1, dev->slot_name, msg);
1079 /* VIA bridges use interrupt line for apic/pci steering across
1080 the V-Link */
1081 else if (interrupt_line_quirk)
1082 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);