debuggers.hg

view xen/arch/x86/pci-pc.c @ 3674:fb875591fd72

bitkeeper revision 1.1159.223.63 (42028527-fv-d9BM0_LRp8UKGP19gQ)

Fix NMI deferral.
Signed-off-by: keir.fraser@cl.cam.ac.uk
author kaf24@scramble.cl.cam.ac.uk
date Thu Feb 03 20:10:15 2005 +0000 (2005-02-03)
parents dee91b44a753
children 51052c8b6456 6bc867ecf95b
line source
1 /*
2 * Low-Level PCI Support for PC
3 *
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
5 */
7 #include <xen/config.h>
8 #include <xen/types.h>
9 #include <xen/kernel.h>
10 #include <xen/sched.h>
11 #include <xen/pci.h>
12 #include <xen/init.h>
13 #include <xen/ioport.h>
14 #include <xen/acpi.h>
16 /*#include <asm/segment.h>*/
17 #include <asm/io.h>
18 #include <asm/smp.h>
19 #include <asm/smpboot.h>
21 #include "pci-x86.h"
23 extern int numnodes;
24 #define __KERNEL_CS __HYPERVISOR_CS
25 #define __KERNEL_DS __HYPERVISOR_DS
27 unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2;
29 int pcibios_last_bus = -1;
30 struct pci_bus *pci_root_bus = NULL;
31 struct pci_ops *pci_root_ops = NULL;
33 int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value) = NULL;
34 int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value) = NULL;
36 static int pci_using_acpi_prt = 0;
38 #ifdef CONFIG_MULTIQUAD
39 #define BUS2QUAD(global) (mp_bus_id_to_node[global])
40 #define BUS2LOCAL(global) (mp_bus_id_to_local[global])
41 #define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
42 #else
43 #define BUS2QUAD(global) (0)
44 #define BUS2LOCAL(global) (global)
45 #define QUADLOCAL2BUS(quad,local) (local)
46 #endif
48 /*
49 * This interrupt-safe spinlock protects all accesses to PCI
50 * configuration space.
51 */
52 static spinlock_t pci_config_lock = SPIN_LOCK_UNLOCKED;
55 /*
56 * Functions for accessing PCI configuration space with type 1 accesses
57 */
59 #ifdef CONFIG_PCI_DIRECT
61 #ifdef CONFIG_MULTIQUAD
62 #define PCI_CONF1_ADDRESS(bus, dev, fn, reg) \
63 (0x80000000 | (BUS2LOCAL(bus) << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
65 static int pci_conf1_mq_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) /* CONFIG_MULTIQUAD */
66 {
67 unsigned long flags;
69 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
70 return -EINVAL;
72 spin_lock_irqsave(&pci_config_lock, flags);
74 outl_quad(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8, BUS2QUAD(bus));
76 switch (len) {
77 case 1:
78 *value = inb_quad(0xCFC + (reg & 3), BUS2QUAD(bus));
79 break;
80 case 2:
81 *value = inw_quad(0xCFC + (reg & 2), BUS2QUAD(bus));
82 break;
83 case 4:
84 *value = inl_quad(0xCFC, BUS2QUAD(bus));
85 break;
86 }
88 spin_unlock_irqrestore(&pci_config_lock, flags);
90 return 0;
91 }
93 static int pci_conf1_mq_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) /* CONFIG_MULTIQUAD */
94 {
95 unsigned long flags;
97 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
98 return -EINVAL;
100 spin_lock_irqsave(&pci_config_lock, flags);
102 outl_quad(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8, BUS2QUAD(bus));
104 switch (len) {
105 case 1:
106 outb_quad((u8)value, 0xCFC + (reg & 3), BUS2QUAD(bus));
107 break;
108 case 2:
109 outw_quad((u16)value, 0xCFC + (reg & 2), BUS2QUAD(bus));
110 break;
111 case 4:
112 outl_quad((u32)value, 0xCFC, BUS2QUAD(bus));
113 break;
114 }
116 spin_unlock_irqrestore(&pci_config_lock, flags);
118 return 0;
119 }
121 static int pci_conf1_read_mq_config_byte(struct pci_dev *dev, int where, u8 *value)
122 {
123 int result;
124 u32 data;
126 result = pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
127 PCI_FUNC(dev->devfn), where, 1, &data);
129 *value = (u8)data;
131 return result;
132 }
134 static int pci_conf1_read_mq_config_word(struct pci_dev *dev, int where, u16 *value)
135 {
136 int result;
137 u32 data;
139 result = pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
140 PCI_FUNC(dev->devfn), where, 2, &data);
142 *value = (u16)data;
144 return result;
145 }
147 static int pci_conf1_read_mq_config_dword(struct pci_dev *dev, int where, u32 *value)
148 {
149 if (!value)
150 return -EINVAL;
152 return pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
153 PCI_FUNC(dev->devfn), where, 4, value);
154 }
156 static int pci_conf1_write_mq_config_byte(struct pci_dev *dev, int where, u8 value)
157 {
158 return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
159 PCI_FUNC(dev->devfn), where, 1, value);
160 }
162 static int pci_conf1_write_mq_config_word(struct pci_dev *dev, int where, u16 value)
163 {
164 return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
165 PCI_FUNC(dev->devfn), where, 2, value);
166 }
168 static int pci_conf1_write_mq_config_dword(struct pci_dev *dev, int where, u32 value)
169 {
170 return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
171 PCI_FUNC(dev->devfn), where, 4, value);
172 }
174 static struct pci_ops pci_direct_mq_conf1 = {
175 pci_conf1_read_mq_config_byte,
176 pci_conf1_read_mq_config_word,
177 pci_conf1_read_mq_config_dword,
178 pci_conf1_write_mq_config_byte,
179 pci_conf1_write_mq_config_word,
180 pci_conf1_write_mq_config_dword
181 };
183 #endif /* !CONFIG_MULTIQUAD */
184 #define PCI_CONF1_ADDRESS(bus, dev, fn, reg) \
185 (0x80000000 | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
187 static int pci_conf1_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) /* !CONFIG_MULTIQUAD */
188 {
189 unsigned long flags;
191 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
192 return -EINVAL;
194 spin_lock_irqsave(&pci_config_lock, flags);
196 outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
198 switch (len) {
199 case 1:
200 *value = inb(0xCFC + (reg & 3));
201 break;
202 case 2:
203 *value = inw(0xCFC + (reg & 2));
204 break;
205 case 4:
206 *value = inl(0xCFC);
207 break;
208 }
210 spin_unlock_irqrestore(&pci_config_lock, flags);
212 return 0;
213 }
215 static int pci_conf1_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) /* !CONFIG_MULTIQUAD */
216 {
217 unsigned long flags;
219 if ((bus > 255 || dev > 31 || fn > 7 || reg > 255))
220 return -EINVAL;
222 spin_lock_irqsave(&pci_config_lock, flags);
224 outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
226 switch (len) {
227 case 1:
228 outb((u8)value, 0xCFC + (reg & 3));
229 break;
230 case 2:
231 outw((u16)value, 0xCFC + (reg & 2));
232 break;
233 case 4:
234 outl((u32)value, 0xCFC);
235 break;
236 }
238 spin_unlock_irqrestore(&pci_config_lock, flags);
240 return 0;
241 }
243 #undef PCI_CONF1_ADDRESS
245 static int pci_conf1_read_config_byte(struct pci_dev *dev, int where, u8 *value)
246 {
247 int result;
248 u32 data;
250 result = pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
251 PCI_FUNC(dev->devfn), where, 1, &data);
253 *value = (u8)data;
255 return result;
256 }
258 static int pci_conf1_read_config_word(struct pci_dev *dev, int where, u16 *value)
259 {
260 int result;
261 u32 data;
263 result = pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
264 PCI_FUNC(dev->devfn), where, 2, &data);
266 *value = (u16)data;
268 return result;
269 }
271 static int pci_conf1_read_config_dword(struct pci_dev *dev, int where, u32 *value)
272 {
273 return pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
274 PCI_FUNC(dev->devfn), where, 4, value);
275 }
277 static int pci_conf1_write_config_byte(struct pci_dev *dev, int where, u8 value)
278 {
279 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
280 PCI_FUNC(dev->devfn), where, 1, value);
281 }
283 static int pci_conf1_write_config_word(struct pci_dev *dev, int where, u16 value)
284 {
285 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
286 PCI_FUNC(dev->devfn), where, 2, value);
287 }
289 static int pci_conf1_write_config_dword(struct pci_dev *dev, int where, u32 value)
290 {
291 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
292 PCI_FUNC(dev->devfn), where, 4, value);
293 }
295 static struct pci_ops pci_direct_conf1 = {
296 pci_conf1_read_config_byte,
297 pci_conf1_read_config_word,
298 pci_conf1_read_config_dword,
299 pci_conf1_write_config_byte,
300 pci_conf1_write_config_word,
301 pci_conf1_write_config_dword
302 };
305 /*
306 * Functions for accessing PCI configuration space with type 2 accesses
307 */
309 #define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg)
311 static int pci_conf2_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value)
312 {
313 unsigned long flags;
315 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
316 return -EINVAL;
318 if (dev & 0x10)
319 return PCIBIOS_DEVICE_NOT_FOUND;
321 spin_lock_irqsave(&pci_config_lock, flags);
323 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
324 outb((u8)bus, 0xCFA);
326 switch (len) {
327 case 1:
328 *value = inb(PCI_CONF2_ADDRESS(dev, reg));
329 break;
330 case 2:
331 *value = inw(PCI_CONF2_ADDRESS(dev, reg));
332 break;
333 case 4:
334 *value = inl(PCI_CONF2_ADDRESS(dev, reg));
335 break;
336 }
338 outb (0, 0xCF8);
340 spin_unlock_irqrestore(&pci_config_lock, flags);
342 return 0;
343 }
345 static int pci_conf2_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value)
346 {
347 unsigned long flags;
349 if ((bus > 255 || dev > 31 || fn > 7 || reg > 255))
350 return -EINVAL;
352 if (dev & 0x10)
353 return PCIBIOS_DEVICE_NOT_FOUND;
355 spin_lock_irqsave(&pci_config_lock, flags);
357 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
358 outb((u8)bus, 0xCFA);
360 switch (len) {
361 case 1:
362 outb ((u8)value, PCI_CONF2_ADDRESS(dev, reg));
363 break;
364 case 2:
365 outw ((u16)value, PCI_CONF2_ADDRESS(dev, reg));
366 break;
367 case 4:
368 outl ((u32)value, PCI_CONF2_ADDRESS(dev, reg));
369 break;
370 }
372 outb (0, 0xCF8);
374 spin_unlock_irqrestore(&pci_config_lock, flags);
376 return 0;
377 }
379 #undef PCI_CONF2_ADDRESS
381 static int pci_conf2_read_config_byte(struct pci_dev *dev, int where, u8 *value)
382 {
383 int result;
384 u32 data;
385 result = pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
386 PCI_FUNC(dev->devfn), where, 1, &data);
387 *value = (u8)data;
388 return result;
389 }
391 static int pci_conf2_read_config_word(struct pci_dev *dev, int where, u16 *value)
392 {
393 int result;
394 u32 data;
395 result = pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
396 PCI_FUNC(dev->devfn), where, 2, &data);
397 *value = (u16)data;
398 return result;
399 }
401 static int pci_conf2_read_config_dword(struct pci_dev *dev, int where, u32 *value)
402 {
403 return pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
404 PCI_FUNC(dev->devfn), where, 4, value);
405 }
407 static int pci_conf2_write_config_byte(struct pci_dev *dev, int where, u8 value)
408 {
409 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
410 PCI_FUNC(dev->devfn), where, 1, value);
411 }
413 static int pci_conf2_write_config_word(struct pci_dev *dev, int where, u16 value)
414 {
415 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
416 PCI_FUNC(dev->devfn), where, 2, value);
417 }
419 static int pci_conf2_write_config_dword(struct pci_dev *dev, int where, u32 value)
420 {
421 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
422 PCI_FUNC(dev->devfn), where, 4, value);
423 }
425 static struct pci_ops pci_direct_conf2 = {
426 pci_conf2_read_config_byte,
427 pci_conf2_read_config_word,
428 pci_conf2_read_config_dword,
429 pci_conf2_write_config_byte,
430 pci_conf2_write_config_word,
431 pci_conf2_write_config_dword
432 };
435 /*
436 * Before we decide to use direct hardware access mechanisms, we try to do some
437 * trivial checks to ensure it at least _seems_ to be working -- we just test
438 * whether bus 00 contains a host bridge (this is similar to checking
439 * techniques used in XFree86, but ours should be more reliable since we
440 * attempt to make use of direct access hints provided by the PCI BIOS).
441 *
442 * This should be close to trivial, but it isn't, because there are buggy
443 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
444 */
445 static int __devinit pci_sanity_check(struct pci_ops *o)
446 {
447 u16 x;
448 struct pci_bus bus; /* Fake bus and device */
449 struct pci_dev dev;
451 if (pci_probe & PCI_NO_CHECKS)
452 return 1;
453 bus.number = 0;
454 dev.bus = &bus;
455 for(dev.devfn=0; dev.devfn < 0x100; dev.devfn++)
456 if ((!o->read_word(&dev, PCI_CLASS_DEVICE, &x) &&
457 (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)) ||
458 (!o->read_word(&dev, PCI_VENDOR_ID, &x) &&
459 (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)))
460 return 1;
461 DBG("PCI: Sanity check failed\n");
462 return 0;
463 }
465 static struct pci_ops * __devinit pci_check_direct(void)
466 {
467 unsigned int tmp;
468 unsigned long flags;
470 __save_flags(flags); __cli();
472 /*
473 * Check if configuration type 1 works.
474 */
475 if (pci_probe & PCI_PROBE_CONF1) {
476 outb (0x01, 0xCFB);
477 tmp = inl (0xCF8);
478 outl (0x80000000, 0xCF8);
479 if (inl (0xCF8) == 0x80000000 &&
480 pci_sanity_check(&pci_direct_conf1)) {
481 outl (tmp, 0xCF8);
482 __restore_flags(flags);
483 printk(KERN_INFO "PCI: Using configuration type 1\n");
484 request_region(0xCF8, 8, "PCI conf1");
486 #ifdef CONFIG_MULTIQUAD
487 /* Multi-Quad has an extended PCI Conf1 */
488 if(clustered_apic_mode == CLUSTERED_APIC_NUMAQ)
489 return &pci_direct_mq_conf1;
490 #endif
491 return &pci_direct_conf1;
492 }
493 outl (tmp, 0xCF8);
494 }
496 /*
497 * Check if configuration type 2 works.
498 */
499 if (pci_probe & PCI_PROBE_CONF2) {
500 outb (0x00, 0xCFB);
501 outb (0x00, 0xCF8);
502 outb (0x00, 0xCFA);
503 if (inb (0xCF8) == 0x00 && inb (0xCFA) == 0x00 &&
504 pci_sanity_check(&pci_direct_conf2)) {
505 __restore_flags(flags);
506 printk(KERN_INFO "PCI: Using configuration type 2\n");
507 request_region(0xCF8, 4, "PCI conf2");
508 return &pci_direct_conf2;
509 }
510 }
512 __restore_flags(flags);
513 return NULL;
514 }
516 #endif
518 /*
519 * BIOS32 and PCI BIOS handling.
520 */
522 #ifdef CONFIG_PCI_BIOS
524 #define PCIBIOS_PCI_FUNCTION_ID 0xb1XX
525 #define PCIBIOS_PCI_BIOS_PRESENT 0xb101
526 #define PCIBIOS_FIND_PCI_DEVICE 0xb102
527 #define PCIBIOS_FIND_PCI_CLASS_CODE 0xb103
528 #define PCIBIOS_GENERATE_SPECIAL_CYCLE 0xb106
529 #define PCIBIOS_READ_CONFIG_BYTE 0xb108
530 #define PCIBIOS_READ_CONFIG_WORD 0xb109
531 #define PCIBIOS_READ_CONFIG_DWORD 0xb10a
532 #define PCIBIOS_WRITE_CONFIG_BYTE 0xb10b
533 #define PCIBIOS_WRITE_CONFIG_WORD 0xb10c
534 #define PCIBIOS_WRITE_CONFIG_DWORD 0xb10d
535 #define PCIBIOS_GET_ROUTING_OPTIONS 0xb10e
536 #define PCIBIOS_SET_PCI_HW_INT 0xb10f
538 /* BIOS32 signature: "_32_" */
539 #define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
541 /* PCI signature: "PCI " */
542 #define PCI_SIGNATURE (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24))
544 /* PCI service signature: "$PCI" */
545 #define PCI_SERVICE (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24))
547 /* PCI BIOS hardware mechanism flags */
548 #define PCIBIOS_HW_TYPE1 0x01
549 #define PCIBIOS_HW_TYPE2 0x02
550 #define PCIBIOS_HW_TYPE1_SPEC 0x10
551 #define PCIBIOS_HW_TYPE2_SPEC 0x20
553 /*
554 * This is the standard structure used to identify the entry point
555 * to the BIOS32 Service Directory, as documented in
556 * Standard BIOS 32-bit Service Directory Proposal
557 * Revision 0.4 May 24, 1993
558 * Phoenix Technologies Ltd.
559 * Norwood, MA
560 * and the PCI BIOS specification.
561 */
563 union bios32 {
564 struct {
565 unsigned long signature; /* _32_ */
566 unsigned long entry; /* 32 bit physical address */
567 unsigned char revision; /* Revision level, 0 */
568 unsigned char length; /* Length in paragraphs should be 01 */
569 unsigned char checksum; /* All bytes must add up to zero */
570 unsigned char reserved[5]; /* Must be zero */
571 } fields;
572 char chars[16];
573 };
575 /*
576 * Physical address of the service directory. I don't know if we're
577 * allowed to have more than one of these or not, so just in case
578 * we'll make pcibios_present() take a memory start parameter and store
579 * the array there.
580 */
582 static struct {
583 unsigned long address;
584 unsigned short segment;
585 } bios32_indirect = { 0, __KERNEL_CS };
587 /*
588 * Returns the entry point for the given service, NULL on error
589 */
591 static unsigned long bios32_service(unsigned long service)
592 {
593 unsigned char return_code; /* %al */
594 unsigned long address; /* %ebx */
595 unsigned long length; /* %ecx */
596 unsigned long entry; /* %edx */
597 unsigned long flags;
599 __save_flags(flags); __cli();
600 __asm__("lcall *(%%edi); cld"
601 : "=a" (return_code),
602 "=b" (address),
603 "=c" (length),
604 "=d" (entry)
605 : "0" (service),
606 "1" (0),
607 "D" (&bios32_indirect));
608 __restore_flags(flags);
610 switch (return_code) {
611 case 0:
612 return address + entry;
613 case 0x80: /* Not present */
614 printk(KERN_WARNING "bios32_service(0x%lx): not present\n", service);
615 return 0;
616 default: /* Shouldn't happen */
617 printk(KERN_WARNING "bios32_service(0x%lx): returned 0x%x -- BIOS bug!\n",
618 service, return_code);
619 return 0;
620 }
621 }
623 static struct {
624 unsigned long address;
625 unsigned short segment;
626 } pci_indirect = { 0, __KERNEL_CS };
628 static int pci_bios_present;
630 static int __devinit check_pcibios(void)
631 {
632 u32 signature, eax, ebx, ecx;
633 u8 status, major_ver, minor_ver, hw_mech;
634 unsigned long flags, pcibios_entry;
636 if ((pcibios_entry = bios32_service(PCI_SERVICE))) {
637 pci_indirect.address = pcibios_entry + PAGE_OFFSET;
639 __save_flags(flags); __cli();
640 __asm__(
641 "lcall *(%%edi); cld\n\t"
642 "jc 1f\n\t"
643 "xor %%ah, %%ah\n"
644 "1:"
645 : "=d" (signature),
646 "=a" (eax),
647 "=b" (ebx),
648 "=c" (ecx)
649 : "1" (PCIBIOS_PCI_BIOS_PRESENT),
650 "D" (&pci_indirect)
651 : "memory");
652 __restore_flags(flags);
654 status = (eax >> 8) & 0xff;
655 hw_mech = eax & 0xff;
656 major_ver = (ebx >> 8) & 0xff;
657 minor_ver = ebx & 0xff;
658 if (pcibios_last_bus < 0)
659 pcibios_last_bus = ecx & 0xff;
660 DBG("PCI: BIOS probe returned s=%02x hw=%02x ver=%02x.%02x l=%02x\n",
661 status, hw_mech, major_ver, minor_ver, pcibios_last_bus);
662 if (status || signature != PCI_SIGNATURE) {
663 printk (KERN_ERR "PCI: BIOS BUG #%x[%08x] found\n",
664 status, signature);
665 return 0;
666 }
667 printk(KERN_INFO "PCI: PCI BIOS revision %x.%02x entry at 0x%lx, last bus=%d\n",
668 major_ver, minor_ver, pcibios_entry, pcibios_last_bus);
669 #ifdef CONFIG_PCI_DIRECT
670 if (!(hw_mech & PCIBIOS_HW_TYPE1))
671 pci_probe &= ~PCI_PROBE_CONF1;
672 if (!(hw_mech & PCIBIOS_HW_TYPE2))
673 pci_probe &= ~PCI_PROBE_CONF2;
674 #endif
675 return 1;
676 }
677 return 0;
678 }
680 static int __devinit pci_bios_find_device (unsigned short vendor, unsigned short device_id,
681 unsigned short index, unsigned char *bus, unsigned char *device_fn)
682 {
683 unsigned short bx;
684 unsigned short ret;
685 unsigned long flags;
687 __save_flags(flags); __cli();
688 __asm__("lcall *(%%edi); cld\n\t"
689 "jc 1f\n\t"
690 "xor %%ah, %%ah\n"
691 "1:"
692 : "=b" (bx),
693 "=a" (ret)
694 : "1" (PCIBIOS_FIND_PCI_DEVICE),
695 "c" (device_id),
696 "d" (vendor),
697 "S" ((int) index),
698 "D" (&pci_indirect));
699 __restore_flags(flags);
700 *bus = (bx >> 8) & 0xff;
701 *device_fn = bx & 0xff;
702 return (int) (ret & 0xff00) >> 8;
703 }
705 static int pci_bios_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value)
706 {
707 unsigned long result = 0;
708 unsigned long flags;
709 unsigned long bx = ((bus << 8) | (dev << 3) | fn);
711 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
712 return -EINVAL;
714 spin_lock_irqsave(&pci_config_lock, flags);
716 switch (len) {
717 case 1:
718 __asm__("lcall *(%%esi); cld\n\t"
719 "jc 1f\n\t"
720 "xor %%ah, %%ah\n"
721 "1:"
722 : "=c" (*value),
723 "=a" (result)
724 : "1" (PCIBIOS_READ_CONFIG_BYTE),
725 "b" (bx),
726 "D" ((long)reg),
727 "S" (&pci_indirect));
728 break;
729 case 2:
730 __asm__("lcall *(%%esi); cld\n\t"
731 "jc 1f\n\t"
732 "xor %%ah, %%ah\n"
733 "1:"
734 : "=c" (*value),
735 "=a" (result)
736 : "1" (PCIBIOS_READ_CONFIG_WORD),
737 "b" (bx),
738 "D" ((long)reg),
739 "S" (&pci_indirect));
740 break;
741 case 4:
742 __asm__("lcall *(%%esi); cld\n\t"
743 "jc 1f\n\t"
744 "xor %%ah, %%ah\n"
745 "1:"
746 : "=c" (*value),
747 "=a" (result)
748 : "1" (PCIBIOS_READ_CONFIG_DWORD),
749 "b" (bx),
750 "D" ((long)reg),
751 "S" (&pci_indirect));
752 break;
753 }
755 spin_unlock_irqrestore(&pci_config_lock, flags);
757 return (int)((result & 0xff00) >> 8);
758 }
760 static int pci_bios_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value)
761 {
762 unsigned long result = 0;
763 unsigned long flags;
764 unsigned long bx = ((bus << 8) | (dev << 3) | fn);
766 if ((bus > 255 || dev > 31 || fn > 7 || reg > 255))
767 return -EINVAL;
769 spin_lock_irqsave(&pci_config_lock, flags);
771 switch (len) {
772 case 1:
773 __asm__("lcall *(%%esi); cld\n\t"
774 "jc 1f\n\t"
775 "xor %%ah, %%ah\n"
776 "1:"
777 : "=a" (result)
778 : "0" (PCIBIOS_WRITE_CONFIG_BYTE),
779 "c" (value),
780 "b" (bx),
781 "D" ((long)reg),
782 "S" (&pci_indirect));
783 break;
784 case 2:
785 __asm__("lcall *(%%esi); cld\n\t"
786 "jc 1f\n\t"
787 "xor %%ah, %%ah\n"
788 "1:"
789 : "=a" (result)
790 : "0" (PCIBIOS_WRITE_CONFIG_WORD),
791 "c" (value),
792 "b" (bx),
793 "D" ((long)reg),
794 "S" (&pci_indirect));
795 break;
796 case 4:
797 __asm__("lcall *(%%esi); cld\n\t"
798 "jc 1f\n\t"
799 "xor %%ah, %%ah\n"
800 "1:"
801 : "=a" (result)
802 : "0" (PCIBIOS_WRITE_CONFIG_DWORD),
803 "c" (value),
804 "b" (bx),
805 "D" ((long)reg),
806 "S" (&pci_indirect));
807 break;
808 }
810 spin_unlock_irqrestore(&pci_config_lock, flags);
812 return (int)((result & 0xff00) >> 8);
813 }
815 static int pci_bios_read_config_byte(struct pci_dev *dev, int where, u8 *value)
816 {
817 int result;
818 u32 data;
820 if (!value)
821 BUG();
823 result = pci_bios_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
824 PCI_FUNC(dev->devfn), where, 1, &data);
826 *value = (u8)data;
828 return result;
829 }
831 static int pci_bios_read_config_word(struct pci_dev *dev, int where, u16 *value)
832 {
833 int result;
834 u32 data;
836 if (!value)
837 BUG();
839 result = pci_bios_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
840 PCI_FUNC(dev->devfn), where, 2, &data);
842 *value = (u16)data;
844 return result;
845 }
847 static int pci_bios_read_config_dword(struct pci_dev *dev, int where, u32 *value)
848 {
849 if (!value)
850 BUG();
852 return pci_bios_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
853 PCI_FUNC(dev->devfn), where, 4, value);
854 }
856 static int pci_bios_write_config_byte(struct pci_dev *dev, int where, u8 value)
857 {
858 return pci_bios_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
859 PCI_FUNC(dev->devfn), where, 1, value);
860 }
862 static int pci_bios_write_config_word(struct pci_dev *dev, int where, u16 value)
863 {
864 return pci_bios_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
865 PCI_FUNC(dev->devfn), where, 2, value);
866 }
868 static int pci_bios_write_config_dword(struct pci_dev *dev, int where, u32 value)
869 {
870 return pci_bios_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
871 PCI_FUNC(dev->devfn), where, 4, value);
872 }
875 /*
876 * Function table for BIOS32 access
877 */
879 static struct pci_ops pci_bios_access = {
880 pci_bios_read_config_byte,
881 pci_bios_read_config_word,
882 pci_bios_read_config_dword,
883 pci_bios_write_config_byte,
884 pci_bios_write_config_word,
885 pci_bios_write_config_dword
886 };
888 /*
889 * Try to find PCI BIOS.
890 */
892 static struct pci_ops * __devinit pci_find_bios(void)
893 {
894 union bios32 *check;
895 unsigned char sum;
896 int i, length;
898 /*
899 * Follow the standard procedure for locating the BIOS32 Service
900 * directory by scanning the permissible address range from
901 * 0xe0000 through 0xfffff for a valid BIOS32 structure.
902 */
904 for (check = (union bios32 *) __va(0xe0000);
905 check <= (union bios32 *) __va(0xffff0);
906 ++check) {
907 if (check->fields.signature != BIOS32_SIGNATURE)
908 continue;
909 length = check->fields.length * 16;
910 if (!length)
911 continue;
912 sum = 0;
913 for (i = 0; i < length ; ++i)
914 sum += check->chars[i];
915 if (sum != 0)
916 continue;
917 if (check->fields.revision != 0) {
918 printk("PCI: unsupported BIOS32 revision %d at 0x%p\n",
919 check->fields.revision, check);
920 continue;
921 }
922 DBG("PCI: BIOS32 Service Directory structure at 0x%p\n", check);
923 if (check->fields.entry >= 0x100000) {
924 printk("PCI: BIOS32 entry (0x%p) in high memory, cannot use.\n", check);
925 return NULL;
926 } else {
927 unsigned long bios32_entry = check->fields.entry;
928 DBG("PCI: BIOS32 Service Directory entry at 0x%lx\n", bios32_entry);
929 bios32_indirect.address = bios32_entry + PAGE_OFFSET;
930 if (check_pcibios())
931 return &pci_bios_access;
932 }
933 break; /* Hopefully more than one BIOS32 cannot happen... */
934 }
936 return NULL;
937 }
939 /*
940 * Sort the device list according to PCI BIOS. Nasty hack, but since some
941 * fool forgot to define the `correct' device order in the PCI BIOS specs
942 * and we want to be (possibly bug-to-bug ;-]) compatible with older kernels
943 * which used BIOS ordering, we are bound to do this...
944 */
946 static void __devinit pcibios_sort(void)
947 {
948 LIST_HEAD(sorted_devices);
949 struct list_head *ln;
950 struct pci_dev *dev, *d;
951 int idx, found;
952 unsigned char bus, devfn;
954 DBG("PCI: Sorting device list...\n");
955 while (!list_empty(&pci_devices)) {
956 ln = pci_devices.next;
957 dev = pci_dev_g(ln);
958 idx = found = 0;
959 while (pci_bios_find_device(dev->vendor, dev->device, idx, &bus, &devfn) == PCIBIOS_SUCCESSFUL) {
960 idx++;
961 for (ln=pci_devices.next; ln != &pci_devices; ln=ln->next) {
962 d = pci_dev_g(ln);
963 if (d->bus->number == bus && d->devfn == devfn) {
964 list_del(&d->global_list);
965 list_add_tail(&d->global_list, &sorted_devices);
966 if (d == dev)
967 found = 1;
968 break;
969 }
970 }
971 if (ln == &pci_devices) {
972 printk(KERN_WARNING "PCI: BIOS reporting unknown device %02x:%02x\n", bus, devfn);
973 /*
974 * We must not continue scanning as several buggy BIOSes
975 * return garbage after the last device. Grr.
976 */
977 break;
978 }
979 }
980 if (!found) {
981 printk(KERN_WARNING "PCI: Device %02x:%02x not found by BIOS\n",
982 dev->bus->number, dev->devfn);
983 list_del(&dev->global_list);
984 list_add_tail(&dev->global_list, &sorted_devices);
985 }
986 }
987 list_splice(&sorted_devices, &pci_devices);
988 }
990 /*
991 * BIOS Functions for IRQ Routing
992 */
994 struct irq_routing_options {
995 u16 size;
996 struct irq_info *table;
997 u16 segment;
998 } __attribute__((packed));
1000 struct irq_routing_table * __devinit pcibios_get_irq_routing_table(void)
1002 struct irq_routing_options opt;
1003 struct irq_routing_table *rt = NULL;
1004 int ret, map;
1005 unsigned long page;
1006 unsigned long flags;
1008 if (!pci_bios_present)
1009 return NULL;
1010 page = alloc_xenheap_page();
1011 if (!page)
1012 return NULL;
1013 opt.table = (struct irq_info *) page;
1014 opt.size = PAGE_SIZE;
1015 opt.segment = __KERNEL_DS;
1017 DBG("PCI: Fetching IRQ routing table... ");
1018 __save_flags(flags); __cli();
1019 __asm__("push %%es\n\t"
1020 "push %%ds\n\t"
1021 "pop %%es\n\t"
1022 "lcall *(%%esi); cld\n\t"
1023 "pop %%es\n\t"
1024 "jc 1f\n\t"
1025 "xor %%ah, %%ah\n"
1026 "1:"
1027 : "=a" (ret),
1028 "=b" (map)
1029 : "0" (PCIBIOS_GET_ROUTING_OPTIONS),
1030 "1" (0),
1031 "D" (&opt),
1032 "S" (&pci_indirect)
1033 : "memory");
1034 __restore_flags(flags);
1035 DBG("OK ret=%d, size=%d, map=%x\n", ret, opt.size, map);
1036 if (ret & 0xff00)
1037 printk(KERN_ERR "PCI: Error %02x when fetching IRQ routing table.\n", (ret >> 8) & 0xff);
1038 else if (opt.size) {
1039 rt = xmalloc(sizeof(struct irq_routing_table) + opt.size);
1040 if (rt) {
1041 memset(rt, 0, sizeof(struct irq_routing_table));
1042 rt->size = opt.size + sizeof(struct irq_routing_table);
1043 rt->exclusive_irqs = map;
1044 memcpy(rt->slots, (void *) page, opt.size);
1045 printk(KERN_INFO "PCI: Using BIOS Interrupt Routing Table\n");
1048 free_xenheap_page(page);
1049 return rt;
1053 int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq)
1055 int ret;
1056 unsigned long flags;
1058 __save_flags(flags); __cli();
1059 __asm__("lcall *(%%esi); cld\n\t"
1060 "jc 1f\n\t"
1061 "xor %%ah, %%ah\n"
1062 "1:"
1063 : "=a" (ret)
1064 : "0" (PCIBIOS_SET_PCI_HW_INT),
1065 "b" ((dev->bus->number << 8) | dev->devfn),
1066 "c" ((irq << 8) | (pin + 10)),
1067 "S" (&pci_indirect));
1068 __restore_flags(flags);
1069 return !(ret & 0xff00);
1072 #endif
1074 /*
1075 * Several buggy motherboards address only 16 devices and mirror
1076 * them to next 16 IDs. We try to detect this `feature' on all
1077 * primary buses (those containing host bridges as they are
1078 * expected to be unique) and remove the ghost devices.
1079 */
1081 static void __devinit pcibios_fixup_ghosts(struct pci_bus *b)
1083 struct list_head *ln, *mn;
1084 struct pci_dev *d, *e;
1085 int mirror = PCI_DEVFN(16,0);
1086 int seen_host_bridge = 0;
1087 int i;
1089 DBG("PCI: Scanning for ghost devices on bus %d\n", b->number);
1090 for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
1091 d = pci_dev_b(ln);
1092 if ((d->class >> 8) == PCI_CLASS_BRIDGE_HOST)
1093 seen_host_bridge++;
1094 for (mn=ln->next; mn != &b->devices; mn=mn->next) {
1095 e = pci_dev_b(mn);
1096 if (e->devfn != d->devfn + mirror ||
1097 e->vendor != d->vendor ||
1098 e->device != d->device ||
1099 e->class != d->class)
1100 continue;
1101 for(i=0; i<PCI_NUM_RESOURCES; i++)
1102 if (e->resource[i].start != d->resource[i].start ||
1103 e->resource[i].end != d->resource[i].end ||
1104 e->resource[i].flags != d->resource[i].flags)
1105 continue;
1106 break;
1108 if (mn == &b->devices)
1109 return;
1111 if (!seen_host_bridge)
1112 return;
1113 printk(KERN_WARNING "PCI: Ignoring ghost devices on bus %02x\n", b->number);
1115 ln = &b->devices;
1116 while (ln->next != &b->devices) {
1117 d = pci_dev_b(ln->next);
1118 if (d->devfn >= mirror) {
1119 list_del(&d->global_list);
1120 list_del(&d->bus_list);
1121 xfree(d);
1122 } else
1123 ln = ln->next;
1127 /*
1128 * Discover remaining PCI buses in case there are peer host bridges.
1129 * We use the number of last PCI bus provided by the PCI BIOS.
1130 */
1131 static void __devinit pcibios_fixup_peer_bridges(void)
1133 int n;
1134 struct pci_bus bus;
1135 struct pci_dev dev;
1136 u16 l;
1138 if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff)
1139 return;
1140 DBG("PCI: Peer bridge fixup\n");
1141 for (n=0; n <= pcibios_last_bus; n++) {
1142 if (pci_bus_exists(&pci_root_buses, n))
1143 continue;
1144 bus.number = n;
1145 bus.ops = pci_root_ops;
1146 dev.bus = &bus;
1147 for(dev.devfn=0; dev.devfn<256; dev.devfn += 8)
1148 if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) &&
1149 l != 0x0000 && l != 0xffff) {
1150 DBG("Found device at %02x:%02x [%04x]\n", n, dev.devfn, l);
1151 printk(KERN_INFO "PCI: Discovered peer bus %02x\n", n);
1152 pci_scan_bus(n, pci_root_ops, NULL);
1153 break;
1158 /*
1159 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
1160 */
1162 static void __devinit pci_fixup_i450nx(struct pci_dev *d)
1164 /*
1165 * i450NX -- Find and scan all secondary buses on all PXB's.
1166 */
1167 int pxb, reg;
1168 u8 busno, suba, subb;
1169 #ifdef CONFIG_MULTIQUAD
1170 int quad = BUS2QUAD(d->bus->number);
1171 #endif
1172 printk("PCI: Searching for i450NX host bridges on %s\n", d->slot_name);
1173 reg = 0xd0;
1174 for(pxb=0; pxb<2; pxb++) {
1175 pci_read_config_byte(d, reg++, &busno);
1176 pci_read_config_byte(d, reg++, &suba);
1177 pci_read_config_byte(d, reg++, &subb);
1178 DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
1179 if (busno)
1180 pci_scan_bus(QUADLOCAL2BUS(quad,busno), pci_root_ops, NULL); /* Bus A */
1181 if (suba < subb)
1182 pci_scan_bus(QUADLOCAL2BUS(quad,suba+1), pci_root_ops, NULL); /* Bus B */
1184 pcibios_last_bus = -1;
1187 static void __devinit pci_fixup_i450gx(struct pci_dev *d)
1189 /*
1190 * i450GX and i450KX -- Find and scan all secondary buses.
1191 * (called separately for each PCI bridge found)
1192 */
1193 u8 busno;
1194 pci_read_config_byte(d, 0x4a, &busno);
1195 printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", d->slot_name, busno);
1196 pci_scan_bus(busno, pci_root_ops, NULL);
1197 pcibios_last_bus = -1;
1200 static void __devinit pci_fixup_umc_ide(struct pci_dev *d)
1202 /*
1203 * UM8886BF IDE controller sets region type bits incorrectly,
1204 * therefore they look like memory despite of them being I/O.
1205 */
1206 int i;
1208 printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", d->slot_name);
1209 for(i=0; i<4; i++)
1210 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
1213 static void __devinit pci_fixup_ncr53c810(struct pci_dev *d)
1215 /*
1216 * NCR 53C810 returns class code 0 (at least on some systems).
1217 * Fix class to be PCI_CLASS_STORAGE_SCSI
1218 */
1219 if (!d->class) {
1220 printk("PCI: fixing NCR 53C810 class code for %s\n", d->slot_name);
1221 d->class = PCI_CLASS_STORAGE_SCSI << 8;
1225 static void __devinit pci_fixup_ide_bases(struct pci_dev *d)
1227 int i;
1229 /*
1230 * PCI IDE controllers use non-standard I/O port decoding, respect it.
1231 */
1232 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
1233 return;
1234 DBG("PCI: IDE base address fixup for %s\n", d->slot_name);
1235 for(i=0; i<4; i++) {
1236 struct resource *r = &d->resource[i];
1237 if ((r->start & ~0x80) == 0x374) {
1238 r->start |= 2;
1239 r->end = r->start;
1244 static void __devinit pci_fixup_ide_trash(struct pci_dev *d)
1246 int i;
1248 /*
1249 * There exist PCI IDE controllers which have utter garbage
1250 * in first four base registers. Ignore that.
1251 */
1252 DBG("PCI: IDE base address trash cleared for %s\n", d->slot_name);
1253 for(i=0; i<4; i++)
1254 d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
1257 static void __devinit pci_fixup_latency(struct pci_dev *d)
1259 /*
1260 * SiS 5597 and 5598 chipsets require latency timer set to
1261 * at most 32 to avoid lockups.
1262 */
1263 DBG("PCI: Setting max latency to 32\n");
1264 pcibios_max_latency = 32;
1267 static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d)
1269 /*
1270 * PIIX4 ACPI device: hardwired IRQ9
1271 */
1272 d->irq = 9;
1275 /*
1276 * Addresses issues with problems in the memory write queue timer in
1277 * certain VIA Northbridges. This bugfix is per VIA's specifications,
1278 * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
1279 * to trigger a bug in its integrated ProSavage video card, which
1280 * causes screen corruption. We only clear bits 6 and 7 for that chipset,
1281 * until VIA can provide us with definitive information on why screen
1282 * corruption occurs, and what exactly those bits do.
1284 * VIA 8363,8622,8361 Northbridges:
1285 * - bits 5, 6, 7 at offset 0x55 need to be turned off
1286 * VIA 8367 (KT266x) Northbridges:
1287 * - bits 5, 6, 7 at offset 0x95 need to be turned off
1288 * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
1289 * - bits 6, 7 at offset 0x55 need to be turned off
1290 */
1292 #define VIA_8363_KL133_REVISION_ID 0x81
1293 #define VIA_8363_KM133_REVISION_ID 0x84
1295 static void __init pci_fixup_via_northbridge_bug(struct pci_dev *d)
1297 u8 v;
1298 u8 revision;
1299 int where = 0x55;
1300 int mask = 0x1f; /* clear bits 5, 6, 7 by default */
1302 pci_read_config_byte(d, PCI_REVISION_ID, &revision);
1304 if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
1305 /* fix pci bus latency issues resulted by NB bios error
1306 it appears on bug free^Wreduced kt266x's bios forces
1307 NB latency to zero */
1308 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
1310 where = 0x95; /* the memory write queue timer register is
1311 different for the KT266x's: 0x95 not 0x55 */
1312 } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
1313 (revision == VIA_8363_KL133_REVISION_ID ||
1314 revision == VIA_8363_KM133_REVISION_ID)) {
1315 mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
1316 causes screen corruption on the KL133/KM133 */
1319 pci_read_config_byte(d, where, &v);
1320 if (v & ~mask) {
1321 printk("Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
1322 d->device, revision, where, v, mask, v & mask);
1323 v &= mask;
1324 pci_write_config_byte(d, where, v);
1328 /*
1329 * For some reasons Intel decided that certain parts of their
1330 * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
1331 * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
1332 * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
1333 * to Intel terminology. These devices do forward all addresses from
1334 * system to PCI bus no matter what are their window settings, so they are
1335 * "transparent" (or subtractive decoding) from programmers point of view.
1336 */
1337 static void __init pci_fixup_transparent_bridge(struct pci_dev *dev)
1339 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
1340 (dev->device & 0xff00) == 0x2400)
1341 dev->transparent = 1;
1344 struct pci_fixup pcibios_fixups[] = {
1345 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx },
1346 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx },
1347 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide },
1348 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash },
1349 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases },
1350 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency },
1351 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency },
1352 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi },
1353 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug },
1354 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug },
1355 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug },
1356 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug },
1357 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810 },
1358 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge },
1359 { 0 }
1360 };
1362 /*
1363 * Called after each bus is probed, but before its children
1364 * are examined.
1365 */
1367 void __devinit pcibios_fixup_bus(struct pci_bus *b)
1369 pcibios_fixup_ghosts(b);
1370 pci_read_bridge_bases(b);
1373 struct pci_bus * __devinit pcibios_scan_root(int busnum)
1375 struct pci_bus *bus;
1377 pci_for_each_bus(bus) {
1378 if (bus->number == busnum) {
1379 /* Already scanned */
1380 return bus;
1384 printk("PCI: Probing PCI hardware (bus %02x)\n", busnum);
1386 return pci_scan_bus(busnum, pci_root_ops, NULL);
1389 void __devinit pcibios_config_init(void)
1391 /*
1392 * Try all known PCI access methods. Note that we support using
1393 * both PCI BIOS and direct access, with a preference for direct.
1394 */
1396 #ifdef CONFIG_PCI_DIRECT
1397 struct pci_ops *tmp = NULL;
1398 #endif
1401 #ifdef CONFIG_PCI_BIOS
1402 if ((pci_probe & PCI_PROBE_BIOS)
1403 && ((pci_root_ops = pci_find_bios()))) {
1404 pci_probe |= PCI_BIOS_SORT;
1405 pci_bios_present = 1;
1406 pci_config_read = pci_bios_read;
1407 pci_config_write = pci_bios_write;
1409 #endif
1411 #ifdef CONFIG_PCI_DIRECT
1412 if ((pci_probe & (PCI_PROBE_CONF1 | PCI_PROBE_CONF2))
1413 && (tmp = pci_check_direct())) {
1414 pci_root_ops = tmp;
1415 if (pci_root_ops == &pci_direct_conf1) {
1416 pci_config_read = pci_conf1_read;
1417 pci_config_write = pci_conf1_write;
1419 else {
1420 pci_config_read = pci_conf2_read;
1421 pci_config_write = pci_conf2_write;
1424 #endif
1426 return;
1429 void __init pcibios_init(void)
1431 int quad;
1433 if (!pci_root_ops)
1434 pcibios_config_init();
1435 if (!pci_root_ops) {
1436 printk(KERN_WARNING "PCI: System does not support PCI\n");
1437 return;
1440 pcibios_set_cacheline_size();
1442 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1443 #ifdef CONFIG_ACPI_PCI
1444 if (!acpi_noirq && !acpi_pci_irq_init()) {
1445 pci_using_acpi_prt = 1;
1446 printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n");
1447 printk(KERN_INFO "PCI: if you experience problems, try using option 'pci=noacpi' or even 'acpi=off'\n");
1449 #endif
1450 if (!pci_using_acpi_prt) {
1451 pci_root_bus = pcibios_scan_root(0);
1452 pcibios_irq_init();
1453 pcibios_fixup_peer_bridges();
1454 pcibios_fixup_irqs();
1456 if (clustered_apic_mode && (numnodes > 1)) {
1457 for (quad = 1; quad < numnodes; ++quad) {
1458 printk("Scanning PCI bus %d for quad %d\n",
1459 QUADLOCAL2BUS(quad,0), quad);
1460 pci_scan_bus(QUADLOCAL2BUS(quad,0),
1461 pci_root_ops, NULL);
1465 pcibios_resource_survey();
1467 #ifdef CONFIG_PCI_BIOS
1468 if ((pci_probe & PCI_BIOS_SORT) && !(pci_probe & PCI_NO_SORT))
1469 pcibios_sort();
1470 #endif
1473 char * __devinit pcibios_setup(char *str)
1475 if (!strcmp(str, "off")) {
1476 pci_probe = 0;
1477 return NULL;
1479 #ifdef CONFIG_PCI_BIOS
1480 else if (!strcmp(str, "bios")) {
1481 pci_probe = PCI_PROBE_BIOS;
1482 return NULL;
1483 } else if (!strcmp(str, "nobios")) {
1484 pci_probe &= ~PCI_PROBE_BIOS;
1485 return NULL;
1486 } else if (!strcmp(str, "nosort")) {
1487 pci_probe |= PCI_NO_SORT;
1488 return NULL;
1489 } else if (!strcmp(str, "biosirq")) {
1490 pci_probe |= PCI_BIOS_IRQ_SCAN;
1491 return NULL;
1493 #endif
1494 #ifdef CONFIG_PCI_DIRECT
1495 else if (!strcmp(str, "conf1")) {
1496 pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
1497 return NULL;
1499 else if (!strcmp(str, "conf2")) {
1500 pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
1501 return NULL;
1503 #endif
1504 else if (!strcmp(str, "rom")) {
1505 pci_probe |= PCI_ASSIGN_ROMS;
1506 return NULL;
1507 } else if (!strcmp(str, "assign-busses")) {
1508 pci_probe |= PCI_ASSIGN_ALL_BUSSES;
1509 return NULL;
1510 } else if (!strncmp(str, "irqmask=", 8)) {
1511 pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
1512 return NULL;
1513 } else if (!strncmp(str, "lastbus=", 8)) {
1514 pcibios_last_bus = simple_strtol(str+8, NULL, 0);
1515 return NULL;
1516 } else if (!strncmp(str, "noacpi", 6)) {
1517 acpi_noirq_set();
1518 return NULL;
1520 return str;
1523 unsigned int pcibios_assign_all_busses(void)
1525 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
1528 int pcibios_enable_device(struct pci_dev *dev, int mask)
1530 int err;
1532 if ((err = pcibios_enable_resources(dev, mask)) < 0)
1533 return err;
1535 #ifdef CONFIG_ACPI_PCI
1536 if (pci_using_acpi_prt) {
1537 acpi_pci_irq_enable(dev);
1538 return 0;
1540 #endif
1542 pcibios_enable_irq(dev);
1544 return 0;