debuggers.hg

view xen/arch/x86/pci-x86.c @ 3674:fb875591fd72

bitkeeper revision 1.1159.223.63 (42028527-fv-d9BM0_LRp8UKGP19gQ)

Fix NMI deferral.
Signed-off-by: keir.fraser@cl.cam.ac.uk
author kaf24@scramble.cl.cam.ac.uk
date Thu Feb 03 20:10:15 2005 +0000 (2005-02-03)
parents 92b8e1efa784
children
line source
1 /*
2 * Low-Level PCI Access for i386 machines
3 *
4 * Copyright 1993, 1994 Drew Eckhardt
5 * Visionary Computing
6 * (Unix and Linux consulting and custom programming)
7 * Drew@Colorado.EDU
8 * +1 (303) 786-7975
9 *
10 * Drew's work was sponsored by:
11 * iX Multiuser Multitasking Magazine
12 * Hannover, Germany
13 * hm@ix.de
14 *
15 * Copyright 1997--2000 Martin Mares <mj@ucw.cz>
16 *
17 * For more information, please consult the following manuals (look at
18 * http://www.pcisig.com/ for how to get them):
19 *
20 * PCI BIOS Specification
21 * PCI Local Bus Specification
22 * PCI to PCI Bridge Specification
23 * PCI System Design Guide
24 *
25 *
26 * CHANGELOG :
27 * Jun 17, 1994 : Modified to accommodate the broken pre-PCI BIOS SPECIFICATION
28 * Revision 2.0 present on <thys@dennis.ee.up.ac.za>'s ASUS mainboard.
29 *
30 * Jan 5, 1995 : Modified to probe PCI hardware at boot time by Frederic
31 * Potter, potter@cao-vlsi.ibp.fr
32 *
33 * Jan 10, 1995 : Modified to store the information about configured pci
34 * devices into a list, which can be accessed via /proc/pci by
35 * Curtis Varner, cvarner@cs.ucr.edu
36 *
37 * Jan 12, 1995 : CPU-PCI bridge optimization support by Frederic Potter.
38 * Alpha version. Intel & UMC chipset support only.
39 *
40 * Apr 16, 1995 : Source merge with the DEC Alpha PCI support. Most of the code
41 * moved to drivers/pci/pci.c.
42 *
43 * Dec 7, 1996 : Added support for direct configuration access of boards
44 * with Intel compatible access schemes (tsbogend@alpha.franken.de)
45 *
46 * Feb 3, 1997 : Set internal functions to static, save/restore flags
47 * avoid dead locks reading broken PCI BIOS, werner@suse.de
48 *
49 * Apr 26, 1997 : Fixed case when there is BIOS32, but not PCI BIOS
50 * (mj@atrey.karlin.mff.cuni.cz)
51 *
52 * May 7, 1997 : Added some missing cli()'s. [mj]
53 *
54 * Jun 20, 1997 : Corrected problems in "conf1" type accesses.
55 * (paubert@iram.es)
56 *
57 * Aug 2, 1997 : Split to PCI BIOS handling and direct PCI access parts
58 * and cleaned it up... Martin Mares <mj@atrey.karlin.mff.cuni.cz>
59 *
60 * Feb 6, 1998 : No longer using BIOS to find devices and device classes. [mj]
61 *
62 * May 1, 1998 : Support for peer host bridges. [mj]
63 *
64 * Jun 19, 1998 : Changed to use spinlocks, so that PCI configuration space
65 * can be accessed from interrupts even on SMP systems. [mj]
66 *
67 * August 1998 : Better support for peer host bridges and more paranoid
68 * checks for direct hardware access. Ugh, this file starts to look as
69 * a large gallery of common hardware bug workarounds (watch the comments)
70 * -- the PCI specs themselves are sane, but most implementors should be
71 * hit hard with \hammer scaled \magstep5. [mj]
72 *
73 * Jan 23, 1999 : More improvements to peer host bridge logic. i450NX fixup. [mj]
74 *
75 * Feb 8, 1999 : Added UM8886BF I/O address fixup. [mj]
76 *
77 * August 1999 : New resource management and configuration access stuff. [mj]
78 *
79 * Sep 19, 1999 : Use PCI IRQ routing tables for detection of peer host bridges.
80 * Based on ideas by Chris Frantz and David Hinds. [mj]
81 *
82 * Sep 28, 1999 : Handle unreported/unassigned IRQs. Thanks to Shuu Yamaguchi
83 * for a lot of patience during testing. [mj]
84 *
85 * Oct 8, 1999 : Split to pci-i386.c, pci-pc.c and pci-visws.c. [mj]
86 */
88 #include <xen/types.h>
89 #include <xen/lib.h>
90 #include <xen/pci.h>
91 #include <xen/init.h>
92 #include <xen/ioport.h>
93 #include <xen/errno.h>
95 #include "pci-x86.h"
97 void
98 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
99 struct resource *res, int resource)
100 {
101 u32 new, check;
102 int reg;
104 new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
105 if (resource < 6) {
106 reg = PCI_BASE_ADDRESS_0 + 4*resource;
107 } else if (resource == PCI_ROM_RESOURCE) {
108 res->flags |= PCI_ROM_ADDRESS_ENABLE;
109 new |= PCI_ROM_ADDRESS_ENABLE;
110 reg = dev->rom_base_reg;
111 } else {
112 /* Somebody might have asked allocation of a non-standard resource */
113 return;
114 }
116 pci_write_config_dword(dev, reg, new);
117 pci_read_config_dword(dev, reg, &check);
118 if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
119 printk(KERN_ERR "PCI: Error while updating region "
120 "%s/%d (%08x != %08x)\n", dev->slot_name, resource,
121 new, check);
122 }
123 }
125 /*
126 * We need to avoid collisions with `mirrored' VGA ports
127 * and other strange ISA hardware, so we always want the
128 * addresses to be allocated in the 0x000-0x0ff region
129 * modulo 0x400.
130 *
131 * Why? Because some silly external IO cards only decode
132 * the low 10 bits of the IO address. The 0x00-0xff region
133 * is reserved for motherboard devices that decode all 16
134 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
135 * but we want to try to avoid allocating at 0x2900-0x2bff
136 * which might have be mirrored at 0x0100-0x03ff..
137 */
138 void
139 pcibios_align_resource(void *data, struct resource *res,
140 unsigned long size, unsigned long align)
141 {
142 if (res->flags & IORESOURCE_IO) {
143 unsigned long start = res->start;
145 if (start & 0x300) {
146 start = (start + 0x3ff) & ~0x3ff;
147 res->start = start;
148 }
149 }
150 }
153 /*
154 * Handle resources of PCI devices. If the world were perfect, we could
155 * just allocate all the resource regions and do nothing more. It isn't.
156 * On the other hand, we cannot just re-allocate all devices, as it would
157 * require us to know lots of host bridge internals. So we attempt to
158 * keep as much of the original configuration as possible, but tweak it
159 * when it's found to be wrong.
160 *
161 * Known BIOS problems we have to work around:
162 * - I/O or memory regions not configured
163 * - regions configured, but not enabled in the command register
164 * - bogus I/O addresses above 64K used
165 * - expansion ROMs left enabled (this may sound harmless, but given
166 * the fact the PCI specs explicitly allow address decoders to be
167 * shared between expansion ROMs and other resource regions, it's
168 * at least dangerous)
169 *
170 * Our solution:
171 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
172 * This gives us fixed barriers on where we can allocate.
173 * (2) Allocate resources for all enabled devices. If there is
174 * a collision, just mark the resource as unallocated. Also
175 * disable expansion ROMs during this step.
176 * (3) Try to allocate resources for disabled devices. If the
177 * resources were assigned correctly, everything goes well,
178 * if they weren't, they won't disturb allocation of other
179 * resources.
180 * (4) Assign new addresses to resources which were either
181 * not configured at all or misconfigured. If explicitly
182 * requested by the user, configure expansion ROM address
183 * as well.
184 */
186 static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
187 {
188 struct list_head *ln;
189 struct pci_bus *bus;
190 struct pci_dev *dev;
191 int idx;
192 struct resource *r, *pr;
194 /* Depth-First Search on bus tree */
195 for (ln=bus_list->next; ln != bus_list; ln=ln->next) {
196 bus = pci_bus_b(ln);
197 if ((dev = bus->self)) {
198 for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
199 r = &dev->resource[idx];
200 if (!r->start)
201 continue;
202 pr = pci_find_parent_resource(dev, r);
203 if (!pr || request_resource(pr, r) < 0)
204 printk(KERN_ERR "PCI: Cannot allocate resource region %d of bridge %s\n", idx, dev->slot_name);
205 }
206 }
207 pcibios_allocate_bus_resources(&bus->children);
208 }
209 }
211 static void __init pcibios_allocate_resources(int pass)
212 {
213 struct pci_dev *dev;
214 int idx, disabled;
215 u16 command;
216 struct resource *r, *pr;
218 pci_for_each_dev(dev) {
219 pci_read_config_word(dev, PCI_COMMAND, &command);
220 for(idx = 0; idx < 6; idx++) {
221 r = &dev->resource[idx];
222 if (r->parent) /* Already allocated */
223 continue;
224 if (!r->start) /* Address not assigned at all */
225 continue;
226 if (r->flags & IORESOURCE_IO)
227 disabled = !(command & PCI_COMMAND_IO);
228 else
229 disabled = !(command & PCI_COMMAND_MEMORY);
230 if (pass == disabled) {
231 DBG("PCI: Resource %08lx-%08lx (f=%lx, d=%d, p=%d)\n",
232 r->start, r->end, r->flags, disabled, pass);
233 pr = pci_find_parent_resource(dev, r);
234 if (!pr || request_resource(pr, r) < 0) {
235 printk(KERN_ERR "PCI: Cannot allocate resource region %d of device %s\n", idx, dev->slot_name);
236 /* We'll assign a new address later */
237 r->end -= r->start;
238 r->start = 0;
239 }
240 }
241 }
242 if (!pass) {
243 r = &dev->resource[PCI_ROM_RESOURCE];
244 if (r->flags & PCI_ROM_ADDRESS_ENABLE) {
245 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
246 u32 reg;
247 DBG("PCI: Switching off ROM of %s\n", dev->slot_name);
248 r->flags &= ~PCI_ROM_ADDRESS_ENABLE;
249 pci_read_config_dword(dev, dev->rom_base_reg, &reg);
250 pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE);
251 }
252 }
253 }
254 }
256 static void __init pcibios_assign_resources(void)
257 {
258 struct pci_dev *dev;
259 int idx;
260 struct resource *r;
262 pci_for_each_dev(dev) {
263 int class = dev->class >> 8;
265 /* Don't touch classless devices and host bridges */
266 if (!class || class == PCI_CLASS_BRIDGE_HOST)
267 continue;
269 for(idx=0; idx<6; idx++) {
270 r = &dev->resource[idx];
272 /*
273 * Don't touch IDE controllers and I/O ports of video cards!
274 */
275 if ((class == PCI_CLASS_STORAGE_IDE && idx < 4) ||
276 (class == PCI_CLASS_DISPLAY_VGA && (r->flags & IORESOURCE_IO)))
277 continue;
279 /*
280 * We shall assign a new address to this resource, either because
281 * the BIOS forgot to do so or because we have decided the old
282 * address was unusable for some reason.
283 */
284 if (!r->start && r->end)
285 pci_assign_resource(dev, idx);
286 }
288 if (pci_probe & PCI_ASSIGN_ROMS) {
289 r = &dev->resource[PCI_ROM_RESOURCE];
290 r->end -= r->start;
291 r->start = 0;
292 if (r->end)
293 pci_assign_resource(dev, PCI_ROM_RESOURCE);
294 }
295 }
296 }
298 void __init pcibios_set_cacheline_size(void)
299 {
300 struct cpuinfo_x86 *c = &boot_cpu_data;
302 pci_cache_line_size = 32 >> 2;
303 if (c->x86 >= 6 && c->x86_vendor == X86_VENDOR_AMD)
304 pci_cache_line_size = 64 >> 2; /* K7 & K8 */
305 else if (c->x86 > 6 && c->x86_vendor == X86_VENDOR_INTEL)
306 pci_cache_line_size = 128 >> 2; /* P4 */
307 }
309 void __init pcibios_resource_survey(void)
310 {
311 DBG("PCI: Allocating resources\n");
312 pcibios_allocate_bus_resources(&pci_root_buses);
313 pcibios_allocate_resources(0);
314 pcibios_allocate_resources(1);
315 pcibios_assign_resources();
316 }
318 int pcibios_enable_resources(struct pci_dev *dev, int mask)
319 {
320 u16 cmd, old_cmd;
321 int idx;
322 struct resource *r;
324 pci_read_config_word(dev, PCI_COMMAND, &cmd);
325 old_cmd = cmd;
326 for(idx=0; idx<6; idx++) {
327 /* Only set up the requested stuff */
328 if (!(mask & (1<<idx)))
329 continue;
331 r = &dev->resource[idx];
332 if (!r->start && r->end) {
333 printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", dev->slot_name);
334 return -EINVAL;
335 }
336 if (r->flags & IORESOURCE_IO)
337 cmd |= PCI_COMMAND_IO;
338 if (r->flags & IORESOURCE_MEM)
339 cmd |= PCI_COMMAND_MEMORY;
340 }
341 if (dev->resource[PCI_ROM_RESOURCE].start)
342 cmd |= PCI_COMMAND_MEMORY;
343 if (cmd != old_cmd) {
344 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
345 pci_write_config_word(dev, PCI_COMMAND, cmd);
346 }
347 return 0;
348 }
350 /*
351 * If we set up a device for bus mastering, we need to check the latency
352 * timer as certain crappy BIOSes forget to set it properly.
353 */
354 unsigned int pcibios_max_latency = 255;
356 void pcibios_set_master(struct pci_dev *dev)
357 {
358 u8 lat;
359 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
360 if (lat < 16)
361 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
362 else if (lat > pcibios_max_latency)
363 lat = pcibios_max_latency;
364 else
365 return;
366 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
367 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
368 }
370 #if 0
371 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
372 enum pci_mmap_state mmap_state, int write_combine)
373 {
374 unsigned long prot;
376 /* I/O space cannot be accessed via normal processor loads and
377 * stores on this platform.
378 */
379 if (mmap_state == pci_mmap_io)
380 return -EINVAL;
382 /* Leave vm_pgoff as-is, the PCI space address is the physical
383 * address on this platform.
384 */
385 vma->vm_flags |= (VM_SHM | VM_LOCKED | VM_IO);
387 prot = pgprot_val(vma->vm_page_prot);
388 if (boot_cpu_data.x86 > 3)
389 prot |= _PAGE_PCD | _PAGE_PWT;
390 vma->vm_page_prot = __pgprot(prot);
392 /* Write-combine setting is ignored, it is changed via the mtrr
393 * interfaces on this platform.
394 */
395 if (remap_page_range(vma->vm_start, vma->vm_pgoff << PAGE_SHIFT,
396 vma->vm_end - vma->vm_start,
397 vma->vm_page_prot))
398 return -EAGAIN;
400 return 0;
401 }
402 #endif