debuggers.hg

view xen/arch/x86/smpboot.c @ 22906:700ac6445812

Now add KDB to the non-kdb tree
author Mukesh Rathor
date Thu Feb 03 15:42:41 2011 -0800 (2011-02-03)
parents 9e33a83b36df
children
line source
1 /*
2 * x86 SMP booting functions
3 *
4 * This inherits a great deal from Linux's SMP boot code:
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
23 #include <xen/config.h>
24 #include <xen/init.h>
25 #include <xen/kernel.h>
26 #include <xen/mm.h>
27 #include <xen/domain.h>
28 #include <xen/sched.h>
29 #include <xen/sched-if.h>
30 #include <xen/irq.h>
31 #include <xen/delay.h>
32 #include <xen/softirq.h>
33 #include <xen/tasklet.h>
34 #include <xen/serial.h>
35 #include <xen/numa.h>
36 #include <xen/cpu.h>
37 #include <asm/current.h>
38 #include <asm/mc146818rtc.h>
39 #include <asm/desc.h>
40 #include <asm/div64.h>
41 #include <asm/flushtlb.h>
42 #include <asm/msr.h>
43 #include <asm/mtrr.h>
44 #include <mach_apic.h>
45 #include <mach_wakecpu.h>
46 #include <smpboot_hooks.h>
47 #include <acpi/cpufreq/processor_perf.h>
49 #define setup_trampoline() (bootsym_phys(trampoline_realmode_entry))
51 /* Set if we find a B stepping CPU */
52 static int smp_b_stepping;
54 /* Package ID of each logical CPU */
55 int phys_proc_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
57 /* Core ID of each logical CPU */
58 int cpu_core_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
60 /* representing HT siblings of each logical CPU */
61 DEFINE_PER_CPU_READ_MOSTLY(cpumask_t, cpu_sibling_map);
62 /* representing HT and core siblings of each logical CPU */
63 DEFINE_PER_CPU_READ_MOSTLY(cpumask_t, cpu_core_map);
65 cpumask_t cpu_online_map __read_mostly;
66 EXPORT_SYMBOL(cpu_online_map);
68 struct cpuinfo_x86 cpu_data[NR_CPUS];
70 u32 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
71 { [0 ... NR_CPUS-1] = BAD_APICID };
73 static void map_cpu_to_logical_apicid(void);
75 static int cpu_error;
76 static enum cpu_state {
77 CPU_STATE_DEAD = 0, /* slave -> master: I am completely dead */
78 CPU_STATE_INIT, /* master -> slave: Early bringup phase 1 */
79 CPU_STATE_CALLOUT, /* master -> slave: Early bringup phase 2 */
80 CPU_STATE_CALLIN, /* slave -> master: Completed phase 2 */
81 CPU_STATE_ONLINE /* master -> slave: Go fully online now. */
82 } cpu_state;
83 #define set_cpu_state(state) do { mb(); cpu_state = (state); } while (0)
85 void *stack_base[NR_CPUS];
87 static void smp_store_cpu_info(int id)
88 {
89 struct cpuinfo_x86 *c = cpu_data + id;
91 *c = boot_cpu_data;
92 if ( id != 0 )
93 identify_cpu(c);
95 /* Mask B, Pentium, but not Pentium MMX -- remember it, as it has bugs. */
96 if ( (c->x86_vendor == X86_VENDOR_INTEL) &&
97 (c->x86 == 5) &&
98 ((c->x86_mask >= 1) && (c->x86_mask <= 4)) &&
99 (c->x86_model <= 3) )
100 smp_b_stepping = 1;
102 /*
103 * Certain Athlons might work (for various values of 'work') in SMP
104 * but they are not certified as MP capable.
105 */
106 if ( (c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6) )
107 {
108 /* Athlon 660/661 is valid. */
109 if ( (c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)) )
110 goto valid_k7;
112 /* Duron 670 is valid */
113 if ( (c->x86_model==7) && (c->x86_mask==0) )
114 goto valid_k7;
116 /*
117 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
118 * It's worth noting that the A5 stepping (662) of some Athlon XP's
119 * have the MP bit set.
120 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
121 */
122 if ( ((c->x86_model==6) && (c->x86_mask>=2)) ||
123 ((c->x86_model==7) && (c->x86_mask>=1)) ||
124 (c->x86_model> 7) )
125 if (cpu_has_mp)
126 goto valid_k7;
128 /* If we get here, it's not a certified SMP capable AMD system. */
129 add_taint(TAINT_UNSAFE_SMP);
130 }
132 valid_k7:
133 ;
134 }
136 static atomic_t tsc_count;
137 static uint64_t tsc_value;
138 static cpumask_t tsc_sync_cpu_mask;
140 static void synchronize_tsc_master(unsigned int slave)
141 {
142 unsigned int i;
144 if ( boot_cpu_has(X86_FEATURE_TSC_RELIABLE) &&
145 !cpu_isset(slave, tsc_sync_cpu_mask) )
146 return;
148 for ( i = 1; i <= 5; i++ )
149 {
150 rdtscll(tsc_value);
151 wmb();
152 atomic_inc(&tsc_count);
153 while ( atomic_read(&tsc_count) != (i<<1) )
154 cpu_relax();
155 }
157 atomic_set(&tsc_count, 0);
158 cpu_clear(slave, tsc_sync_cpu_mask);
159 }
161 static void synchronize_tsc_slave(unsigned int slave)
162 {
163 unsigned int i;
165 if ( boot_cpu_has(X86_FEATURE_TSC_RELIABLE) &&
166 !cpu_isset(slave, tsc_sync_cpu_mask) )
167 return;
169 for ( i = 1; i <= 5; i++ )
170 {
171 while ( atomic_read(&tsc_count) != ((i<<1)-1) )
172 cpu_relax();
173 rmb();
174 write_tsc(tsc_value);
175 atomic_inc(&tsc_count);
176 }
177 }
179 void smp_callin(void)
180 {
181 unsigned int cpu = smp_processor_id();
182 int i, rc;
184 /* Wait 2s total for startup. */
185 Dprintk("Waiting for CALLOUT.\n");
186 for ( i = 0; cpu_state != CPU_STATE_CALLOUT; i++ )
187 {
188 BUG_ON(i >= 200);
189 cpu_relax();
190 mdelay(10);
191 }
193 /*
194 * The boot CPU has finished the init stage and is spinning on cpu_state
195 * update until we finish. We are free to set up this CPU: first the APIC.
196 */
197 Dprintk("CALLIN, before setup_local_APIC().\n");
198 x2apic_ap_setup();
199 setup_local_APIC();
200 map_cpu_to_logical_apicid();
202 /* Save our processor parameters. */
203 smp_store_cpu_info(cpu);
205 if ( (rc = hvm_cpu_up()) != 0 )
206 {
207 extern void (*dead_idle) (void);
208 printk("CPU%d: Failed to initialise HVM. Not coming online.\n", cpu);
209 cpu_error = rc;
210 clear_local_APIC();
211 spin_debug_enable();
212 cpu_exit_clear(cpu);
213 (*dead_idle)();
214 }
216 /* Allow the master to continue. */
217 set_cpu_state(CPU_STATE_CALLIN);
219 synchronize_tsc_slave(cpu);
221 /* And wait for our final Ack. */
222 while ( cpu_state != CPU_STATE_ONLINE )
223 cpu_relax();
224 }
226 static int booting_cpu;
228 /* CPUs for which sibling maps can be computed. */
229 static cpumask_t cpu_sibling_setup_map;
231 static void set_cpu_sibling_map(int cpu)
232 {
233 int i;
234 struct cpuinfo_x86 *c = cpu_data;
236 cpu_set(cpu, cpu_sibling_setup_map);
238 if ( c[cpu].x86_num_siblings > 1 )
239 {
240 for_each_cpu_mask ( i, cpu_sibling_setup_map )
241 {
242 if ( (phys_proc_id[cpu] == phys_proc_id[i]) &&
243 (cpu_core_id[cpu] == cpu_core_id[i]) )
244 {
245 cpu_set(i, per_cpu(cpu_sibling_map, cpu));
246 cpu_set(cpu, per_cpu(cpu_sibling_map, i));
247 cpu_set(i, per_cpu(cpu_core_map, cpu));
248 cpu_set(cpu, per_cpu(cpu_core_map, i));
249 }
250 }
251 }
252 else
253 {
254 cpu_set(cpu, per_cpu(cpu_sibling_map, cpu));
255 }
257 if ( c[cpu].x86_max_cores == 1 )
258 {
259 per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu);
260 c[cpu].booted_cores = 1;
261 return;
262 }
264 for_each_cpu_mask ( i, cpu_sibling_setup_map )
265 {
266 if ( phys_proc_id[cpu] == phys_proc_id[i] )
267 {
268 cpu_set(i, per_cpu(cpu_core_map, cpu));
269 cpu_set(cpu, per_cpu(cpu_core_map, i));
270 /*
271 * Does this new cpu bringup a new core?
272 */
273 if ( cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1 )
274 {
275 /*
276 * for each core in package, increment
277 * the booted_cores for this new cpu
278 */
279 if ( first_cpu(per_cpu(cpu_sibling_map, i)) == i )
280 c[cpu].booted_cores++;
281 /*
282 * increment the core count for all
283 * the other cpus in this package
284 */
285 if ( i != cpu )
286 c[i].booted_cores++;
287 }
288 else if ( (i != cpu) && !c[cpu].booted_cores )
289 {
290 c[cpu].booted_cores = c[i].booted_cores;
291 }
292 }
293 }
294 }
296 static void construct_percpu_idt(unsigned int cpu)
297 {
298 unsigned char idt_load[10];
300 *(unsigned short *)(&idt_load[0]) = (IDT_ENTRIES*sizeof(idt_entry_t))-1;
301 *(unsigned long *)(&idt_load[2]) = (unsigned long)idt_tables[cpu];
302 __asm__ __volatile__ ( "lidt %0" : "=m" (idt_load) );
303 }
305 void start_secondary(void *unused)
306 {
307 /*
308 * Dont put anything before smp_callin(), SMP booting is so fragile that we
309 * want to limit the things done here to the most necessary things.
310 */
311 unsigned int cpu = booting_cpu;
313 set_processor_id(cpu);
314 set_current(idle_vcpu[cpu]);
315 this_cpu(curr_vcpu) = idle_vcpu[cpu];
316 if ( cpu_has_efer )
317 rdmsrl(MSR_EFER, this_cpu(efer));
318 asm volatile ( "mov %%cr4,%0" : "=r" (this_cpu(cr4)) );
320 /*
321 * Just as during early bootstrap, it is convenient here to disable
322 * spinlock checking while we have IRQs disabled. This allows us to
323 * acquire IRQ-unsafe locks when it would otherwise be disallowed.
324 *
325 * It is safe because the race we are usually trying to avoid involves
326 * a group of CPUs rendezvousing in an IPI handler, where one cannot
327 * join because it is spinning with IRQs disabled waiting to acquire a
328 * lock held by another in the rendezvous group (the lock must be an
329 * IRQ-unsafe lock since the CPU took the IPI after acquiring it, and
330 * hence had IRQs enabled). This is a deadlock scenario.
331 *
332 * However, no CPU can be involved in rendezvous until it is online,
333 * hence no such group can be waiting for this CPU until it is
334 * visible in cpu_online_map. Hence such a deadlock is not possible.
335 */
336 spin_debug_disable();
338 percpu_traps_init();
340 cpu_init();
342 smp_callin();
344 /*
345 * At this point, boot CPU has fully initialised the IDT. It is
346 * now safe to make ourselves a private copy.
347 */
348 construct_percpu_idt(cpu);
350 setup_secondary_APIC_clock();
352 /*
353 * low-memory mappings have been cleared, flush them from
354 * the local TLBs too.
355 */
356 flush_tlb_local();
358 /* This must be done before setting cpu_online_map */
359 spin_debug_enable();
360 set_cpu_sibling_map(cpu);
361 notify_cpu_starting(cpu);
362 wmb();
364 /*
365 * We need to hold vector_lock so there the set of online cpus
366 * does not change while we are assigning vectors to cpus. Holding
367 * this lock ensures we don't half assign or remove an irq from a cpu.
368 */
369 lock_vector_lock();
370 __setup_vector_irq(cpu);
371 cpu_set(cpu, cpu_online_map);
372 unlock_vector_lock();
374 init_percpu_time();
376 /* We can take interrupts now: we're officially "up". */
377 local_irq_enable();
378 mtrr_ap_init();
380 microcode_resume_cpu(cpu);
382 wmb();
383 startup_cpu_idle_loop();
384 }
386 extern struct {
387 void * esp;
388 unsigned short ss;
389 } stack_start;
391 u32 cpu_2_logical_apicid[NR_CPUS] __read_mostly =
392 { [0 ... NR_CPUS-1] = BAD_APICID };
394 static void map_cpu_to_logical_apicid(void)
395 {
396 int cpu = smp_processor_id();
397 int apicid = logical_smp_processor_id();
399 cpu_2_logical_apicid[cpu] = apicid;
400 }
402 static void unmap_cpu_to_logical_apicid(int cpu)
403 {
404 cpu_2_logical_apicid[cpu] = BAD_APICID;
405 }
407 static int wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
408 {
409 unsigned long send_status = 0, accept_status = 0;
410 int maxlvt, timeout, num_starts, i;
412 /*
413 * Be paranoid about clearing APIC errors.
414 */
415 if ( APIC_INTEGRATED(apic_version[phys_apicid]) )
416 {
417 apic_read_around(APIC_SPIV);
418 apic_write(APIC_ESR, 0);
419 apic_read(APIC_ESR);
420 }
422 Dprintk("Asserting INIT.\n");
424 /*
425 * Turn INIT on target chip via IPI
426 */
427 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
428 phys_apicid);
430 Dprintk("Waiting for send to finish...\n");
431 timeout = 0;
432 do {
433 Dprintk("+");
434 udelay(100);
435 if ( !x2apic_enabled )
436 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
437 } while ( send_status && (timeout++ < 1000) );
439 mdelay(10);
441 Dprintk("Deasserting INIT.\n");
443 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
445 Dprintk("Waiting for send to finish...\n");
446 timeout = 0;
447 do {
448 Dprintk("+");
449 udelay(100);
450 if ( !x2apic_enabled )
451 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
452 } while ( send_status && (timeout++ < 1000) );
454 /*
455 * Should we send STARTUP IPIs ?
456 *
457 * Determine this based on the APIC version.
458 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
459 */
460 num_starts = APIC_INTEGRATED(apic_version[phys_apicid]) ? 2 : 0;
462 /* Run STARTUP IPI loop. */
463 Dprintk("#startup loops: %d.\n", num_starts);
465 maxlvt = get_maxlvt();
467 for ( i = 0; i < num_starts; i++ )
468 {
469 Dprintk("Sending STARTUP #%d.\n", i+1);
470 apic_read_around(APIC_SPIV);
471 apic_write(APIC_ESR, 0);
472 apic_read(APIC_ESR);
473 Dprintk("After apic_write.\n");
475 /*
476 * STARTUP IPI
477 * Boot on the stack
478 */
479 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), phys_apicid);
481 /* Give the other CPU some time to accept the IPI. */
482 udelay(300);
484 Dprintk("Startup point 1.\n");
486 Dprintk("Waiting for send to finish...\n");
487 timeout = 0;
488 do {
489 Dprintk("+");
490 udelay(100);
491 if ( !x2apic_enabled )
492 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
493 } while ( send_status && (timeout++ < 1000) );
495 /* Give the other CPU some time to accept the IPI. */
496 udelay(200);
498 /* Due to the Pentium erratum 3AP. */
499 if ( maxlvt > 3 )
500 {
501 apic_read_around(APIC_SPIV);
502 apic_write(APIC_ESR, 0);
503 }
504 accept_status = (apic_read(APIC_ESR) & 0xEF);
505 if ( send_status || accept_status )
506 break;
507 }
508 Dprintk("After Startup.\n");
510 if ( send_status )
511 printk("APIC never delivered???\n");
512 if ( accept_status )
513 printk("APIC delivery error (%lx).\n", accept_status);
515 return (send_status | accept_status);
516 }
518 int alloc_cpu_id(void)
519 {
520 cpumask_t tmp_map;
521 int cpu;
522 cpus_complement(tmp_map, cpu_present_map);
523 cpu = first_cpu(tmp_map);
524 return (cpu < NR_CPUS) ? cpu : -ENODEV;
525 }
527 static int do_boot_cpu(int apicid, int cpu)
528 {
529 unsigned long boot_error;
530 int timeout, rc = 0;
531 unsigned long start_eip;
533 /*
534 * Save current MTRR state in case it was changed since early boot
535 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
536 */
537 mtrr_save_state();
539 booting_cpu = cpu;
541 /* start_eip had better be page-aligned! */
542 start_eip = setup_trampoline();
544 /* So we see what's up */
545 if ( opt_cpu_info )
546 printk("Booting processor %d/%d eip %lx\n",
547 cpu, apicid, start_eip);
549 stack_start.esp = stack_base[cpu];
551 /* This grunge runs the startup process for the targeted processor. */
553 set_cpu_state(CPU_STATE_INIT);
555 Dprintk("Setting warm reset code and vector.\n");
557 smpboot_setup_warm_reset_vector(start_eip);
559 /* Starting actual IPI sequence... */
560 boot_error = wakeup_secondary_cpu(apicid, start_eip);
562 if ( !boot_error )
563 {
564 /* Allow AP to start initializing. */
565 set_cpu_state(CPU_STATE_CALLOUT);
566 Dprintk("After Callout %d.\n", cpu);
568 /* Wait 5s total for a response. */
569 for ( timeout = 0; timeout < 50000; timeout++ )
570 {
571 if ( cpu_state != CPU_STATE_CALLOUT )
572 break;
573 udelay(100);
574 }
576 if ( cpu_state == CPU_STATE_CALLIN )
577 {
578 /* number CPUs logically, starting from 1 (BSP is 0) */
579 Dprintk("OK.\n");
580 print_cpu_info(cpu);
581 synchronize_tsc_master(cpu);
582 Dprintk("CPU has booted.\n");
583 }
584 else if ( cpu_state == CPU_STATE_DEAD )
585 {
586 rmb();
587 rc = cpu_error;
588 }
589 else
590 {
591 boot_error = 1;
592 mb();
593 if ( bootsym(trampoline_cpu_started) == 0xA5 )
594 /* trampoline started but...? */
595 printk("Stuck ??\n");
596 else
597 /* trampoline code not run */
598 printk("Not responding.\n");
599 }
600 }
602 if ( boot_error )
603 {
604 cpu_exit_clear(cpu);
605 rc = -EIO;
606 }
608 /* mark "stuck" area as not stuck */
609 bootsym(trampoline_cpu_started) = 0;
610 mb();
612 smpboot_restore_warm_reset_vector();
614 return rc;
615 }
617 void cpu_exit_clear(unsigned int cpu)
618 {
619 cpu_uninit(cpu);
620 unmap_cpu_to_logical_apicid(cpu);
621 set_cpu_state(CPU_STATE_DEAD);
622 }
624 static void cpu_smpboot_free(unsigned int cpu)
625 {
626 unsigned int order;
628 xfree(idt_tables[cpu]);
629 idt_tables[cpu] = NULL;
631 order = get_order_from_pages(NR_RESERVED_GDT_PAGES);
632 #ifdef __x86_64__
633 if ( per_cpu(compat_gdt_table, cpu) )
634 free_domheap_pages(virt_to_page(per_cpu(gdt_table, cpu)), order);
635 if ( per_cpu(gdt_table, cpu) )
636 free_domheap_pages(virt_to_page(per_cpu(compat_gdt_table, cpu)),
637 order);
638 per_cpu(compat_gdt_table, cpu) = NULL;
639 #else
640 free_xenheap_pages(per_cpu(gdt_table, cpu), order);
641 #endif
642 per_cpu(gdt_table, cpu) = NULL;
644 if ( stack_base[cpu] != NULL )
645 {
646 memguard_unguard_stack(stack_base[cpu]);
647 free_xenheap_pages(stack_base[cpu], STACK_ORDER);
648 stack_base[cpu] = NULL;
649 }
650 }
652 static int cpu_smpboot_alloc(unsigned int cpu)
653 {
654 unsigned int order;
655 struct desc_struct *gdt;
656 #ifdef __x86_64__
657 struct page_info *page;
658 #endif
660 stack_base[cpu] = alloc_xenheap_pages(STACK_ORDER, 0);
661 if ( stack_base[cpu] == NULL )
662 goto oom;
663 memguard_guard_stack(stack_base[cpu]);
665 order = get_order_from_pages(NR_RESERVED_GDT_PAGES);
666 #ifdef __x86_64__
667 page = alloc_domheap_pages(NULL, order,
668 MEMF_node(cpu_to_node(cpu)));
669 if ( !page )
670 goto oom;
671 per_cpu(compat_gdt_table, cpu) = gdt = page_to_virt(page);
672 memcpy(gdt, boot_cpu_compat_gdt_table,
673 NR_RESERVED_GDT_PAGES * PAGE_SIZE);
674 gdt[PER_CPU_GDT_ENTRY - FIRST_RESERVED_GDT_ENTRY].a = cpu;
675 page = alloc_domheap_pages(NULL, order,
676 MEMF_node(cpu_to_node(cpu)));
677 if ( !page )
678 goto oom;
679 per_cpu(gdt_table, cpu) = gdt = page_to_virt(page);
680 #else
681 per_cpu(gdt_table, cpu) = gdt = alloc_xenheap_pages(order, 0);
682 if ( !gdt )
683 goto oom;
684 #endif
685 memcpy(gdt, boot_cpu_gdt_table,
686 NR_RESERVED_GDT_PAGES * PAGE_SIZE);
687 BUILD_BUG_ON(NR_CPUS > 0x10000);
688 gdt[PER_CPU_GDT_ENTRY - FIRST_RESERVED_GDT_ENTRY].a = cpu;
690 idt_tables[cpu] = xmalloc_array(idt_entry_t, IDT_ENTRIES);
691 if ( idt_tables[cpu] == NULL )
692 goto oom;
693 memcpy(idt_tables[cpu], idt_table,
694 IDT_ENTRIES*sizeof(idt_entry_t));
696 return 0;
698 oom:
699 cpu_smpboot_free(cpu);
700 return -ENOMEM;
701 }
703 static int cpu_smpboot_callback(
704 struct notifier_block *nfb, unsigned long action, void *hcpu)
705 {
706 unsigned int cpu = (unsigned long)hcpu;
707 int rc = 0;
709 switch ( action )
710 {
711 case CPU_UP_PREPARE:
712 rc = cpu_smpboot_alloc(cpu);
713 break;
714 case CPU_UP_CANCELED:
715 case CPU_DEAD:
716 cpu_smpboot_free(cpu);
717 break;
718 default:
719 break;
720 }
722 return !rc ? NOTIFY_DONE : notifier_from_errno(rc);
723 }
725 static struct notifier_block cpu_smpboot_nfb = {
726 .notifier_call = cpu_smpboot_callback
727 };
729 void __init smp_prepare_cpus(unsigned int max_cpus)
730 {
731 register_cpu_notifier(&cpu_smpboot_nfb);
733 mtrr_aps_sync_begin();
735 /* Setup boot CPU information */
736 smp_store_cpu_info(0); /* Final full version of the data */
737 print_cpu_info(0);
739 boot_cpu_physical_apicid = get_apic_id();
740 x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
742 stack_base[0] = stack_start.esp;
744 set_cpu_sibling_map(0);
746 /*
747 * If we couldn't find an SMP configuration at boot time,
748 * get out of here now!
749 */
750 if ( !smp_found_config && !acpi_lapic )
751 {
752 printk(KERN_NOTICE "SMP motherboard not detected.\n");
753 init_uniprocessor:
754 phys_cpu_present_map = physid_mask_of_physid(0);
755 if (APIC_init_uniprocessor())
756 printk(KERN_NOTICE "Local APIC not detected."
757 " Using dummy APIC emulation.\n");
758 map_cpu_to_logical_apicid();
759 cpu_set(0, per_cpu(cpu_sibling_map, 0));
760 cpu_set(0, per_cpu(cpu_core_map, 0));
761 return;
762 }
764 /*
765 * Should not be necessary because the MP table should list the boot
766 * CPU too, but we do it for the sake of robustness anyway.
767 * Makes no sense to do this check in clustered apic mode, so skip it
768 */
769 if ( !check_phys_apicid_present(boot_cpu_physical_apicid) )
770 {
771 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
772 boot_cpu_physical_apicid);
773 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
774 }
776 /* If we couldn't find a local APIC, then get out of here now! */
777 if ( APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])
778 && !cpu_has_apic )
779 {
780 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
781 boot_cpu_physical_apicid);
782 goto init_uniprocessor;
783 }
785 verify_local_APIC();
787 connect_bsp_APIC();
788 setup_local_APIC();
789 map_cpu_to_logical_apicid();
791 /*
792 * construct cpu_sibling_map, so that we can tell sibling CPUs
793 * efficiently.
794 */
795 cpu_set(0, per_cpu(cpu_sibling_map, 0));
796 cpu_set(0, per_cpu(cpu_core_map, 0));
798 smpboot_setup_io_apic();
800 setup_boot_APIC_clock();
801 }
803 void __init smp_prepare_boot_cpu(void)
804 {
805 cpu_set(smp_processor_id(), cpu_online_map);
806 cpu_set(smp_processor_id(), cpu_present_map);
807 }
809 static void
810 remove_siblinginfo(int cpu)
811 {
812 int sibling;
813 struct cpuinfo_x86 *c = cpu_data;
815 for_each_cpu_mask ( sibling, per_cpu(cpu_core_map, cpu) )
816 {
817 cpu_clear(cpu, per_cpu(cpu_core_map, sibling));
818 /* Last thread sibling in this cpu core going down. */
819 if ( cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1 )
820 c[sibling].booted_cores--;
821 }
823 for_each_cpu_mask(sibling, per_cpu(cpu_sibling_map, cpu))
824 cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling));
825 cpus_clear(per_cpu(cpu_sibling_map, cpu));
826 cpus_clear(per_cpu(cpu_core_map, cpu));
827 phys_proc_id[cpu] = BAD_APICID;
828 cpu_core_id[cpu] = BAD_APICID;
829 cpu_clear(cpu, cpu_sibling_setup_map);
830 }
832 void __cpu_disable(void)
833 {
834 extern void fixup_irqs(void);
835 int cpu = smp_processor_id();
837 local_irq_disable();
838 clear_local_APIC();
839 /* Allow any queued timer interrupts to get serviced */
840 local_irq_enable();
841 mdelay(1);
842 local_irq_disable();
844 time_suspend();
846 remove_siblinginfo(cpu);
848 /* It's now safe to remove this processor from the online map */
849 cpu_clear(cpu, cpupool0->cpu_valid);
850 cpu_clear(cpu, cpu_online_map);
851 fixup_irqs();
853 if ( cpu_disable_scheduler(cpu) )
854 BUG();
855 }
857 void __cpu_die(unsigned int cpu)
858 {
859 /* We don't do anything here: idle task is faking death itself. */
860 unsigned int i = 0;
862 while ( cpu_state != CPU_STATE_DEAD )
863 {
864 mdelay(100);
865 cpu_relax();
866 process_pending_softirqs();
867 if ( (++i % 10) == 0 )
868 printk(KERN_ERR "CPU %u still not dead...\n", cpu);
869 }
870 }
872 int cpu_add(uint32_t apic_id, uint32_t acpi_id, uint32_t pxm)
873 {
874 int node, cpu = -1;
876 dprintk(XENLOG_DEBUG, "cpu_add apic_id %x acpi_id %x pxm %x\n",
877 apic_id, acpi_id, pxm);
879 if ( acpi_id > MAX_MADT_ENTRIES || apic_id > MAX_APICS || pxm > 256 )
880 return -EINVAL;
882 if ( !cpu_hotplug_begin() )
883 return -EBUSY;
885 /* Detect if the cpu has been added before */
886 if ( x86_acpiid_to_apicid[acpi_id] != BAD_APICID )
887 {
888 cpu = (x86_acpiid_to_apicid[acpi_id] != apic_id)
889 ? -EINVAL : -EEXIST;
890 goto out;
891 }
893 if ( physid_isset(apic_id, phys_cpu_present_map) )
894 {
895 cpu = -EEXIST;
896 goto out;
897 }
899 if ( (cpu = mp_register_lapic(apic_id, 1)) < 0 )
900 goto out;
902 x86_acpiid_to_apicid[acpi_id] = apic_id;
904 if ( !srat_disabled() )
905 {
906 if ( (node = setup_node(pxm)) < 0 )
907 {
908 dprintk(XENLOG_WARNING,
909 "Setup node failed for pxm %x\n", pxm);
910 x86_acpiid_to_apicid[acpi_id] = BAD_APICID;
911 mp_unregister_lapic(apic_id, cpu);
912 cpu = node;
913 goto out;
914 }
915 apicid_to_node[apic_id] = node;
916 }
918 /* Physically added CPUs do not have synchronised TSC. */
919 if ( boot_cpu_has(X86_FEATURE_TSC_RELIABLE) )
920 {
921 static bool_t once_only;
922 if ( !test_and_set_bool(once_only) )
923 printk(XENLOG_WARNING
924 " ** New physical CPU %u may have skewed TSC and hence "
925 "break assumed cross-CPU TSC coherency.\n"
926 " ** Consider using boot parameter \"tsc=skewed\" "
927 "which forces TSC emulation where appropriate.\n", cpu);
928 cpu_set(cpu, tsc_sync_cpu_mask);
929 }
931 srat_detect_node(cpu);
932 numa_add_cpu(cpu);
933 dprintk(XENLOG_INFO, "Add CPU %x with index %x\n", apic_id, cpu);
934 out:
935 cpu_hotplug_done();
936 return cpu;
937 }
940 int __cpu_up(unsigned int cpu)
941 {
942 int apicid, ret;
944 if ( (apicid = x86_cpu_to_apicid[cpu]) == BAD_APICID )
945 return -ENODEV;
947 if ( (ret = do_boot_cpu(apicid, cpu)) != 0 )
948 return ret;
950 set_cpu_state(CPU_STATE_ONLINE);
951 while ( !cpu_isset(cpu, cpu_online_map) )
952 {
953 cpu_relax();
954 process_pending_softirqs();
955 }
957 return 0;
958 }
961 void __init smp_cpus_done(unsigned int max_cpus)
962 {
963 if ( smp_b_stepping )
964 printk(KERN_WARNING "WARNING: SMP operation may be "
965 "unreliable with B stepping processors.\n");
967 /*
968 * Don't taint if we are running SMP kernel on a single non-MP
969 * approved Athlon
970 */
971 if ( tainted & TAINT_UNSAFE_SMP )
972 {
973 if ( num_online_cpus() > 1 )
974 printk(KERN_INFO "WARNING: This combination of AMD "
975 "processors is not suitable for SMP.\n");
976 else
977 tainted &= ~TAINT_UNSAFE_SMP;
978 }
980 if ( nmi_watchdog == NMI_LOCAL_APIC )
981 check_nmi_watchdog();
983 setup_ioapic_dest();
985 mtrr_save_state();
986 mtrr_aps_sync_end();
987 }
989 void __init smp_intr_init(void)
990 {
991 int irq, seridx, cpu = smp_processor_id();
993 /*
994 * IRQ0 must be given a fixed assignment and initialized,
995 * because it's used before the IO-APIC is set up.
996 */
997 irq_vector[0] = FIRST_HIPRIORITY_VECTOR;
999 /*
1000 * Also ensure serial interrupts are high priority. We do not
1001 * want them to be blocked by unacknowledged guest-bound interrupts.
1002 */
1003 for ( seridx = 0; seridx < 2; seridx++ )
1005 if ( (irq = serial_irq(seridx)) < 0 )
1006 continue;
1007 irq_vector[irq] = FIRST_HIPRIORITY_VECTOR + seridx + 1;
1008 per_cpu(vector_irq, cpu)[FIRST_HIPRIORITY_VECTOR + seridx + 1] = irq;
1009 irq_cfg[irq].vector = FIRST_HIPRIORITY_VECTOR + seridx + 1;
1010 irq_cfg[irq].cpu_mask = cpu_online_map;
1013 /* IPI for cleanuping vectors after irq move */
1014 set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
1016 /* IPI for event checking. */
1017 set_intr_gate(EVENT_CHECK_VECTOR, event_check_interrupt);
1019 /* IPI for invalidation */
1020 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1022 /* IPI for generic function call */
1023 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);