# HG changeset patch
# User mafetter@fleming.research
# Date 1106585228 0
# Node ID 6b76ae4b9ea782641b03f051b6789508fb8c5552
# Parent  09041bbc0e2c467a611edb5e4206e305457544ac
bitkeeper revision 1.1159.212.30 (41f5268cMEdHLMEMs4o0SWqVEHZvuw)

Minor cleanup.  Removed some duplicate MSRs, fixed some MSR names,
added a few new MSRs and MSR bit fields.
Signed-off-by: michael.fetterman@cl.cam.ac.uk


diff -r 09041bbc0e2c -r 6b76ae4b9ea7 xen/arch/x86/nmi.c
--- a/xen/arch/x86/nmi.c	Mon Jan 24 16:46:25 2005 +0000
+++ b/xen/arch/x86/nmi.c	Mon Jan 24 16:47:08 2005 +0000
@@ -48,9 +48,6 @@ extern int logical_proc_id[];
 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED	0x79
 #define P6_NMI_EVENT		P6_EVENT_CPU_CLOCKS_NOT_HALTED
 
-#define MSR_P4_MISC_ENABLE	0x1A0
-#define MSR_P4_MISC_ENABLE_PERF_AVAIL	(1<<7)
-#define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL	(1<<12)
 #define MSR_P4_PERFCTR0		0x300
 #define MSR_P4_CCCR0		0x360
 #define P4_ESCR_EVENT_SELECT(N)	((N)<<25)
@@ -186,15 +183,15 @@ static int __pminit setup_p4_watchdog(vo
 {
     unsigned int misc_enable, dummy;
 
-    rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
-    if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
+    rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
+    if (!(misc_enable & MSR_IA32_MISC_ENABLE_PERF_AVAIL))
         return 0;
 
     nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
 
     if ( logical_proc_id[smp_processor_id()] == 0 )
     {
-        if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
+        if (!(misc_enable & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
             clear_msr_range(0x3F1, 2);
         /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
            docs doesn't fully define it, so leave it alone for now. */
diff -r 09041bbc0e2c -r 6b76ae4b9ea7 xen/include/asm-x86/cpufeature.h
--- a/xen/include/asm-x86/cpufeature.h	Mon Jan 24 16:46:25 2005 +0000
+++ b/xen/include/asm-x86/cpufeature.h	Mon Jan 24 16:47:08 2005 +0000
@@ -8,7 +8,7 @@
 #define __ASM_X86_CPUFEATURE_H
 
 /* Sample usage: CPU_FEATURE_P(cpu.x86_capability, FPU) */
-#define CPU_FEATURE_P(CAP, FEATURE) test_bit(CAP, X86_FEATURE_##FEATURE ##_BIT)
+#define CPU_FEATURE_P(CAP, FEATURE) test_bit(CAP, X86_FEATURE_##FEATURE)
 
 #define NCAPINTS	6	/* Currently we have 6 32-bit words worth of info */
 
diff -r 09041bbc0e2c -r 6b76ae4b9ea7 xen/include/asm-x86/fixmap.h
--- a/xen/include/asm-x86/fixmap.h	Mon Jan 24 16:46:25 2005 +0000
+++ b/xen/include/asm-x86/fixmap.h	Mon Jan 24 16:47:08 2005 +0000
@@ -26,7 +26,7 @@
  */
 enum fixed_addresses {
 #ifdef CONFIG_X86_LOCAL_APIC
-    FIX_APIC_BASE,	/* local (CPU) APIC) -- required for SMP or not */
+    FIX_APIC_BASE,	/* local (CPU) APIC -- required for SMP or not */
 #endif
 #ifdef CONFIG_X86_IO_APIC
     FIX_IO_APIC_BASE_0,
diff -r 09041bbc0e2c -r 6b76ae4b9ea7 xen/include/asm-x86/irq.h
--- a/xen/include/asm-x86/irq.h	Mon Jan 24 16:46:25 2005 +0000
+++ b/xen/include/asm-x86/irq.h	Mon Jan 24 16:47:08 2005 +0000
@@ -134,11 +134,6 @@ SYMBOL_NAME_STR(IRQ) #nr "_interrupt:\n\
 	"push"__OS" $"#nr"<<16\n\t" \
 	"jmp common_interrupt");
 
-extern unsigned long prof_cpu_mask;
-extern unsigned int *prof_buffer;
-extern unsigned long prof_len;
-extern unsigned long prof_shift;
-
 #include <xen/irq.h>
 
 static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i)
diff -r 09041bbc0e2c -r 6b76ae4b9ea7 xen/include/asm-x86/msr.h
--- a/xen/include/asm-x86/msr.h	Mon Jan 24 16:46:25 2005 +0000
+++ b/xen/include/asm-x86/msr.h	Mon Jan 24 16:47:08 2005 +0000
@@ -95,12 +95,6 @@
 #define MSR_IA32_EVNTSEL0      0x186
 #define MSR_IA32_EVNTSEL1      0x187
 
-#define MSR_IA32_DEBUGCTLMSR       0x1d9
-#define MSR_IA32_LASTBRANCHFROMIP  0x1db
-#define MSR_IA32_LASTBRANCHTOIP        0x1dc
-#define MSR_IA32_LASTINTFROMIP     0x1dd
-#define MSR_IA32_LASTINTTOIP       0x1de
-
 #define MSR_MTRRfix64K_00000	0x250
 #define MSR_MTRRfix16K_80000	0x258
 #define MSR_MTRRfix16K_A0000	0x259
@@ -119,6 +113,8 @@
 #define MSR_IA32_MC0_ADDR      0x402
 #define MSR_IA32_MC0_MISC      0x403
 
+#define MSR_IA32_DS_AREA	0x600
+
 #define MSR_IA32_APICBASE		0x1b
 #define MSR_IA32_APICBASE_BSP		(1<<8)
 #define MSR_IA32_APICBASE_ENABLE	(1<<11)
@@ -138,11 +134,22 @@
 #define MSR_IA32_THERM_STATUS		0x19c
 #define MSR_IA32_MISC_ENABLE		0x1a0
 
+#define MSR_IA32_MISC_ENABLE_PERF_AVAIL   (1<<7)
+#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL  (1<<11)
+#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
+
 #define MSR_IA32_DEBUGCTLMSR		0x1d9
-#define MSR_IA32_LASTBRANCHFROMIP	0x1db
-#define MSR_IA32_LASTBRANCHTOIP		0x1dc
-#define MSR_IA32_LASTINTFROMIP		0x1dd
-#define MSR_IA32_LASTINTTOIP		0x1de
+#define MSR_IA32_DEBUGCTLMSR_LBR        (1<<0)
+#define MSR_IA32_DEBUGCTLMSR_BTF        (1<<1)
+#define MSR_IA32_DEBUGCTLMSR_TR		(1<<2)
+#define MSR_IA32_DEBUGCTLMSR_BTS        (1<<3)
+#define MSR_IA32_DEBUGCTLMSR_BTINT      (1<<4)
+
+#define MSR_IA32_LASTBRANCH_TOS         0x1da
+#define MSR_IA32_LASTBRANCH_0		0x1db
+#define MSR_IA32_LASTBRANCH_1		0x1dc
+#define MSR_IA32_LASTBRANCH_2		0x1dd
+#define MSR_IA32_LASTBRANCH_3		0x1de
 
 #define MSR_IA32_MC0_CTL		0x400
 #define MSR_IA32_MC0_STATUS		0x401
@@ -154,6 +161,7 @@
 #define MSR_P6_EVNTSEL0			0x186
 #define MSR_P6_EVNTSEL1			0x187
 
+
 /* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */
 #define MSR_K7_EVNTSEL0            0xC0010000
 #define MSR_K7_PERFCTR0            0xC0010004