debuggers.hg

changeset 16546:0cc58b6dfeb2

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[IA64] vcpu_setcontext: only set cr_irr if VGCF_SET_CR_IRR flag is set.

cr_irr can be modified even when a vcpu is blocked (by itv handler).
Unconditionally setting cr_irr can trouble debugger as it may clear a bit
of cr_irr and thus miss an interrupt. This can be very annoying if the
interrupt is itv and the vcpu is inside PAL_HALT_LIGHT (the vcpu stays
blocked forever).

Signed-off-by: Tristan Gingold <tgingold@free.fr>
author Alex Williamson <alex.williamson@hp.com>
date Wed Nov 28 12:32:28 2007 -0700 (2007-11-28)
parents 98defc4f3bf9
children c4ed92fb0d05
files tools/libxc/ia64/xc_ia64_linux_restore.c xen/arch/ia64/vmx/vmx_vcpu_save.c xen/include/public/arch-ia64.h
line diff
     1.1 --- a/tools/libxc/ia64/xc_ia64_linux_restore.c	Mon Nov 26 10:07:30 2007 -0700
     1.2 +++ b/tools/libxc/ia64/xc_ia64_linux_restore.c	Wed Nov 28 12:32:28 2007 -0700
     1.3 @@ -127,7 +127,7 @@ xc_ia64_recv_vcpu_context(int xc_handle,
     1.4      fprintf(stderr, "ip=%016lx, b0=%016lx\n", ctxt->regs.ip, ctxt->regs.b[0]);
     1.5  
     1.6      /* Initialize and set registers.  */
     1.7 -    ctxt->flags = VGCF_EXTRA_REGS;
     1.8 +    ctxt->flags = VGCF_EXTRA_REGS | VGCF_SET_CR_IRR;
     1.9      if (xc_vcpu_setcontext(xc_handle, dom, vcpu, ctxt) != 0) {
    1.10          ERROR("Couldn't set vcpu context");
    1.11          return -1;

     2.1 --- a/xen/arch/ia64/vmx/vmx_vcpu_save.c	Mon Nov 26 10:07:30 2007 -0700
     2.2 +++ b/xen/arch/ia64/vmx/vmx_vcpu_save.c	Wed Nov 28 12:32:28 2007 -0700
     2.3 @@ -118,8 +118,8 @@ vmx_arch_set_info_guest(struct vcpu *v, 
     2.4      unsigned long vnat;
     2.5      unsigned long vbnat;
     2.6  
     2.7 -     union vcpu_ar_regs *ar = &c.nat->regs.ar;
     2.8 -     union vcpu_cr_regs *cr = &c.nat->regs.cr;
     2.9 +    union vcpu_ar_regs *ar = &c.nat->regs.ar;
    2.10 +    union vcpu_cr_regs *cr = &c.nat->regs.cr;
    2.11      int i;
    2.12  
    2.13      // banked registers
    2.14 @@ -177,13 +177,15 @@ vmx_arch_set_info_guest(struct vcpu *v, 
    2.15      vpd_low->iim = cr->iim;
    2.16      vpd_low->iha = cr->iha;
    2.17      vpd_low->lid = cr->lid;
    2.18 +    vpd_low->tpr = cr->tpr;
    2.19      vpd_low->ivr = cr->ivr; //XXX vlsapic
    2.20 -    vpd_low->tpr = cr->tpr;
    2.21      vpd_low->eoi = cr->eoi;
    2.22 -    vpd_low->irr[0] = cr->irr[0];
    2.23 -    vpd_low->irr[1] = cr->irr[1];
    2.24 -    vpd_low->irr[2] = cr->irr[2];
    2.25 -    vpd_low->irr[3] = cr->irr[3];
    2.26 +    if (c.nat->flags & VGCF_SET_CR_IRR) {
    2.27 +        vpd_low->irr[0] = cr->irr[0];
    2.28 +        vpd_low->irr[1] = cr->irr[1];
    2.29 +        vpd_low->irr[2] = cr->irr[2];
    2.30 +        vpd_low->irr[3] = cr->irr[3];
    2.31 +    }
    2.32      vpd_low->itv = cr->itv;
    2.33      vpd_low->pmv = cr->pmv;
    2.34      vpd_low->cmcv = cr->cmcv;

     3.1 --- a/xen/include/public/arch-ia64.h	Mon Nov 26 10:07:30 2007 -0700
     3.2 +++ b/xen/include/public/arch-ia64.h	Wed Nov 28 12:32:28 2007 -0700
     3.3 @@ -435,6 +435,7 @@ struct vcpu_guest_context_regs {
     3.4  
     3.5  struct vcpu_guest_context {
     3.6  #define VGCF_EXTRA_REGS (1UL << 1)	/* Set extra regs.  */
     3.7 +#define VGCF_SET_CR_IRR (1UL << 2)	/* Set cr_irr[0:3]. */
     3.8      unsigned long flags;       /* VGCF_* flags */
     3.9  
    3.10      struct vcpu_guest_context_regs regs;