debuggers.hg
changeset 16652:301507ac350a
xenoprof: Fix more than one events can't be sampled concurrently for Intel CPU with family equal to 6
The original code only sets EN bit of IA32_PERFEVTSEL0 when profiling
is started.
Signed-off-by: Xiaowei Yang <xiaowei.yang@intel.com>
The original code only sets EN bit of IA32_PERFEVTSEL0 when profiling
is started.
Signed-off-by: Xiaowei Yang <xiaowei.yang@intel.com>
author | Keir Fraser <keir.fraser@citrix.com> |
---|---|
date | Fri Dec 14 10:34:22 2007 +0000 (2007-12-14) |
parents | 61ff9b393c83 |
children | 3ee37b6279b7 |
files | xen/arch/x86/oprofile/op_model_ppro.c |
line diff
1.1 --- a/xen/arch/x86/oprofile/op_model_ppro.c Fri Dec 14 10:26:11 2007 +0000 1.2 +++ b/xen/arch/x86/oprofile/op_model_ppro.c Fri Dec 14 10:34:22 2007 +0000 1.3 @@ -104,6 +104,8 @@ static int ppro_check_ctrs(unsigned int 1.4 int mode = xenoprofile_get_mode(current, regs); 1.5 1.6 for (i = 0 ; i < NUM_COUNTERS; ++i) { 1.7 + if (!reset_value[i]) 1.8 + continue; 1.9 CTR_READ(low, high, msrs, i); 1.10 if (CTR_OVERFLOWED(low)) { 1.11 xenoprof_log_event(current, regs, eip, mode, i); 1.12 @@ -123,18 +125,30 @@ static int ppro_check_ctrs(unsigned int 1.13 static void ppro_start(struct op_msrs const * const msrs) 1.14 { 1.15 unsigned int low,high; 1.16 - CTRL_READ(low, high, msrs, 0); 1.17 - CTRL_SET_ACTIVE(low); 1.18 - CTRL_WRITE(low, high, msrs, 0); 1.19 + int i; 1.20 + 1.21 + for (i = 0; i < NUM_COUNTERS; ++i) { 1.22 + if (reset_value[i]) { 1.23 + CTRL_READ(low, high, msrs, i); 1.24 + CTRL_SET_ACTIVE(low); 1.25 + CTRL_WRITE(low, high, msrs, i); 1.26 + } 1.27 + } 1.28 } 1.29 1.30 1.31 static void ppro_stop(struct op_msrs const * const msrs) 1.32 { 1.33 unsigned int low,high; 1.34 - CTRL_READ(low, high, msrs, 0); 1.35 - CTRL_SET_INACTIVE(low); 1.36 - CTRL_WRITE(low, high, msrs, 0); 1.37 + int i; 1.38 + 1.39 + for (i = 0; i < NUM_COUNTERS; ++i) { 1.40 + if (!reset_value[i]) 1.41 + continue; 1.42 + CTRL_READ(low, high, msrs, i); 1.43 + CTRL_SET_INACTIVE(low); 1.44 + CTRL_WRITE(low, high, msrs, i); 1.45 + } 1.46 } 1.47 1.48