debuggers.hg

changeset 21957:4566d523b10a

x86 hvm: Fix MSR xentrace output.

Signed-off-by: Christoph Egger <Christoph.Egger@amd.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Aug 04 11:21:08 2010 +0100 (2010-08-04)
parents 38aee6139719
children 39448a99227b
files xen/arch/x86/hvm/hvm.c xen/arch/x86/hvm/svm/svm.c xen/arch/x86/hvm/vmx/vmx.c
line diff
     1.1 --- a/xen/arch/x86/hvm/hvm.c	Tue Aug 03 21:03:09 2010 +0100
     1.2 +++ b/xen/arch/x86/hvm/hvm.c	Wed Aug 04 11:21:08 2010 +0100
     1.3 @@ -2021,7 +2021,7 @@ int hvm_msr_read_intercept(unsigned int 
     1.4      uint64_t *var_range_base, *fixed_range_base;
     1.5      int index, mtrr;
     1.6      uint32_t cpuid[4];
     1.7 -    int ret;
     1.8 +    int ret = X86EMUL_OKAY;
     1.9  
    1.10      var_range_base = (uint64_t *)v->arch.hvm_vcpu.mtrr.var_ranges;
    1.11      fixed_range_base = (uint64_t *)v->arch.hvm_vcpu.mtrr.fixed_ranges;
    1.12 @@ -2094,24 +2094,25 @@ int hvm_msr_read_intercept(unsigned int 
    1.13           break;
    1.14  
    1.15      default:
    1.16 -        ret = vmce_rdmsr(msr, msr_content);
    1.17 -        if ( ret < 0 )
    1.18 +        if ( (ret = vmce_rdmsr(msr, msr_content)) < 0 )
    1.19              goto gp_fault;
    1.20 -        else if ( ret )
    1.21 -            break;
    1.22 -        /* ret == 0, This is not an MCE MSR, see other MSRs */
    1.23 -        else if (!ret) {
    1.24 -            return hvm_funcs.msr_read_intercept(msr, msr_content);
    1.25 -        }
    1.26 +        /* If ret == 0 then this is not an MCE MSR, see other MSRs. */
    1.27 +        ret = ((ret == 0)
    1.28 +               ? hvm_funcs.msr_read_intercept(msr, msr_content)
    1.29 +               : X86EMUL_OKAY);
    1.30 +        break;
    1.31      }
    1.32  
    1.33 -    HVMTRACE_3D(MSR_READ, (uint32_t)*msr_content, (uint32_t)(*msr_content >> 32), msr);
    1.34 -
    1.35 -    return X86EMUL_OKAY;
    1.36 -
    1.37 -gp_fault:
    1.38 + out:
    1.39 +    HVMTRACE_3D(MSR_READ, msr,
    1.40 +                (uint32_t)*msr_content, (uint32_t)(*msr_content >> 32));
    1.41 +    return ret;
    1.42 +
    1.43 + gp_fault:
    1.44      hvm_inject_exception(TRAP_gp_fault, 0, 0);
    1.45 -    return X86EMUL_EXCEPTION;
    1.46 +    ret = X86EMUL_EXCEPTION;
    1.47 +    *msr_content = -1ull;
    1.48 +    goto out;
    1.49  }
    1.50  
    1.51  int hvm_msr_write_intercept(unsigned int msr, uint64_t msr_content)
    1.52 @@ -2119,9 +2120,10 @@ int hvm_msr_write_intercept(unsigned int
    1.53      struct vcpu *v = current;
    1.54      int index, mtrr;
    1.55      uint32_t cpuid[4];
    1.56 -    int ret;
    1.57 -
    1.58 -    HVMTRACE_3D(MSR_WRITE, (uint32_t)msr_content, (uint32_t)(msr_content >> 32), msr);
    1.59 +    int ret = X86EMUL_OKAY;
    1.60 +
    1.61 +    HVMTRACE_3D(MSR_WRITE, msr,
    1.62 +               (uint32_t)msr_content, (uint32_t)(msr_content >> 32));
    1.63  
    1.64      hvm_cpuid(1, &cpuid[0], &cpuid[1], &cpuid[2], &cpuid[3]);
    1.65      mtrr = !!(cpuid[3] & bitmaskof(X86_FEATURE_MTRR));
    1.66 @@ -2194,16 +2196,16 @@ int hvm_msr_write_intercept(unsigned int
    1.67          break;
    1.68  
    1.69      default:
    1.70 -        ret = vmce_wrmsr(msr, msr_content);
    1.71 -        if ( ret < 0 )
    1.72 +        if ( (ret = vmce_wrmsr(msr, msr_content)) < 0 )
    1.73              goto gp_fault;
    1.74 -        else if ( ret )
    1.75 -            break;
    1.76 -        else if (!ret)
    1.77 -            return hvm_funcs.msr_write_intercept(msr, msr_content);
    1.78 +        /* If ret == 0 then this is not an MCE MSR, see other MSRs. */
    1.79 +        ret = ((ret == 0)
    1.80 +               ? hvm_funcs.msr_write_intercept(msr, msr_content)
    1.81 +               : X86EMUL_OKAY);
    1.82 +        break;
    1.83      }
    1.84  
    1.85 -    return X86EMUL_OKAY;
    1.86 +    return ret;
    1.87  
    1.88  gp_fault:
    1.89      hvm_inject_exception(TRAP_gp_fault, 0, 0);
     2.1 --- a/xen/arch/x86/hvm/svm/svm.c	Tue Aug 03 21:03:09 2010 +0100
     2.2 +++ b/xen/arch/x86/hvm/svm/svm.c	Wed Aug 04 11:21:08 2010 +0100
     2.3 @@ -1117,8 +1117,6 @@ static int svm_msr_read_intercept(unsign
     2.4          goto gpf;
     2.5      }
     2.6  
     2.7 -    HVMTRACE_3D (MSR_READ, msr,
     2.8 -                (uint32_t)*msr_content, (uint32_t)(*msr_content>>32));
     2.9      HVM_DBG_LOG(DBG_LEVEL_1, "returns: ecx=%x, msr_value=%"PRIx64,
    2.10                  msr, *msr_content);
    2.11      return X86EMUL_OKAY;
    2.12 @@ -1133,9 +1131,6 @@ static int svm_msr_write_intercept(unsig
    2.13      struct vcpu *v = current;
    2.14      struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
    2.15  
    2.16 -    HVMTRACE_3D(MSR_WRITE, msr,
    2.17 -               (uint32_t)msr_content, (uint32_t)(msr_content >> 32)); 
    2.18 -
    2.19      switch ( msr )
    2.20      {
    2.21      case MSR_K8_VM_HSAVE_PA:
     3.1 --- a/xen/arch/x86/hvm/vmx/vmx.c	Tue Aug 03 21:03:09 2010 +0100
     3.2 +++ b/xen/arch/x86/hvm/vmx/vmx.c	Wed Aug 04 11:21:08 2010 +0100
     3.3 @@ -1872,8 +1872,6 @@ static int vmx_msr_read_intercept(unsign
     3.4      }
     3.5  
     3.6  done:
     3.7 -    HVMTRACE_3D(MSR_READ, msr,
     3.8 -                (uint32_t)*msr_content, (uint32_t)(*msr_content >> 32));
     3.9      HVM_DBG_LOG(DBG_LEVEL_1, "returns: ecx=%x, msr_value=0x%"PRIx64,
    3.10                  msr, *msr_content);
    3.11      return X86EMUL_OKAY;
    3.12 @@ -1950,9 +1948,6 @@ static int vmx_msr_write_intercept(unsig
    3.13      HVM_DBG_LOG(DBG_LEVEL_1, "ecx=%x, msr_value=0x%"PRIx64,
    3.14                  msr, msr_content);
    3.15  
    3.16 -    HVMTRACE_3D(MSR_WRITE, msr,
    3.17 -               (uint32_t)msr_content, (uint32_t)(msr_content >> 32));
    3.18 -
    3.19      switch ( msr )
    3.20      {
    3.21      case MSR_IA32_SYSENTER_CS: