1.1 --- a/xen/arch/ia64/vmx/vmmu.c	Wed Aug 02 15:04:03 2006 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vmmu.c	Wed Aug 02 15:09:56 2006 -0600
     1.3 @@ -375,7 +375,7 @@ IA64FAULT vmx_vcpu_itc_i(VCPU *vcpu, UIN
     1.4      }
     1.5  #endif //VTLB_DEBUG    
     1.6      pte &= ~PAGE_FLAGS_RV_MASK;
     1.7 -    thash_purge_and_insert(vcpu, pte, itir, ifa);
     1.8 +    thash_purge_and_insert(vcpu, pte, itir, ifa, ISIDE_TLB);
     1.9      return IA64_NO_FAULT;
    1.10  }
    1.11  
    1.12 @@ -398,7 +398,7 @@ IA64FAULT vmx_vcpu_itc_d(VCPU *vcpu, UIN
    1.13      gpfn = (pte & _PAGE_PPN_MASK)>> PAGE_SHIFT;
    1.14      if (VMX_DOMAIN(vcpu) && __gpfn_is_io(vcpu->domain, gpfn))
    1.15          pte |= VTLB_PTE_IO;
    1.16 -    thash_purge_and_insert(vcpu, pte, itir, ifa);
    1.17 +    thash_purge_and_insert(vcpu, pte, itir, ifa, DSIDE_TLB);
    1.18      return IA64_NO_FAULT;
    1.19  
    1.20  }

     2.1 --- a/xen/arch/ia64/vmx/vmx_process.c	Wed Aug 02 15:04:03 2006 -0600
     2.2 +++ b/xen/arch/ia64/vmx/vmx_process.c	Wed Aug 02 15:09:56 2006 -0600
     2.3 @@ -313,7 +313,7 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
     2.4                      ((pteval & _PAGE_MA_MASK) != _PAGE_MA_ST)) {
     2.5                      vcpu_get_rr(v, vadr, &rr);
     2.6                      itir = rr&(RR_RID_MASK | RR_PS_MASK);
     2.7 -                    thash_purge_and_insert(v, pteval, itir , vadr);
     2.8 +                    thash_purge_and_insert(v, pteval, itir, vadr, DSIDE_TLB);
     2.9                      return IA64_NO_FAULT;
    2.10                  }
    2.11                  if(vpsr.ic){
    2.12 @@ -361,7 +361,7 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
    2.13                  if (pteval & _PAGE_P){
    2.14                      vcpu_get_rr(v, vadr, &rr);
    2.15                      itir = rr&(RR_RID_MASK | RR_PS_MASK);
    2.16 -                    thash_purge_and_insert(v, pteval, itir , vadr);
    2.17 +                    thash_purge_and_insert(v, pteval, itir, vadr, ISIDE_TLB);
    2.18                      return IA64_NO_FAULT;
    2.19                  }
    2.20                  if(!vpsr.ic){

     3.1 --- a/xen/arch/ia64/vmx/vtlb.c	Wed Aug 02 15:04:03 2006 -0600
     3.2 +++ b/xen/arch/ia64/vmx/vtlb.c	Wed Aug 02 15:09:56 2006 -0600
     3.3 @@ -450,7 +450,7 @@ u64 translate_phy_pte(VCPU *v, u64 *pte,
     3.4   * Purge overlap TCs and then insert the new entry to emulate itc ops.
     3.5   *    Notes: Only TC entry can purge and insert.
     3.6   */
     3.7 -void thash_purge_and_insert(VCPU *v, u64 pte, u64 itir, u64 ifa)
     3.8 +void thash_purge_and_insert(VCPU *v, u64 pte, u64 itir, u64 ifa, int type)
     3.9  {
    3.10      u64 ps;//, va;
    3.11      u64 phy_pte;
    3.12 @@ -490,8 +490,14 @@ void thash_purge_and_insert(VCPU *v, u64
    3.13              }
    3.14          }
    3.15          else {
    3.16 +            u64 psr;
    3.17 +            phy_pte  &= ~PAGE_FLAGS_RV_MASK;
    3.18 +            psr = ia64_clear_ic();
    3.19 +            ia64_itc(type + 1, ifa, phy_pte, ps);
    3.20 +            ia64_set_psr(psr);
    3.21 +            ia64_srlz_i();
    3.22              // ps < mrr.ps, this is not supported
    3.23 -            panic_domain(NULL, "%s: ps (%lx) < mrr.ps \n", __func__, ps);
    3.24 +            // panic_domain(NULL, "%s: ps (%lx) < mrr.ps \n", __func__, ps);
    3.25          }
    3.26      }
    3.27      else{

     4.1 --- a/xen/include/asm-ia64/vmmu.h	Wed Aug 02 15:04:03 2006 -0600
     4.2 +++ b/xen/include/asm-ia64/vmmu.h	Wed Aug 02 15:09:56 2006 -0600
     4.3 @@ -270,7 +270,7 @@ extern thash_data_t *thash_find_next_ove
     4.4   *
     4.5   */
     4.6  extern void thash_purge_entries(struct vcpu *v, u64 va, u64 ps);
     4.7 -extern void thash_purge_and_insert(struct vcpu *v, u64 pte, u64 itir, u64 ifa);
     4.8 +extern void thash_purge_and_insert(struct vcpu *v, u64 pte, u64 itir, u64 ifa, int type);
     4.9  
    4.10  /*
    4.11   * Purge all TCs or VHPT entries including those in Hash table.