debuggers.hg

changeset 22874:6067a17114bc

hvm: allow pass-through of new FPU/ALU CPUID features

there are some new CPUID features that are safe for guests to see, as
they don't require OS awareness (FPU/ALU related instructions only).
Among features for new AMD CPUs there is also the PCLMULQDQ bit, which
Intel CPU have already for quite a while.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
author Keir Fraser <keir@xen.org>
date Thu Jan 27 16:17:27 2011 +0000 (2011-01-27)
parents 3b00ee057c4a
children 5222f128a83b
files tools/libxc/xc_cpufeature.h tools/libxc/xc_cpuid_x86.c tools/libxl/libxl_cpuid.c xen/include/asm-x86/cpufeature.h
line diff
     1.1 --- a/tools/libxc/xc_cpufeature.h	Thu Jan 27 16:12:07 2011 +0000
     1.2 +++ b/tools/libxc/xc_cpufeature.h	Thu Jan 27 16:17:27 2011 +0000
     1.3 @@ -83,6 +83,7 @@
     1.4  
     1.5  /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
     1.6  #define X86_FEATURE_XMM3	(4*32+ 0) /* Streaming SIMD Extensions-3 */
     1.7 +#define X86_FEATURE_PCLMULQDQ	(4*32+ 1) /* Carry-less multiplication */
     1.8  #define X86_FEATURE_DTES64	(4*32+ 2) /* 64-bit Debug Store */
     1.9  #define X86_FEATURE_MWAIT	(4*32+ 3) /* Monitor/Mwait support */
    1.10  #define X86_FEATURE_DSCPL	(4*32+ 4) /* CPL Qualified Debug Store */
    1.11 @@ -104,6 +105,7 @@
    1.12  #define X86_FEATURE_AES		(4*32+25) /* AES acceleration instructions */
    1.13  #define X86_FEATURE_XSAVE	(4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
    1.14  #define X86_FEATURE_AVX		(4*32+28) /* Advanced Vector Extensions */
    1.15 +#define X86_FEATURE_F16C	(4*32+29) /* Half-precision convert instruction */
    1.16  #define X86_FEATURE_HYPERVISOR	(4*32+31) /* Running under some hypervisor */
    1.17  
    1.18  /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
     2.1 --- a/tools/libxc/xc_cpuid_x86.c	Thu Jan 27 16:12:07 2011 +0000
     2.2 +++ b/tools/libxc/xc_cpuid_x86.c	Thu Jan 27 16:17:27 2011 +0000
     2.3 @@ -101,7 +101,10 @@ static void amd_xc_cpuid_policy(
     2.4                      bitmaskof(X86_FEATURE_ABM) |
     2.5                      bitmaskof(X86_FEATURE_SSE4A) |
     2.6                      bitmaskof(X86_FEATURE_MISALIGNSSE) |
     2.7 -                    bitmaskof(X86_FEATURE_3DNOWPREFETCH));
     2.8 +                    bitmaskof(X86_FEATURE_3DNOWPREFETCH) |
     2.9 +                    bitmaskof(X86_FEATURE_XOP) |
    2.10 +                    bitmaskof(X86_FEATURE_FMA4) |
    2.11 +                    bitmaskof(X86_FEATURE_TBM));
    2.12          regs[3] &= (0x0183f3ff | /* features shared with 0x00000001:EDX */
    2.13                      (is_pae ? bitmaskof(X86_FEATURE_NX) : 0) |
    2.14                      (is_64bit ? bitmaskof(X86_FEATURE_LM) : 0) |
    2.15 @@ -251,12 +254,14 @@ static void xc_cpuid_hvm_policy(
    2.16          regs[1] = (regs[1] & 0x0000ffffu) | ((regs[1] & 0x007f0000u) << 1);
    2.17  
    2.18          regs[2] &= (bitmaskof(X86_FEATURE_XMM3) |
    2.19 +                    bitmaskof(X86_FEATURE_PCLMULQDQ) |
    2.20                      bitmaskof(X86_FEATURE_SSSE3) |
    2.21                      bitmaskof(X86_FEATURE_CX16) |
    2.22                      bitmaskof(X86_FEATURE_SSE4_1) |
    2.23                      bitmaskof(X86_FEATURE_SSE4_2) |
    2.24                      bitmaskof(X86_FEATURE_POPCNT) |
    2.25                      bitmaskof(X86_FEATURE_AES) |
    2.26 +                    bitmaskof(X86_FEATURE_F16C) |
    2.27                      ((xfeature_mask != 0) ?
    2.28                       (bitmaskof(X86_FEATURE_AVX) |
    2.29                        bitmaskof(X86_FEATURE_XSAVE)) : 0));
     3.1 --- a/tools/libxl/libxl_cpuid.c	Thu Jan 27 16:12:07 2011 +0000
     3.2 +++ b/tools/libxl/libxl_cpuid.c	Thu Jan 27 16:17:27 2011 +0000
     3.3 @@ -115,6 +115,7 @@ int libxl_cpuid_parse_config(libxl_cpuid
     3.4          {"dscpl",        0x00000001, NA, CPUID_REG_ECX,  4,  1},
     3.5          {"monitor",      0x00000001, NA, CPUID_REG_ECX,  3,  1},
     3.6          {"dtes64",       0x00000001, NA, CPUID_REG_ECX,  2,  1},
     3.7 +        {"pclmulqdq",    0x00000001, NA, CPUID_REG_ECX,  1,  1},
     3.8          {"sse3",         0x00000001, NA, CPUID_REG_ECX,  0,  1},
     3.9          {"pbe",          0x00000001, NA, CPUID_REG_EDX, 31,  1},
    3.10          {"ia64",         0x00000001, NA, CPUID_REG_EDX, 30,  1},
     4.1 --- a/xen/include/asm-x86/cpufeature.h	Thu Jan 27 16:12:07 2011 +0000
     4.2 +++ b/xen/include/asm-x86/cpufeature.h	Thu Jan 27 16:17:27 2011 +0000
     4.3 @@ -82,6 +82,7 @@
     4.4  
     4.5  /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
     4.6  #define X86_FEATURE_XMM3	(4*32+ 0) /* Streaming SIMD Extensions-3 */
     4.7 +#define X86_FEATURE_PCLMULQDQ	(4*32+ 1) /* Carry-less mulitplication */
     4.8  #define X86_FEATURE_DTES64	(4*32+ 2) /* 64-bit Debug Store */
     4.9  #define X86_FEATURE_MWAIT	(4*32+ 3) /* Monitor/Mwait support */
    4.10  #define X86_FEATURE_DSCPL	(4*32+ 4) /* CPL Qualified Debug Store */
    4.11 @@ -103,6 +104,7 @@
    4.12  #define X86_FEATURE_XSAVE	(4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
    4.13  #define X86_FEATURE_OSXSAVE	(4*32+27) /* OSXSAVE */
    4.14  #define X86_FEATURE_AVX 	(4*32+28) /* Advanced Vector Extensions */
    4.15 +#define X86_FEATURE_F16C 	(4*32+29) /* Half-precision convert instruction */
    4.16  #define X86_FEATURE_HYPERVISOR	(4*32+31) /* Running under some hypervisor */
    4.17  
    4.18  /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */