debuggers.hg

changeset 4657:67c40314aa6e

bitkeeper revision 1.1356 (4267b673efcxbbD0RRVHEKvD5FY3Ng)

A few APIC cleanups. I hate '#if 0' code.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Thu Apr 21 14:19:31 2005 +0000 (2005-04-21)
parents 6a086854f9a8
children caaf9d543bc5
files xen/arch/x86/apic.c xen/arch/x86/smpboot.c
line diff
     1.1 --- a/xen/arch/x86/apic.c	Thu Apr 21 12:12:12 2005 +0000
     1.2 +++ b/xen/arch/x86/apic.c	Thu Apr 21 14:19:31 2005 +0000
     1.3 @@ -83,16 +83,6 @@ void clear_local_APIC(void)
     1.4          apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
     1.5      }
     1.6  
     1.7 -#if 0
     1.8 -/* lets not touch this if we didn't frob it */
     1.9 -#ifdef CONFIG_X86_MCE_P4THERMAL
    1.10 -    if (maxlvt >= 5) {
    1.11 -        v = apic_read(APIC_LVTTHMR);
    1.12 -        apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
    1.13 -    }
    1.14 -#endif
    1.15 -#endif
    1.16 -
    1.17      /*
    1.18       * Clean APIC state for other OSs:
    1.19       */
    1.20 @@ -104,13 +94,6 @@ void clear_local_APIC(void)
    1.21      if (maxlvt >= 4)
    1.22          apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
    1.23  
    1.24 -#if 0
    1.25 -#ifdef CONFIG_X86_MCE_P4THERMAL
    1.26 -    if (maxlvt >= 5)
    1.27 -        apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
    1.28 -#endif
    1.29 -#endif 
    1.30 -
    1.31      v = GET_APIC_VERSION(apic_read(APIC_LVR));
    1.32      if (APIC_INTEGRATED(v)) {	/* !82489DX */
    1.33          if (maxlvt > 3)        /* Due to Pentium errata 3AP and 11AP. */
    1.34 @@ -134,9 +117,6 @@ void __init connect_bsp_APIC(void)
    1.35          outb(0x70, 0x22);
    1.36          outb(0x01, 0x23);
    1.37      }
    1.38 -#if 0
    1.39 -    enable_apic_mode();
    1.40 -#endif
    1.41  }
    1.42  
    1.43  void disconnect_bsp_APIC(void)
    1.44 @@ -406,9 +386,6 @@ void __init setup_local_APIC (void)
    1.45  
    1.46      if (nmi_watchdog == NMI_LOCAL_APIC)
    1.47          setup_apic_nmi_watchdog();
    1.48 -#if 0
    1.49 -    apic_pm_activate();
    1.50 -#endif
    1.51  }
    1.52  
    1.53  /*
    1.54 @@ -421,12 +398,6 @@ static int __init detect_init_APIC (void
    1.55      u32 h, l, features;
    1.56      extern void get_cpu_vendor(struct cpuinfo_x86*);
    1.57  
    1.58 -#if 0
    1.59 -    /* Disabled by kernel option? */
    1.60 -    if (enable_local_apic < 0)
    1.61 -        return -1;
    1.62 -#endif
    1.63 -
    1.64      /* Workaround for us being called before identify_cpu(). */
    1.65      get_cpu_vendor(&boot_cpu_data);
    1.66  
    1.67 @@ -447,17 +418,6 @@ static int __init detect_init_APIC (void
    1.68  
    1.69      if (!cpu_has_apic) {
    1.70          /*
    1.71 -         * Over-ride BIOS and try to enable the local
    1.72 -         * APIC only if "lapic" specified.
    1.73 -         */
    1.74 -#if 0
    1.75 -        if (enable_local_apic <= 0) {
    1.76 -            printk("Local APIC disabled by BIOS -- "
    1.77 -                   "you can enable it with \"lapic\"\n");
    1.78 -            return -1;
    1.79 -        }
    1.80 -#endif
    1.81 -        /*
    1.82           * Some BIOSes disable the local APIC in the
    1.83           * APIC_BASE MSR. This can only be done in
    1.84           * software for Intel P6 or later and AMD K7
    1.85 @@ -472,15 +432,14 @@ static int __init detect_init_APIC (void
    1.86              enabled_via_apicbase = 1;
    1.87          }
    1.88      }
    1.89 -    /*
    1.90 -     * The APIC feature bit should now be enabled
    1.91 -     * in `cpuid'
    1.92 -     */
    1.93 +
    1.94 +    /* The APIC feature bit should now be enabled in `cpuid' */
    1.95      features = cpuid_edx(1);
    1.96      if (!(features & (1 << X86_FEATURE_APIC))) {
    1.97          printk("Could not enable APIC!\n");
    1.98          return -1;
    1.99      }
   1.100 +
   1.101      set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
   1.102      mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
   1.103  
   1.104 @@ -489,15 +448,11 @@ static int __init detect_init_APIC (void
   1.105      if (l & MSR_IA32_APICBASE_ENABLE)
   1.106          mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
   1.107  
   1.108 -	if (nmi_watchdog != NMI_NONE)
   1.109 -		nmi_watchdog = NMI_LOCAL_APIC;
   1.110 +    if (nmi_watchdog != NMI_NONE)
   1.111 +        nmi_watchdog = NMI_LOCAL_APIC;
   1.112  
   1.113      printk("Found and enabled local APIC!\n");
   1.114  
   1.115 -#if 0
   1.116 -    apic_pm_activate();
   1.117 -#endif
   1.118 -
   1.119      return 0;
   1.120  
   1.121  no_apic:
   1.122 @@ -616,11 +571,10 @@ static void __init wait_8254_wraparound(
   1.123          delta = curr_count-prev_count;
   1.124  
   1.125          /*
   1.126 -     * This limit for delta seems arbitrary, but it isn't, it's
   1.127 -     * slightly above the level of error a buggy Mercury/Neptune
   1.128 -     * chipset timer can cause.
   1.129 +         * This limit for delta seems arbitrary, but it isn't, it's slightly
   1.130 +         * above the level of error a buggy Mercury/Neptune chipset timer can
   1.131 +         * cause.
   1.132           */
   1.133 -
   1.134      } while (delta < 300);
   1.135  }
   1.136  
   1.137 @@ -649,21 +603,12 @@ static void __setup_APIC_LVTT(unsigned i
   1.138      unsigned int lvtt_value, tmp_value, ver;
   1.139  
   1.140      ver = GET_APIC_VERSION(apic_read(APIC_LVR));
   1.141 -    lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;
   1.142 +    /* NB. Xen uses local APIC timer in one-shot mode. */
   1.143 +    lvtt_value = /*APIC_LVT_TIMER_PERIODIC |*/ LOCAL_TIMER_VECTOR;
   1.144      if (!APIC_INTEGRATED(ver))
   1.145          lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
   1.146      apic_write_around(APIC_LVTT, lvtt_value);
   1.147  
   1.148 -#if 0
   1.149 -    /*
   1.150 -     * Divide PICLK by 16
   1.151 -     */
   1.152 -    tmp_value = apic_read(APIC_TDCR);
   1.153 -    apic_write_around(APIC_TDCR, (tmp_value
   1.154 -                & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
   1.155 -                | APIC_TDR_DIV_16);
   1.156 -#endif
   1.157 -
   1.158      tmp_value = apic_read(APIC_TDCR);
   1.159      apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
   1.160  
   1.161 @@ -704,9 +649,6 @@ int __init calibrate_APIC_clock(void)
   1.162      int i;
   1.163      const int LOOPS = HZ/10;
   1.164  
   1.165 -#if 0
   1.166 -    apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n");
   1.167 -#endif
   1.168      printk("Calibrating APIC timer for CPU%d...\n",  smp_processor_id());
   1.169  
   1.170      /*
   1.171 @@ -721,14 +663,13 @@ int __init calibrate_APIC_clock(void)
   1.172       * for a wraparound to start exact measurement:
   1.173       * (the current tick might have been already half done)
   1.174       */
   1.175 -
   1.176      wait_timer_tick();
   1.177  
   1.178      /*
   1.179       * We wrapped around just now. Let's start:
   1.180       */
   1.181      if (cpu_has_tsc)
   1.182 -    rdtscll(t1);
   1.183 +        rdtscll(t1);
   1.184      tt1 = apic_read(APIC_TMCCT);
   1.185  
   1.186      /*
   1.187 @@ -739,14 +680,13 @@ int __init calibrate_APIC_clock(void)
   1.188  
   1.189      tt2 = apic_read(APIC_TMCCT);
   1.190      if (cpu_has_tsc)
   1.191 -    rdtscll(t2);
   1.192 +        rdtscll(t2);
   1.193  
   1.194      /*
   1.195       * The APIC bus clock counter is 32 bits only, it
   1.196       * might have overflown, but note that we use signed
   1.197       * longs, thus no extra care needed.
   1.198 -     *
   1.199 -     * underflown to be exact, as the timer counts down ;)
   1.200 +     * [underflown to be exact, as the timer counts down ;)]
   1.201       */
   1.202  
   1.203      result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
   1.204 @@ -861,7 +801,6 @@ void smp_apic_timer_interrupt(struct xen
   1.205      raise_softirq(AC_TIMER_SOFTIRQ);
   1.206  }
   1.207  
   1.208 -
   1.209  /*
   1.210   * This interrupt should _never_ happen with our APIC/SMP architecture
   1.211   */
   1.212 @@ -869,9 +808,6 @@ asmlinkage void smp_spurious_interrupt(s
   1.213  {
   1.214      unsigned long v;
   1.215  
   1.216 -#if 0
   1.217 -    irq_enter();
   1.218 -#endif
   1.219      /*
   1.220       * Check if this really is a spurious interrupt and ACK it
   1.221       * if it is a vectored one.  Just in case...
   1.222 @@ -884,9 +820,6 @@ asmlinkage void smp_spurious_interrupt(s
   1.223      /* see sw-dev-man vol 3, chapter 7.4.13.5 */
   1.224      printk("spurious APIC interrupt on CPU#%d, should never happen.\n",
   1.225             smp_processor_id());
   1.226 -#if 0
   1.227 -    irq_exit();
   1.228 -#endif
   1.229  }
   1.230  
   1.231  /*
   1.232 @@ -897,9 +830,6 @@ asmlinkage void smp_error_interrupt(stru
   1.233  {
   1.234      unsigned long v, v1;
   1.235  
   1.236 -#if 0
   1.237 -    irq_enter();
   1.238 -#endif
   1.239      /* First tickle the hardware, only then report what went on. -- REW */
   1.240      v = apic_read(APIC_ESR);
   1.241      apic_write(APIC_ESR, 0);
   1.242 @@ -917,11 +847,8 @@ asmlinkage void smp_error_interrupt(stru
   1.243         6: Received illegal vector
   1.244         7: Illegal register address
   1.245      */
   1.246 -    Dprintk("APIC error on CPU%d: %02lx(%02lx)\n",
   1.247 -            smp_processor_id(), v , v1);
   1.248 -#if 0
   1.249 -    irq_exit();
   1.250 -#endif
   1.251 +    printk("APIC error on CPU%d: %02lx(%02lx)\n",
   1.252 +            smp_processor_id(), v, v1);
   1.253  }
   1.254  
   1.255  /*
   1.256 @@ -930,11 +857,6 @@ asmlinkage void smp_error_interrupt(stru
   1.257   */
   1.258  int __init APIC_init_uniprocessor (void)
   1.259  {
   1.260 -#if 0
   1.261 -    if (enable_local_apic < 0)
   1.262 -        clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
   1.263 -#endif
   1.264 -
   1.265      if (!smp_found_config && !cpu_has_apic)
   1.266          return -1;
   1.267  
   1.268 @@ -954,25 +876,15 @@ int __init APIC_init_uniprocessor (void)
   1.269  #ifdef CONFIG_SMP
   1.270      cpu_online_map = 1;
   1.271  #endif
   1.272 -#if 0
   1.273 -    phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
   1.274 -#endif
   1.275      phys_cpu_present_map = 1;
   1.276      apic_write_around(APIC_ID, boot_cpu_physical_apicid);
   1.277  
   1.278      setup_local_APIC();
   1.279  
   1.280 -#if 0
   1.281 -    if (nmi_watchdog == NMI_LOCAL_APIC)
   1.282 -        check_nmi_watchdog();
   1.283 -#endif
   1.284  #ifdef CONFIG_X86_IO_APIC
   1.285      if (smp_found_config)
   1.286          if (!skip_ioapic_setup && nr_ioapics)
   1.287 -        setup_IO_APIC();
   1.288 -#endif
   1.289 -#if 0
   1.290 -    setup_boot_APIC_clock();
   1.291 +            setup_IO_APIC();
   1.292  #endif
   1.293      setup_APIC_clocks();
   1.294  
     2.1 --- a/xen/arch/x86/smpboot.c	Thu Apr 21 12:12:12 2005 +0000
     2.2 +++ b/xen/arch/x86/smpboot.c	Thu Apr 21 14:19:31 2005 +0000
     2.3 @@ -361,9 +361,6 @@ void __init smp_callin(void)
     2.4       */
     2.5      smp_store_cpu_info(cpuid);
     2.6  
     2.7 -    if (nmi_watchdog == NMI_LOCAL_APIC)
     2.8 -        setup_apic_nmi_watchdog();
     2.9 -
    2.10      /*
    2.11       * Allow the master to continue.
    2.12       */