1.1 --- a/xen/arch/ia64/process.c	Fri Apr 15 22:52:25 2005 +0000
     1.2 +++ b/xen/arch/ia64/process.c	Wed Apr 20 18:12:03 2005 +0000
     1.3 @@ -171,6 +171,10 @@ panic_domain(regs,"psr.ic off, deliverin
     1.4  		else if (vector == IA64_INST_TLB_VECTOR)
     1.5  			vector = IA64_ALT_INST_TLB_VECTOR;
     1.6  //	}
     1.7 +	if (vector == IA64_ALT_DATA_TLB_VECTOR ||
     1.8 +	    vector == IA64_ALT_INST_TLB_VECTOR) {
     1.9 +		vcpu_thash(ed,ifa,&PSCB(ed,iha));
    1.10 +	}
    1.11  	PSCB(ed,unat) = regs->ar_unat;  // not sure if this is really needed?
    1.12  	PSCB(ed,precover_ifs) = regs->cr_ifs;
    1.13  	vcpu_bsw0(ed);

     2.1 --- a/xen/arch/ia64/vcpu.c	Fri Apr 15 22:52:25 2005 +0000
     2.2 +++ b/xen/arch/ia64/vcpu.c	Wed Apr 20 18:12:03 2005 +0000
     2.3 @@ -394,7 +394,10 @@ IA64FAULT vcpu_get_iim(VCPU *vcpu, UINT6
     2.4  
     2.5  IA64FAULT vcpu_get_iha(VCPU *vcpu, UINT64 *pval)
     2.6  {
     2.7 -	return vcpu_thash(vcpu,PSCB(vcpu,ifa),pval);
     2.8 +	//return vcpu_thash(vcpu,PSCB(vcpu,ifa),pval);
     2.9 +	UINT64 val = PSCB(vcpu,iha);
    2.10 +	*pval = val;
    2.11 +	return (IA64_NO_FAULT);
    2.12  }
    2.13  
    2.14  IA64FAULT vcpu_set_dcr(VCPU *vcpu, UINT64 val)
    2.15 @@ -1138,11 +1141,13 @@ IA64FAULT vcpu_thash(VCPU *vcpu, UINT64 
    2.16  	UINT64 VHPT_addr = VHPT_addr1 | ((VHPT_addr2a | VHPT_addr2b) << 15) |
    2.17  			VHPT_addr3;
    2.18  
    2.19 +#if 0
    2.20  	if (VHPT_addr1 == 0xe000000000000000L) {
    2.21  	    printf("vcpu_thash: thash unsupported with rr7 @%lx\n",
    2.22  		PSCB(vcpu,iip));
    2.23  	    return (IA64_ILLOP_FAULT);
    2.24  	}
    2.25 +#endif
    2.26  //verbose("vcpu_thash: vadr=%p, VHPT_addr=%p\n",vadr,VHPT_addr);
    2.27  	*pval = VHPT_addr;
    2.28  	return (IA64_NO_FAULT);