debuggers.hg

changeset 22693:852d87e0480b

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x86: Allow dom0 to write MSR IA32_ENERGY_PERF_BIAS

Allow dom0 to write MSR IA32_ENERGY_PERF_BIAS

There is a new hardware feature, which lets system software to set
Energy Performance Preference. This is a opaque knob in the form of
IA32_ENERGY_PERF_BIAS MSR, which has a 4 bit Energy Performance
Preference Hint.

The support for this feature is indicated by CPUID.06H.ECX.bit3. Refer
to Intel Architectures Software Developer's Manual for more info.

Let dom0 tools to control it.

Signed-off-by: Wei Gang <gang.wei@intel.com>
author Keir Fraser <keir@xen.org>
date Wed Jan 05 09:52:18 2011 +0000 (2011-01-05)
parents e635e6641c07
children 41a259d7a33d
files xen/arch/x86/traps.c xen/include/asm-x86/msr-index.h
line diff
     1.1 --- a/xen/arch/x86/traps.c	Wed Jan 05 09:50:21 2011 +0000
     1.2 +++ b/xen/arch/x86/traps.c	Wed Jan 05 09:52:18 2011 +0000
     1.3 @@ -2333,6 +2333,7 @@ static int emulate_privileged_op(struct 
     1.4                  goto fail;
     1.5              break;
     1.6          case MSR_IA32_THERM_CONTROL:
     1.7 +        case MSR_IA32_ENERGY_PERF_BIAS:
     1.8              if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL )
     1.9                  goto fail;
    1.10              if ( (v->domain->domain_id != 0) || !v->domain->is_pinned )

     2.1 --- a/xen/include/asm-x86/msr-index.h	Wed Jan 05 09:50:21 2011 +0000
     2.2 +++ b/xen/include/asm-x86/msr-index.h	Wed Jan 05 09:52:18 2011 +0000
     2.3 @@ -330,6 +330,7 @@
     2.4  #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23)
     2.5  
     2.6  #define MSR_IA32_TSC_DEADLINE		0x000006E0
     2.7 +#define MSR_IA32_ENERGY_PERF_BIAS	0x000001b0
     2.8  
     2.9  /* Intel Model 6 */
    2.10  #define MSR_P6_EVNTSEL0			0x00000186