debuggers.hg

changeset 19985:855d0f17e364

i386: eliminate unsupported CPUs' MCA handling code

Neither Intel P5 nor Winchip are supported by Xen (due to
-march=i686 being passed to the compiler), so there is no point in
having code for handling their (rudimentary) MCA capabilities.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Jul 15 14:35:34 2009 +0100 (2009-07-15)
parents 91407452cdb6
children bc80ccb79c5b
files xen/arch/x86/cpu/mcheck/Makefile xen/arch/x86/cpu/mcheck/mce.c xen/arch/x86/cpu/mcheck/mce.h xen/arch/x86/cpu/mcheck/p5.c xen/arch/x86/cpu/mcheck/winchip.c
line diff
     1.1 --- a/xen/arch/x86/cpu/mcheck/Makefile	Wed Jul 15 13:15:50 2009 +0100
     1.2 +++ b/xen/arch/x86/cpu/mcheck/Makefile	Wed Jul 15 14:35:34 2009 +0100
     1.3 @@ -6,5 +6,3 @@ obj-y += mctelem.o
     1.4  obj-y += mce.o
     1.5  obj-y += mce_intel.o
     1.6  obj-y += non-fatal.o
     1.7 -obj-$(x86_32) += p5.o
     1.8 -obj-$(x86_32) += winchip.o
     2.1 --- a/xen/arch/x86/cpu/mcheck/mce.c	Wed Jul 15 13:15:50 2009 +0100
     2.2 +++ b/xen/arch/x86/cpu/mcheck/mce.c	Wed Jul 15 14:35:34 2009 +0100
     2.3 @@ -616,12 +616,6 @@ void mcheck_init(struct cpuinfo_x86 *c)
     2.4  
     2.5  	case X86_VENDOR_INTEL:
     2.6  		switch (c->x86) {
     2.7 -		case 5:
     2.8 -#ifndef CONFIG_X86_64
     2.9 -			inited = intel_p5_mcheck_init(c);
    2.10 -#endif
    2.11 -			break;
    2.12 -
    2.13  		case 6:
    2.14  		case 15:
    2.15  			inited = intel_mcheck_init(c);
    2.16 @@ -629,14 +623,6 @@ void mcheck_init(struct cpuinfo_x86 *c)
    2.17  		}
    2.18  		break;
    2.19  
    2.20 -#ifndef CONFIG_X86_64
    2.21 -	case X86_VENDOR_CENTAUR:
    2.22 -		if (c->x86==5) {
    2.23 -			inited = winchip_mcheck_init(c);
    2.24 -		}
    2.25 -		break;
    2.26 -#endif
    2.27 -
    2.28  	default:
    2.29  		break;
    2.30  	}
     3.1 --- a/xen/arch/x86/cpu/mcheck/mce.h	Wed Jul 15 13:15:50 2009 +0100
     3.2 +++ b/xen/arch/x86/cpu/mcheck/mce.h	Wed Jul 15 14:35:34 2009 +0100
     3.3 @@ -17,8 +17,6 @@ int amd_k7_mcheck_init(struct cpuinfo_x8
     3.4  int amd_k8_mcheck_init(struct cpuinfo_x86 *c);
     3.5  int amd_f10_mcheck_init(struct cpuinfo_x86 *c);
     3.6  
     3.7 -int intel_p5_mcheck_init(struct cpuinfo_x86 *c);
     3.8 -int winchip_mcheck_init(struct cpuinfo_x86 *c);
     3.9  int intel_mcheck_init(struct cpuinfo_x86 *c);
    3.10  
    3.11  void intel_mcheck_timer(struct cpuinfo_x86 *c);
     4.1 --- a/xen/arch/x86/cpu/mcheck/p5.c	Wed Jul 15 13:15:50 2009 +0100
     4.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.3 @@ -1,50 +0,0 @@
     4.4 -/*
     4.5 - * P5 specific Machine Check Exception Reporting
     4.6 - * (C) Copyright 2002 Alan Cox <alan@redhat.com>
     4.7 - */
     4.8 -
     4.9 -#include <xen/init.h>
    4.10 -#include <xen/types.h>
    4.11 -#include <xen/kernel.h>
    4.12 -#include <xen/smp.h>
    4.13 -
    4.14 -#include <asm/processor.h> 
    4.15 -#include <asm/system.h>
    4.16 -#include <asm/msr.h>
    4.17 -
    4.18 -#include "mce.h"
    4.19 -#include "x86_mca.h"
    4.20 -
    4.21 -/* Machine check handler for Pentium class Intel */
    4.22 -static void pentium_machine_check(struct cpu_user_regs * regs, long error_code)
    4.23 -{
    4.24 -	u32 loaddr, hi, lotype;
    4.25 -	rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
    4.26 -	rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
    4.27 -	printk(KERN_EMERG "CPU#%d: Machine Check Exception:  0x%8X (type 0x%8X).\n", smp_processor_id(), loaddr, lotype);
    4.28 -	if(lotype&(1<<5))
    4.29 -		printk(KERN_EMERG "CPU#%d: Possible thermal failure (CPU on fire ?).\n", smp_processor_id());
    4.30 -	add_taint(TAINT_MACHINE_CHECK);
    4.31 -}
    4.32 -
    4.33 -/* Set up machine check reporting for processors with Intel style MCE */
    4.34 -int intel_p5_mcheck_init(struct cpuinfo_x86 *c)
    4.35 -{
    4.36 -	u32 l, h;
    4.37 -	
    4.38 -	/* Default P5 to off as its often misconnected */
    4.39 -	if(mce_disabled != -1)
    4.40 -		return 0;
    4.41 -	x86_mce_vector_register(pentium_machine_check);
    4.42 -
    4.43 -	/* Read registers before enabling */
    4.44 -	rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
    4.45 -	rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
    4.46 -	printk(KERN_INFO "Intel old style machine check architecture supported.\n");
    4.47 -
    4.48 - 	/* Enable MCE */
    4.49 -	set_in_cr4(X86_CR4_MCE);
    4.50 -	printk(KERN_INFO "Intel old style machine check reporting enabled on CPU#%d.\n", smp_processor_id());
    4.51 -
    4.52 -	return 1;
    4.53 -}
     5.1 --- a/xen/arch/x86/cpu/mcheck/winchip.c	Wed Jul 15 13:15:50 2009 +0100
     5.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.3 @@ -1,39 +0,0 @@
     5.4 -/*
     5.5 - * IDT Winchip specific Machine Check Exception Reporting
     5.6 - * (C) Copyright 2002 Alan Cox <alan@redhat.com>
     5.7 - */
     5.8 -
     5.9 -#include <xen/config.h>
    5.10 -#include <xen/init.h>
    5.11 -#include <xen/lib.h>
    5.12 -#include <xen/types.h>
    5.13 -#include <xen/kernel.h>
    5.14 -
    5.15 -#include <asm/processor.h> 
    5.16 -#include <asm/system.h>
    5.17 -#include <asm/msr.h>
    5.18 -
    5.19 -#include "mce.h"
    5.20 -
    5.21 -/* Machine check handler for WinChip C6 */
    5.22 -static void winchip_machine_check(struct cpu_user_regs * regs, long error_code)
    5.23 -{
    5.24 -	printk(KERN_EMERG "CPU0: Machine Check Exception.\n");
    5.25 -	add_taint(TAINT_MACHINE_CHECK);
    5.26 -}
    5.27 -
    5.28 -/* Set up machine check reporting on the Winchip C6 series */
    5.29 -int winchip_mcheck_init(struct cpuinfo_x86 *c)
    5.30 -{
    5.31 -	u32 lo, hi;
    5.32 -
    5.33 -	wmb();
    5.34 -	x86_mce_vector_register(winchip_machine_check);
    5.35 -	rdmsr(MSR_IDT_FCR1, lo, hi);
    5.36 -	lo|= (1<<2);	/* Enable EIERRINT (int 18 MCE) */
    5.37 -	lo&= ~(1<<4);	/* Enable MCE */
    5.38 -	wrmsr(MSR_IDT_FCR1, lo, hi);
    5.39 -	set_in_cr4(X86_CR4_MCE);
    5.40 -	printk(KERN_INFO "Winchip machine check reporting enabled on CPU#0.\n");
    5.41 -	return (1);
    5.42 -}