debuggers.hg

changeset 22277:a1405385db77

x86: emulate MSR_IA32_UCODE_REV Intel access protocol

Intel requires a write of zeros (hence such writes now get silently
ignored) followed by a cpuid(1) followed by the actual read.

Includes some code redundancy elimination possible after the actual
change.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir@xen.org>
date Mon Oct 11 09:01:45 2010 +0100 (2010-10-11)
parents a33886146b45
children eb964c4b4f31
files xen/arch/x86/traps.c
line diff
     1.1 --- a/xen/arch/x86/traps.c	Fri Oct 08 11:41:57 2010 +0100
     1.2 +++ b/xen/arch/x86/traps.c	Mon Oct 11 09:01:45 2010 +0100
     1.3 @@ -2276,6 +2276,14 @@ static int emulate_privileged_op(struct 
     1.4              if ( wrmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, msr_content) != 0 )
     1.5                  goto fail;
     1.6              break;
     1.7 +        case MSR_IA32_UCODE_REV:
     1.8 +            if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL )
     1.9 +                goto fail;
    1.10 +            if ( rdmsr_safe(regs->ecx, val) )
    1.11 +                goto fail;
    1.12 +            if ( msr_content )
    1.13 +                goto invalid;
    1.14 +            break;
    1.15          case MSR_IA32_MISC_ENABLE:
    1.16              if ( rdmsr_safe(regs->ecx, val) )
    1.17                  goto invalid;
    1.18 @@ -2382,11 +2390,16 @@ static int emulate_privileged_op(struct 
    1.19                  regs->eax = regs->edx = 0;
    1.20                  break;
    1.21              }
    1.22 -            if ( rdmsr_safe(regs->ecx, msr_content) != 0 )
    1.23 -                goto fail;
    1.24 -            regs->eax = (uint32_t)msr_content;
    1.25 -            regs->edx = (uint32_t)(msr_content >> 32);
    1.26 -            break;
    1.27 +            goto rdmsr_normal;
    1.28 +        case MSR_IA32_UCODE_REV:
    1.29 +            BUILD_BUG_ON(MSR_IA32_UCODE_REV != MSR_AMD_PATCHLEVEL);
    1.30 +            if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
    1.31 +            {
    1.32 +                if ( wrmsr_safe(MSR_IA32_UCODE_REV, 0) )
    1.33 +                    goto fail;
    1.34 +                sync_core();
    1.35 +            }
    1.36 +            goto rdmsr_normal;
    1.37          case MSR_IA32_MISC_ENABLE:
    1.38              if ( rdmsr_safe(regs->ecx, msr_content) )
    1.39                  goto fail;
    1.40 @@ -2394,8 +2407,6 @@ static int emulate_privileged_op(struct 
    1.41              regs->eax = (uint32_t)msr_content;
    1.42              regs->edx = (uint32_t)(msr_content >> 32);
    1.43              break;
    1.44 -        case MSR_EFER:
    1.45 -        case MSR_AMD_PATCHLEVEL:
    1.46          default:
    1.47              if ( rdmsr_hypervisor_regs(regs->ecx, &val) )
    1.48              {
    1.49 @@ -2411,6 +2422,8 @@ static int emulate_privileged_op(struct 
    1.50              if ( rc )
    1.51                  goto rdmsr_writeback;
    1.52  
    1.53 +        case MSR_EFER:
    1.54 + rdmsr_normal:
    1.55              /* Everyone can read the MSR space. */
    1.56              /* gdprintk(XENLOG_WARNING,"Domain attempted RDMSR %p.\n",
    1.57                          _p(regs->ecx));*/