debuggers.hg

changeset 22733:aa3242c34dda

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Update AMD CPU feature flags 0x80000001:ECX for Xen Hypervisor

This patch syncs-up AMD CPU feature flags 0x80000001:ECX with the
latest Linux kernel. Several new features are added. Some of existing
features' names are changed as well.

Signed-off-by: Wei Huang <wei.huang2@amd.com>
author Keir Fraser <keir@xen.org>
date Sat Jan 08 10:48:46 2011 +0000 (2011-01-08)
parents aec06605e125
children 2a18d709f6e9
files xen/arch/x86/cpu/mcheck/amd_nonfatal.c xen/arch/x86/hvm/svm/svm.c xen/arch/x86/traps.c xen/include/asm-x86/amd.h xen/include/asm-x86/cpufeature.h
line diff
     1.1 --- a/xen/arch/x86/cpu/mcheck/amd_nonfatal.c	Sat Jan 08 10:48:09 2011 +0000
     1.2 +++ b/xen/arch/x86/cpu/mcheck/amd_nonfatal.c	Sat Jan 08 10:48:46 2011 +0000
     1.3 @@ -212,7 +212,7 @@ void amd_nonfatal_mcheck_init(struct cpu
     1.4  
     1.5  	/* The threshold bitfields in MSR_IA32_MC4_MISC has
     1.6  	 * been introduced along with the SVME feature bit. */
     1.7 -	if (variable_period && cpu_has(c, X86_FEATURE_SVME)) {
     1.8 +	if (variable_period && cpu_has(c, X86_FEATURE_SVM)) {
     1.9  		uint64_t value;
    1.10  
    1.11  		/* hw threshold registers present */

     2.1 --- a/xen/arch/x86/hvm/svm/svm.c	Sat Jan 08 10:48:09 2011 +0000
     2.2 +++ b/xen/arch/x86/hvm/svm/svm.c	Sat Jan 08 10:48:46 2011 +0000
     2.3 @@ -919,7 +919,7 @@ struct hvm_function_table * __init start
     2.4  {
     2.5      bool_t printed = 0;
     2.6  
     2.7 -    if ( !test_bit(X86_FEATURE_SVME, &boot_cpu_data.x86_capability) )
     2.8 +    if ( !test_bit(X86_FEATURE_SVM, &boot_cpu_data.x86_capability) )
     2.9          return NULL;
    2.10  
    2.11      if ( svm_cpu_up() )

     3.1 --- a/xen/arch/x86/traps.c	Sat Jan 08 10:48:09 2011 +0000
     3.2 +++ b/xen/arch/x86/traps.c	Sat Jan 08 10:48:46 2011 +0000
     3.3 @@ -795,9 +795,9 @@ static void pv_cpuid(struct cpu_user_reg
     3.4          __clear_bit(X86_FEATURE_PAGE1GB % 32, &d);
     3.5          __clear_bit(X86_FEATURE_RDTSCP % 32, &d);
     3.6  
     3.7 -        __clear_bit(X86_FEATURE_SVME % 32, &c);
     3.8 +        __clear_bit(X86_FEATURE_SVM % 32, &c);
     3.9          if ( !cpu_has_apic )
    3.10 -           __clear_bit(X86_FEATURE_EXTAPICSPACE % 32, &c);
    3.11 +           __clear_bit(X86_FEATURE_EXTAPIC % 32, &c);
    3.12          __clear_bit(X86_FEATURE_OSVW % 32, &c);
    3.13          __clear_bit(X86_FEATURE_IBS % 32, &c);
    3.14          __clear_bit(X86_FEATURE_SKINIT % 32, &c);

     4.1 --- a/xen/include/asm-x86/amd.h	Sat Jan 08 10:48:09 2011 +0000
     4.2 +++ b/xen/include/asm-x86/amd.h	Sat Jan 08 10:48:46 2011 +0000
     4.3 @@ -63,8 +63,8 @@
     4.4  	__bit(X86_FEATURE_CX16))
     4.5  #define AMD_FEATURES_K8_REV_F_EDX         AMD_FEATURES_K8_REV_E_EDX
     4.6  #define AMD_EXTFEATURES_K8_REV_F_ECX     (AMD_EXTFEATURES_K8_REV_E_ECX |\
     4.7 -	__bit(X86_FEATURE_SVME) | __bit(X86_FEATURE_EXTAPICSPACE) |	\
     4.8 -	__bit(X86_FEATURE_ALTMOVCR))
     4.9 +	__bit(X86_FEATURE_SVM) | __bit(X86_FEATURE_EXTAPIC) |	        \
    4.10 +	__bit(X86_FEATURE_CR8_LEGACY))
    4.11  #define AMD_EXTFEATURES_K8_REV_F_EDX     (AMD_EXTFEATURES_K8_REV_E_EDX |\
    4.12  	__bit(X86_FEATURE_RDTSCP))
    4.13  
    4.14 @@ -72,7 +72,7 @@
    4.15  #define AMD_FEATURES_K8_REV_G_ECX         AMD_FEATURES_K8_REV_F_ECX
    4.16  #define AMD_FEATURES_K8_REV_G_EDX         AMD_FEATURES_K8_REV_F_EDX
    4.17  #define AMD_EXTFEATURES_K8_REV_G_ECX     (AMD_EXTFEATURES_K8_REV_F_ECX |\
    4.18 -	__bit(X86_FEATURE_3DNOWPF))
    4.19 +	__bit(X86_FEATURE_3DNOWPREFETCH))
    4.20  #define AMD_EXTFEATURES_K8_REV_G_EDX      AMD_EXTFEATURES_K8_REV_F_EDX
    4.21  
    4.22  /* Family 10h, Revision B */

     5.1 --- a/xen/include/asm-x86/cpufeature.h	Sat Jan 08 10:48:09 2011 +0000
     5.2 +++ b/xen/include/asm-x86/cpufeature.h	Sat Jan 08 10:48:46 2011 +0000
     5.3 @@ -118,20 +118,25 @@
     5.4  #define X86_FEATURE_PMM_EN	(5*32+ 13) /* PMM enabled */
     5.5  
     5.6  /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
     5.7 -#define X86_FEATURE_LAHF_LM	(6*32+ 0) /* LAHF/SAHF in long mode */
     5.8 -#define X86_FEATURE_CMP_LEGACY	(6*32+ 1) /* If yes HyperThreading not valid */
     5.9 -#define X86_FEATURE_SVME        (6*32+ 2) /* Secure Virtual Machine */
    5.10 -#define X86_FEATURE_EXTAPICSPACE (6*32+ 3) /* Extended APIC space */
    5.11 -#define X86_FEATURE_ALTMOVCR	(6*32+ 4) /* LOCK MOV CR accesses CR+8 */
    5.12 -#define X86_FEATURE_ABM		(6*32+ 5) /* Advanced Bit Manipulation */
    5.13 -#define X86_FEATURE_SSE4A	(6*32+ 6) /* AMD Streaming SIMD Extensions-4a */
    5.14 -#define X86_FEATURE_MISALIGNSSE	(6*32+ 7) /* Misaligned SSE Access */
    5.15 -#define X86_FEATURE_3DNOWPF	(6*32+ 8) /* 3DNow! Prefetch */
    5.16 -#define X86_FEATURE_OSVW	(6*32+ 9) /* OS Visible Workaround */
    5.17 -#define X86_FEATURE_IBS		(6*32+ 10) /* Instruction Based Sampling */
    5.18 -#define X86_FEATURE_SSE5	(6*32+ 11) /* AMD Streaming SIMD Extensions-5 */
    5.19 -#define X86_FEATURE_SKINIT	(6*32+ 12) /* SKINIT, STGI/CLGI, DEV */
    5.20 -#define X86_FEATURE_WDT		(6*32+ 13) /* Watchdog Timer */
    5.21 +#define X86_FEATURE_LAHF_LM     (6*32+ 0) /* LAHF/SAHF in long mode */
    5.22 +#define X86_FEATURE_CMP_LEGACY  (6*32+ 1) /* If yes HyperThreading not valid */
    5.23 +#define X86_FEATURE_SVM         (6*32+ 2) /* Secure virtual machine */
    5.24 +#define X86_FEATURE_EXTAPIC     (6*32+ 3) /* Extended APIC space */
    5.25 +#define X86_FEATURE_CR8_LEGACY  (6*32+ 4) /* CR8 in 32-bit mode */
    5.26 +#define X86_FEATURE_ABM         (6*32+ 5) /* Advanced bit manipulation */
    5.27 +#define X86_FEATURE_SSE4A       (6*32+ 6) /* SSE-4A */
    5.28 +#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
    5.29 +#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
    5.30 +#define X86_FEATURE_OSVW        (6*32+ 9) /* OS Visible Workaround */
    5.31 +#define X86_FEATURE_IBS         (6*32+10) /* Instruction Based Sampling */
    5.32 +#define X86_FEATURE_XOP         (6*32+11) /* extended AVX instructions */
    5.33 +#define X86_FEATURE_SKINIT      (6*32+12) /* SKINIT/STGI instructions */
    5.34 +#define X86_FEATURE_WDT         (6*32+13) /* Watchdog timer */
    5.35 +#define X86_FEATURE_LWP         (6*32+15) /* Light Weight Profiling */
    5.36 +#define X86_FEATURE_FMA4        (6*32+16) /* 4 operands MAC instructions */
    5.37 +#define X86_FEATURE_NODEID_MSR  (6*32+19) /* NodeId MSR */
    5.38 +#define X86_FEATURE_TBM         (6*32+21) /* trailing bit manipulations */
    5.39 +#define X86_FEATURE_TOPOEXT     (6*32+22) /* topology extensions CPUID leafs */
    5.40  
    5.41  /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
    5.42  #define X86_FEATURE_FSGSBASE	(7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */