debuggers.hg

changeset 656:c7557b3832b9

bitkeeper revision 1.339.1.6 (3f12cffdzSdqoflJR3gfS-S45xcteA)

nmi.c:
new file
Many files:
NMI watchdog support in Xen.
author kaf24@scramble.cl.cam.ac.uk
date Mon Jul 14 15:45:01 2003 +0000 (2003-07-14)
parents ef9e002c0596
children c085fac641e2 89575098aa97
files .rootkeys xen/arch/i386/apic.c xen/arch/i386/entry.S xen/arch/i386/io_apic.c xen/arch/i386/nmi.c xen/arch/i386/setup.c xen/arch/i386/traps.c xen/include/asm-i386/hardirq.h xen/include/asm-i386/msr.h xen/include/xeno/irq_cpustat.h
line diff
     1.1 --- a/.rootkeys	Mon Jul 14 14:33:54 2003 +0000
     1.2 +++ b/.rootkeys	Mon Jul 14 15:45:01 2003 +0000
     1.3 @@ -159,6 +159,7 @@ 3ddb79bc1uNlAtc-84Ioq4qfcnI_CQ xen/arch/
     1.4  3ddb79bdqfIcjkz_h9Hvtp8Tk_19Zw xen/arch/i386/irq.c
     1.5  3ddb79bcHwuCQDjBICDTSis52hWguw xen/arch/i386/mm.c
     1.6  3ddb79bdS4UeWWXDH-FaBKqcpMFcnw xen/arch/i386/mpparse.c
     1.7 +3f12cff65EV3qOG2j37Qm0ShgvXGRw xen/arch/i386/nmi.c
     1.8  3ddb79bcnL-_Dtsbtjgxl7vJU3vBiQ xen/arch/i386/pci-dma.c
     1.9  3ddb79bdeJ7_86z03yTAPIeeywOg3Q xen/arch/i386/pci-i386.c
    1.10  3ddb79bdIKgipvGoqExEQ7jawfVowA xen/arch/i386/pci-i386.h
     2.1 --- a/xen/arch/i386/apic.c	Mon Jul 14 14:33:54 2003 +0000
     2.2 +++ b/xen/arch/i386/apic.c	Mon Jul 14 15:45:01 2003 +0000
     2.3 @@ -353,6 +353,9 @@ void __init setup_local_APIC (void)
     2.4      } else {
     2.5          printk("No ESR for 82489DX.\n");
     2.6      }
     2.7 +
     2.8 +	if (nmi_watchdog == NMI_LOCAL_APIC)
     2.9 +		setup_apic_nmi_watchdog();
    2.10  }
    2.11  
    2.12  
    2.13 @@ -413,6 +416,8 @@ static int __init detect_init_APIC (void
    2.14      set_bit(X86_FEATURE_APIC, &boot_cpu_data.x86_capability);
    2.15      mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
    2.16      boot_cpu_physical_apicid = 0;
    2.17 +	if (nmi_watchdog != NMI_NONE)
    2.18 +		nmi_watchdog = NMI_LOCAL_APIC;
    2.19  
    2.20      printk("Found and enabled local APIC!\n");
    2.21      apic_pm_init1();
     3.1 --- a/xen/arch/i386/entry.S	Mon Jul 14 14:33:54 2003 +0000
     3.2 +++ b/xen/arch/i386/entry.S	Mon Jul 14 15:45:01 2003 +0000
     3.3 @@ -131,7 +131,7 @@ CF_MASK		= 0x00000001
     3.4  IF_MASK		= 0x00000200
     3.5  NT_MASK		= 0x00004000
     3.6  
     3.7 -#define SAVE_ALL \
     3.8 +#define SAVE_ALL_NOSTI \
     3.9  	cld; \
    3.10  	pushl %gs; \
    3.11  	pushl %fs; \
    3.12 @@ -146,8 +146,11 @@ NT_MASK		= 0x00004000
    3.13  	pushl %ebx; \
    3.14  	movl $(__HYPERVISOR_DS),%edx; \
    3.15  	movl %edx,%ds; \
    3.16 -	movl %edx,%es; \
    3.17 -        sti; 
    3.18 +	movl %edx,%es;
    3.19 +
    3.20 +#define SAVE_ALL \
    3.21 +	SAVE_ALL_NOSTI \
    3.22 +	sti;
    3.23  
    3.24  #define RESTORE_ALL	\
    3.25  	popl %ebx;	\
    3.26 @@ -554,7 +557,7 @@ ENTRY(debug)
    3.27  
    3.28  ENTRY(nmi)
    3.29  	pushl %eax
    3.30 -	SAVE_ALL
    3.31 +	SAVE_ALL_NOSTI
    3.32  	movl %esp,%edx
    3.33  	pushl $0
    3.34  	pushl %edx
     4.1 --- a/xen/arch/i386/io_apic.c	Mon Jul 14 14:33:54 2003 +0000
     4.2 +++ b/xen/arch/i386/io_apic.c	Mon Jul 14 15:45:01 2003 +0000
     4.3 @@ -34,8 +34,6 @@
     4.4  
     4.5  #ifdef CONFIG_X86_IO_APIC
     4.6  
     4.7 -static unsigned int nmi_watchdog;  /* XXXX XEN */
     4.8 -
     4.9  #undef APIC_LOCKUP_DEBUG
    4.10  
    4.11  #define APIC_LOCKUP_DEBUG
    4.12 @@ -1641,15 +1639,8 @@ static inline void check_timer(void)
    4.13  		 * Ok, does IRQ0 through the IOAPIC work?
    4.14  		 */
    4.15  		unmask_IO_APIC_irq(0);
    4.16 -		if (timer_irq_works()) {
    4.17 -			if (nmi_watchdog == NMI_IO_APIC) {
    4.18 -				disable_8259A_irq(0);
    4.19 -				setup_nmi();
    4.20 -				enable_8259A_irq(0);
    4.21 -				// XXX Xen check_nmi_watchdog();
    4.22 -			}
    4.23 +		if (timer_irq_works())
    4.24  			return;
    4.25 -		}
    4.26  		clear_IO_APIC_pin(0, pin1);
    4.27  		printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
    4.28  	}
    4.29 @@ -1667,10 +1658,6 @@ static inline void check_timer(void)
    4.30  				replace_pin_at_irq(0, 0, pin1, 0, pin2);
    4.31  			else
    4.32  				add_pin_to_irq(0, 0, pin2);
    4.33 -			if (nmi_watchdog == NMI_IO_APIC) {
    4.34 -				setup_nmi();
    4.35 -				// XXX Xen check_nmi_watchdog();
    4.36 -			}
    4.37  			return;
    4.38  		}
    4.39  		/*
    4.40 @@ -1680,11 +1667,6 @@ static inline void check_timer(void)
    4.41  	}
    4.42  	printk(" failed.\n");
    4.43  
    4.44 -	if (nmi_watchdog) {
    4.45 -		printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
    4.46 -		nmi_watchdog = 0;
    4.47 -	}
    4.48 -
    4.49  	printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
    4.50  
    4.51  	disable_8259A_irq(0);
     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/xen/arch/i386/nmi.c	Mon Jul 14 15:45:01 2003 +0000
     5.3 @@ -0,0 +1,275 @@
     5.4 +/*
     5.5 + *  linux/arch/i386/nmi.c
     5.6 + *
     5.7 + *  NMI watchdog support on APIC systems
     5.8 + *
     5.9 + *  Started by Ingo Molnar <mingo@redhat.com>
    5.10 + *
    5.11 + *  Fixes:
    5.12 + *  Mikael Pettersson	: AMD K7 support for local APIC NMI watchdog.
    5.13 + *  Mikael Pettersson	: Power Management for local APIC NMI watchdog.
    5.14 + *  Mikael Pettersson	: Pentium 4 support for local APIC NMI watchdog.
    5.15 + */
    5.16 +
    5.17 +#include <linux/config.h>
    5.18 +#include <linux/init.h>
    5.19 +#include <linux/lib.h>
    5.20 +#include <linux/mm.h>
    5.21 +#include <linux/irq.h>
    5.22 +#include <linux/delay.h>
    5.23 +#include <linux/interrupt.h>
    5.24 +#include <linux/time.h>
    5.25 +#include <linux/timex.h>
    5.26 +#include <linux/sched.h>
    5.27 +
    5.28 +#include <asm/mc146818rtc.h>
    5.29 +#include <asm/smp.h>
    5.30 +#include <asm/msr.h>
    5.31 +#include <asm/mpspec.h>
    5.32 +
    5.33 +#undef Dprintk
    5.34 +#define Dprintk(x...) printk(x)
    5.35 +
    5.36 +unsigned int nmi_watchdog = NMI_LOCAL_APIC;
    5.37 +static unsigned int nmi_hz = HZ;
    5.38 +unsigned int nmi_perfctr_msr;	/* the MSR to reset in NMI handler */
    5.39 +extern void show_registers(struct pt_regs *regs);
    5.40 +
    5.41 +#define K7_EVNTSEL_ENABLE	(1 << 22)
    5.42 +#define K7_EVNTSEL_INT		(1 << 20)
    5.43 +#define K7_EVNTSEL_OS		(1 << 17)
    5.44 +#define K7_EVNTSEL_USR		(1 << 16)
    5.45 +#define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING	0x76
    5.46 +#define K7_NMI_EVENT		K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
    5.47 +
    5.48 +#define P6_EVNTSEL0_ENABLE	(1 << 22)
    5.49 +#define P6_EVNTSEL_INT		(1 << 20)
    5.50 +#define P6_EVNTSEL_OS		(1 << 17)
    5.51 +#define P6_EVNTSEL_USR		(1 << 16)
    5.52 +#define P6_EVENT_CPU_CLOCKS_NOT_HALTED	0x79
    5.53 +#define P6_NMI_EVENT		P6_EVENT_CPU_CLOCKS_NOT_HALTED
    5.54 +
    5.55 +#define MSR_P4_MISC_ENABLE	0x1A0
    5.56 +#define MSR_P4_MISC_ENABLE_PERF_AVAIL	(1<<7)
    5.57 +#define MSR_P4_MISC_ENABLE_PEBS_UNAVAIL	(1<<12)
    5.58 +#define MSR_P4_PERFCTR0		0x300
    5.59 +#define MSR_P4_CCCR0		0x360
    5.60 +#define P4_ESCR_EVENT_SELECT(N)	((N)<<25)
    5.61 +#define P4_ESCR_OS		(1<<3)
    5.62 +#define P4_ESCR_USR		(1<<2)
    5.63 +#define P4_CCCR_OVF_PMI		(1<<26)
    5.64 +#define P4_CCCR_THRESHOLD(N)	((N)<<20)
    5.65 +#define P4_CCCR_COMPLEMENT	(1<<19)
    5.66 +#define P4_CCCR_COMPARE		(1<<18)
    5.67 +#define P4_CCCR_REQUIRED	(3<<16)
    5.68 +#define P4_CCCR_ESCR_SELECT(N)	((N)<<13)
    5.69 +#define P4_CCCR_ENABLE		(1<<12)
    5.70 +/* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
    5.71 +   CRU_ESCR0 (with any non-null event selector) through a complemented
    5.72 +   max threshold. [IA32-Vol3, Section 14.9.9] */
    5.73 +#define MSR_P4_IQ_COUNTER0	0x30C
    5.74 +#define MSR_P4_IQ_CCCR0		0x36C
    5.75 +#define MSR_P4_CRU_ESCR0	0x3B8
    5.76 +#define P4_NMI_CRU_ESCR0	(P4_ESCR_EVENT_SELECT(0x3F)|P4_ESCR_OS|P4_ESCR_USR)
    5.77 +#define P4_NMI_IQ_CCCR0	\
    5.78 +	(P4_CCCR_OVF_PMI|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT|	\
    5.79 +	 P4_CCCR_COMPARE|P4_CCCR_REQUIRED|P4_CCCR_ESCR_SELECT(4)|P4_CCCR_ENABLE)
    5.80 +
    5.81 +int __init check_nmi_watchdog (void)
    5.82 +{
    5.83 +    unsigned int prev_nmi_count[NR_CPUS];
    5.84 +    int j, cpu;
    5.85 +    
    5.86 +    printk("testing NMI watchdog ---\n");
    5.87 +
    5.88 +    for (j = 0; j < smp_num_cpus; j++) {
    5.89 +        cpu = cpu_logical_map(j);
    5.90 +        prev_nmi_count[cpu] = irq_stat[cpu].__nmi_count;
    5.91 +    }
    5.92 +    sti();
    5.93 +    mdelay((10*1000)/nmi_hz); /* wait 10 ticks */
    5.94 +
    5.95 +    for (j = 0; j < smp_num_cpus; j++) {
    5.96 +        cpu = cpu_logical_map(j);
    5.97 +        if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5)
    5.98 +            printk("CPU#%d: NMI stuck? (Hyperthread secondary CPU?)\n", cpu);
    5.99 +        else
   5.100 +            printk("CPU#%d: NMI okay\n", cpu);
   5.101 +    }
   5.102 +
   5.103 +    /* now that we know it works we can reduce NMI frequency to
   5.104 +       something more reasonable; makes a difference in some configs */
   5.105 +    if (nmi_watchdog == NMI_LOCAL_APIC)
   5.106 +        nmi_hz = 1;
   5.107 +
   5.108 +    return 0;
   5.109 +}
   5.110 +
   5.111 +static inline void nmi_pm_init(void) { }
   5.112 +#define __pminit	__init
   5.113 +
   5.114 +/*
   5.115 + * Activate the NMI watchdog via the local APIC.
   5.116 + * Original code written by Keith Owens.
   5.117 + */
   5.118 +
   5.119 +static void __pminit clear_msr_range(unsigned int base, unsigned int n)
   5.120 +{
   5.121 +    unsigned int i;
   5.122 +
   5.123 +    for(i = 0; i < n; ++i)
   5.124 +        wrmsr(base+i, 0, 0);
   5.125 +}
   5.126 +
   5.127 +static void __pminit setup_k7_watchdog(void)
   5.128 +{
   5.129 +    unsigned int evntsel;
   5.130 +
   5.131 +    nmi_perfctr_msr = MSR_K7_PERFCTR0;
   5.132 +
   5.133 +    clear_msr_range(MSR_K7_EVNTSEL0, 4);
   5.134 +    clear_msr_range(MSR_K7_PERFCTR0, 4);
   5.135 +
   5.136 +    evntsel = K7_EVNTSEL_INT
   5.137 +        | K7_EVNTSEL_OS
   5.138 +        | K7_EVNTSEL_USR
   5.139 +        | K7_NMI_EVENT;
   5.140 +
   5.141 +    wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
   5.142 +    Dprintk("setting K7_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
   5.143 +    wrmsr(MSR_K7_PERFCTR0, -(cpu_khz/nmi_hz*1000), -1);
   5.144 +    apic_write(APIC_LVTPC, APIC_DM_NMI);
   5.145 +    evntsel |= K7_EVNTSEL_ENABLE;
   5.146 +    wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
   5.147 +}
   5.148 +
   5.149 +static void __pminit setup_p6_watchdog(void)
   5.150 +{
   5.151 +    unsigned int evntsel;
   5.152 +
   5.153 +    nmi_perfctr_msr = MSR_P6_PERFCTR0;
   5.154 +
   5.155 +    clear_msr_range(MSR_P6_EVNTSEL0, 2);
   5.156 +    clear_msr_range(MSR_P6_PERFCTR0, 2);
   5.157 +
   5.158 +    evntsel = P6_EVNTSEL_INT
   5.159 +        | P6_EVNTSEL_OS
   5.160 +        | P6_EVNTSEL_USR
   5.161 +        | P6_NMI_EVENT;
   5.162 +
   5.163 +    wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
   5.164 +    Dprintk("setting P6_PERFCTR0 to %08lx\n", -(cpu_khz/nmi_hz*1000));
   5.165 +    wrmsr(MSR_P6_PERFCTR0, -(cpu_khz/nmi_hz*1000), 0);
   5.166 +    apic_write(APIC_LVTPC, APIC_DM_NMI);
   5.167 +    evntsel |= P6_EVNTSEL0_ENABLE;
   5.168 +    wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
   5.169 +}
   5.170 +
   5.171 +static int __pminit setup_p4_watchdog(void)
   5.172 +{
   5.173 +    unsigned int misc_enable, dummy;
   5.174 +
   5.175 +    rdmsr(MSR_P4_MISC_ENABLE, misc_enable, dummy);
   5.176 +    if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
   5.177 +        return 0;
   5.178 +
   5.179 +    nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
   5.180 +
   5.181 +    if (!(misc_enable & MSR_P4_MISC_ENABLE_PEBS_UNAVAIL))
   5.182 +        clear_msr_range(0x3F1, 2);
   5.183 +    /* MSR 0x3F0 seems to have a default value of 0xFC00, but current
   5.184 +       docs doesn't fully define it, so leave it alone for now. */
   5.185 +    clear_msr_range(0x3A0, 31);
   5.186 +    clear_msr_range(0x3C0, 6);
   5.187 +    clear_msr_range(0x3C8, 6);
   5.188 +    clear_msr_range(0x3E0, 2);
   5.189 +    clear_msr_range(MSR_P4_CCCR0, 18);
   5.190 +    clear_msr_range(MSR_P4_PERFCTR0, 18);
   5.191 +
   5.192 +    wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
   5.193 +    wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
   5.194 +    Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000));
   5.195 +    wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1);
   5.196 +    apic_write(APIC_LVTPC, APIC_DM_NMI);
   5.197 +    wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0, 0);
   5.198 +    return 1;
   5.199 +}
   5.200 +
   5.201 +void __pminit setup_apic_nmi_watchdog (void)
   5.202 +{
   5.203 +    switch (boot_cpu_data.x86_vendor) {
   5.204 +    case X86_VENDOR_AMD:
   5.205 +        if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
   5.206 +            return;
   5.207 +        setup_k7_watchdog();
   5.208 +        break;
   5.209 +    case X86_VENDOR_INTEL:
   5.210 +        switch (boot_cpu_data.x86) {
   5.211 +        case 6:
   5.212 +            setup_p6_watchdog();
   5.213 +            break;
   5.214 +        case 15:
   5.215 +            if (!setup_p4_watchdog())
   5.216 +                return;
   5.217 +            break;
   5.218 +        default:
   5.219 +            return;
   5.220 +        }
   5.221 +        break;
   5.222 +    default:
   5.223 +        return;
   5.224 +    }
   5.225 +    nmi_pm_init();
   5.226 +}
   5.227 +
   5.228 +
   5.229 +static unsigned int
   5.230 +last_irq_sums [NR_CPUS],
   5.231 +    alert_counter [NR_CPUS];
   5.232 +
   5.233 +void touch_nmi_watchdog (void)
   5.234 +{
   5.235 +    int i;
   5.236 +    for (i = 0; i < smp_num_cpus; i++)
   5.237 +        alert_counter[i] = 0;
   5.238 +}
   5.239 +
   5.240 +void nmi_watchdog_tick (struct pt_regs * regs)
   5.241 +{
   5.242 +    extern spinlock_t console_lock;
   5.243 +    extern void die(const char * str, struct pt_regs * regs, long err);
   5.244 +    extern void putchar_serial(unsigned char c);
   5.245 +
   5.246 +    int sum, cpu = smp_processor_id();
   5.247 +
   5.248 +    sum = apic_timer_irqs[cpu];
   5.249 +    
   5.250 +    if (last_irq_sums[cpu] == sum) {
   5.251 +        /*
   5.252 +         * Ayiee, looks like this CPU is stuck ... wait a few IRQs (5 seconds) 
   5.253 +         * before doing the oops ...
   5.254 +         */
   5.255 +        alert_counter[cpu]++;
   5.256 +        if (alert_counter[cpu] == 5*nmi_hz) {
   5.257 +            console_lock = SPIN_LOCK_UNLOCKED;
   5.258 +            die("NMI Watchdog detected LOCKUP on CPU", regs, cpu);
   5.259 +        }
   5.260 +    } else {
   5.261 +        last_irq_sums[cpu] = sum;
   5.262 +        alert_counter[cpu] = 0;
   5.263 +    }
   5.264 +
   5.265 +    if (nmi_perfctr_msr) {
   5.266 +        if (nmi_perfctr_msr == MSR_P4_IQ_COUNTER0) {
   5.267 +            /*
   5.268 +             * P4 quirks: - An overflown perfctr will assert its interrupt
   5.269 +             *   until the OVF flag in its CCCR is cleared. - LVTPC is masked 
   5.270 +             * on interrupt and must be
   5.271 +             *   unmasked by the LVTPC handler.
   5.272 +             */
   5.273 +            wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0, 0);
   5.274 +            apic_write(APIC_LVTPC, APIC_DM_NMI);
   5.275 +        }
   5.276 +        wrmsr(nmi_perfctr_msr, -(cpu_khz/nmi_hz*1000), -1);
   5.277 +    }
   5.278 +}
     6.1 --- a/xen/arch/i386/setup.c	Mon Jul 14 14:33:54 2003 +0000
     6.2 +++ b/xen/arch/i386/setup.c	Mon Jul 14 15:45:01 2003 +0000
     6.3 @@ -148,7 +148,8 @@ void __init identify_cpu(struct cpuinfo_
     6.4              c->x86_capability[2] = cpuid_edx(0x80860001);
     6.5      }
     6.6  
     6.7 -    printk("CPU: Before vendor init, caps: %08x %08x %08x, vendor = %d\n",
     6.8 +    printk("CPU%d: Before vendor init, caps: %08x %08x %08x, vendor = %d\n",
     6.9 +           smp_processor_id(),
    6.10             c->x86_capability[0],
    6.11             c->x86_capability[1],
    6.12             c->x86_capability[2],
    6.13 @@ -345,13 +346,15 @@ void __init start_of_day(void)
    6.14  #endif
    6.15      initialize_keytable(); /* call back handling for key codes      */
    6.16  
    6.17 -	disable_pit();		/* not needed anymore */
    6.18 -	ac_timer_init();    /* init accurate timers */
    6.19 -	init_xeno_time();	/* initialise the time */
    6.20 -	schedulers_start(); /* start scheduler for each CPU */
    6.21 +    disable_pit();		/* not needed anymore */
    6.22 +    ac_timer_init();    /* init accurate timers */
    6.23 +    init_xeno_time();	/* initialise the time */
    6.24 +    schedulers_start(); /* start scheduler for each CPU */
    6.25  
    6.26      sti();
    6.27  
    6.28 +    check_nmi_watchdog();
    6.29 +
    6.30      zap_low_mappings();
    6.31      kmem_cache_init();
    6.32      kmem_cache_sizes_init(max_page);
    6.33 @@ -369,7 +372,6 @@ void __init start_of_day(void)
    6.34      net_init();            /* initializes virtual network system. */
    6.35      initialize_block_io(); /* setup block devices */
    6.36  
    6.37 -
    6.38  #ifdef CONFIG_SMP
    6.39      wait_init_idle = cpu_online_map;
    6.40      clear_bit(smp_processor_id(), &wait_init_idle);
     7.1 --- a/xen/arch/i386/traps.c	Mon Jul 14 14:33:54 2003 +0000
     7.2 +++ b/xen/arch/i386/traps.c	Mon Jul 14 15:45:01 2003 +0000
     7.3 @@ -470,7 +470,15 @@ asmlinkage void do_nmi(struct pt_regs * 
     7.4  {
     7.5      unsigned char reason = inb(0x61);
     7.6  
     7.7 +    ++nmi_count(smp_processor_id());
     7.8 +
     7.9      if (!(reason & 0xc0)) {
    7.10 +#if CONFIG_X86_LOCAL_APIC
    7.11 +        if (nmi_watchdog) {
    7.12 +            nmi_watchdog_tick(regs);
    7.13 +            return;
    7.14 +        }
    7.15 +#endif
    7.16          unknown_nmi_error(reason, regs);
    7.17          return;
    7.18      }
     8.1 --- a/xen/include/asm-i386/hardirq.h	Mon Jul 14 14:33:54 2003 +0000
     8.2 +++ b/xen/include/asm-i386/hardirq.h	Mon Jul 14 15:45:01 2003 +0000
     8.3 @@ -10,6 +10,7 @@ typedef struct {
     8.4  	unsigned int __local_irq_count;
     8.5  	unsigned int __local_bh_count;
     8.6  	unsigned int __syscall_count;
     8.7 +	unsigned int __nmi_count;
     8.8  	unsigned long idle_timestamp;
     8.9  } ____cacheline_aligned irq_cpustat_t;
    8.10  
     9.1 --- a/xen/include/asm-i386/msr.h	Mon Jul 14 14:33:54 2003 +0000
     9.2 +++ b/xen/include/asm-i386/msr.h	Mon Jul 14 15:45:01 2003 +0000
     9.3 @@ -48,17 +48,16 @@
     9.4  #define MSR_IA32_UCODE_WRITE		0x79
     9.5  #define MSR_IA32_UCODE_REV		0x8b
     9.6  
     9.7 -#define MSR_IA32_PERFCTR0		0xc1
     9.8 -#define MSR_IA32_PERFCTR1		0xc2
     9.9 -
    9.10  #define MSR_IA32_BBL_CR_CTL		0x119
    9.11  
    9.12  #define MSR_IA32_MCG_CAP		0x179
    9.13  #define MSR_IA32_MCG_STATUS		0x17a
    9.14  #define MSR_IA32_MCG_CTL		0x17b
    9.15  
    9.16 -#define MSR_IA32_EVNTSEL0		0x186
    9.17 -#define MSR_IA32_EVNTSEL1		0x187
    9.18 +#define MSR_IA32_THERM_CONTROL		0x19a
    9.19 +#define MSR_IA32_THERM_INTERRUPT	0x19b
    9.20 +#define MSR_IA32_THERM_STATUS		0x19c
    9.21 +#define MSR_IA32_MISC_ENABLE		0x1a0
    9.22  
    9.23  #define MSR_IA32_DEBUGCTLMSR		0x1d9
    9.24  #define MSR_IA32_LASTBRANCHFROMIP	0x1db
    9.25 @@ -71,16 +70,26 @@
    9.26  #define MSR_IA32_MC0_ADDR		0x402
    9.27  #define MSR_IA32_MC0_MISC		0x403
    9.28  
    9.29 +#define MSR_P6_PERFCTR0			0xc1
    9.30 +#define MSR_P6_PERFCTR1			0xc2
    9.31 +#define MSR_P6_EVNTSEL0			0x186
    9.32 +#define MSR_P6_EVNTSEL1			0x187
    9.33 +
    9.34  /* AMD Defined MSRs */
    9.35  #define MSR_K6_EFER			0xC0000080
    9.36  #define MSR_K6_STAR			0xC0000081
    9.37  #define MSR_K6_WHCR			0xC0000082
    9.38  #define MSR_K6_UWCCR			0xC0000085
    9.39 +#define MSR_K6_EPMR			0xC0000086
    9.40  #define MSR_K6_PSOR			0xC0000087
    9.41  #define MSR_K6_PFIR			0xC0000088
    9.42  
    9.43  #define MSR_K7_EVNTSEL0			0xC0010000
    9.44  #define MSR_K7_PERFCTR0			0xC0010004
    9.45 +#define MSR_K7_HWCR			0xC0010015
    9.46 +#define MSR_K7_CLK_CTL			0xC001001b
    9.47 +#define MSR_K7_FID_VID_CTL		0xC0010041
    9.48 +#define MSR_K7_VID_STATUS		0xC0010042
    9.49  
    9.50  /* Centaur-Hauls/IDT defined MSRs. */
    9.51  #define MSR_IDT_FCR1			0x107
    9.52 @@ -100,5 +109,13 @@
    9.53  
    9.54  /* VIA Cyrix defined MSRs*/
    9.55  #define MSR_VIA_FCR			0x1107
    9.56 +#define MSR_VIA_LONGHAUL		0x110a
    9.57 +#define MSR_VIA_BCR2			0x1147
    9.58 +
    9.59 +/* Transmeta defined MSRs */
    9.60 +#define MSR_TMTA_LONGRUN_CTRL		0x80868010
    9.61 +#define MSR_TMTA_LONGRUN_FLAGS		0x80868011
    9.62 +#define MSR_TMTA_LRTI_READOUT		0x80868018
    9.63 +#define MSR_TMTA_LRTI_VOLT_MHZ		0x8086801a
    9.64  
    9.65  #endif /* __ASM_MSR_H */
    10.1 --- a/xen/include/xeno/irq_cpustat.h	Mon Jul 14 14:33:54 2003 +0000
    10.2 +++ b/xen/include/xeno/irq_cpustat.h	Mon Jul 14 15:45:01 2003 +0000
    10.3 @@ -30,5 +30,6 @@ extern irq_cpustat_t irq_stat[];			/* de
    10.4  #define local_irq_count(cpu)	__IRQ_STAT((cpu), __local_irq_count)
    10.5  #define local_bh_count(cpu)	__IRQ_STAT((cpu), __local_bh_count)
    10.6  #define syscall_count(cpu)	__IRQ_STAT((cpu), __syscall_count)
    10.7 +#define nmi_count(cpu)		__IRQ_STAT((cpu), __nmi_count)
    10.8  
    10.9  #endif	/* __irq_cpustat_h */