debuggers.hg

changeset 21940:c9e7850ec9a1

x86: unmask CPUID levels on Intel CPUs

If the CPUID limit bit in MSR_IA32_MISC_ENABLE is set, clear it to
make all CPUID information available. This is required for some
features to work, such as MWAIT in cpuidle, get cpu topology, XSAVE,
etc.

Signed-off-by: Wei Gang <gang.wei@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jul 30 11:36:34 2010 +0100 (2010-07-30)
parents 754877be695b
children de62cfdd7b9f
files xen/arch/x86/cpu/intel.c xen/include/asm-x86/msr-index.h
line diff
     1.1 --- a/xen/arch/x86/cpu/intel.c	Thu Jul 29 18:58:19 2010 +0100
     1.2 +++ b/xen/arch/x86/cpu/intel.c	Fri Jul 30 11:36:34 2010 +0100
     1.3 @@ -90,6 +90,20 @@ void __devinit early_intel_workaround(st
     1.4  	/* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
     1.5  	if (c->x86 == 15 && c->x86_cache_alignment == 64)
     1.6  		c->x86_cache_alignment = 128;
     1.7 +
     1.8 +	/* Unmask CPUID levels if masked: */
     1.9 +	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
    1.10 +		u64 misc_enable;
    1.11 +
    1.12 +		rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
    1.13 +
    1.14 +		if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
    1.15 +			misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
    1.16 +			wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
    1.17 +			c->cpuid_level = cpuid_eax(0);
    1.18 +			printk("revised cpuid_level = %d\n", c->cpuid_level);
    1.19 +		}
    1.20 +	}
    1.21  }
    1.22  
    1.23  /*
     2.1 --- a/xen/include/asm-x86/msr-index.h	Thu Jul 29 18:58:19 2010 +0100
     2.2 +++ b/xen/include/asm-x86/msr-index.h	Fri Jul 30 11:36:34 2010 +0100
     2.3 @@ -324,6 +324,7 @@
     2.4  #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL  (1<<11)
     2.5  #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
     2.6  #define MSR_IA32_MISC_ENABLE_MONITOR_ENABLE (1<<18)
     2.7 +#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID  (1<<22)
     2.8  #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23)
     2.9  
    2.10  /* Intel Model 6 */