gdunlap/sched-sim.hg
annotate workloads.c @ 1:ec2d50e41437
Handle multiple cpus.
author | George Dunlap <gdunlap@xensource.com> |
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date | Tue Oct 13 17:29:50 2009 +0100 (2009-10-13) |
parents | d27bb3c56e71 |
children | 1d7310217c5a |
rev | line source |
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gdunlap@0 | 1 #include "workload.h" |
gdunlap@0 | 2 |
gdunlap@0 | 3 const int default_workload = 0; |
gdunlap@0 | 4 struct workload builtin_workloads[] = |
gdunlap@0 | 5 { |
gdunlap@0 | 6 { |
gdunlap@1 | 7 .name="r1", |
gdunlap@1 | 8 .vm_count=3, |
gdunlap@1 | 9 .vm_workloads = { |
gdunlap@1 | 10 { .phase_count = 2, |
gdunlap@1 | 11 .list = { |
gdunlap@1 | 12 { |
gdunlap@1 | 13 .type=PHASE_RUN, |
gdunlap@1 | 14 .time=70 |
gdunlap@1 | 15 }, |
gdunlap@1 | 16 { |
gdunlap@1 | 17 .type=PHASE_BLOCK, |
gdunlap@1 | 18 .time=250 |
gdunlap@1 | 19 }, |
gdunlap@1 | 20 } |
gdunlap@1 | 21 }, |
gdunlap@1 | 22 { .phase_count = 2, |
gdunlap@1 | 23 .list = { |
gdunlap@1 | 24 { |
gdunlap@1 | 25 .type=PHASE_RUN, |
gdunlap@1 | 26 .time=500 |
gdunlap@1 | 27 }, |
gdunlap@1 | 28 { |
gdunlap@1 | 29 .type=PHASE_BLOCK, |
gdunlap@1 | 30 .time=500 |
gdunlap@1 | 31 }, |
gdunlap@1 | 32 } |
gdunlap@1 | 33 }, |
gdunlap@1 | 34 { .phase_count = 2, |
gdunlap@1 | 35 .list = { |
gdunlap@1 | 36 { |
gdunlap@1 | 37 .type=PHASE_RUN, |
gdunlap@1 | 38 .time=1295 |
gdunlap@1 | 39 }, |
gdunlap@1 | 40 { |
gdunlap@1 | 41 .type=PHASE_BLOCK, |
gdunlap@1 | 42 .time=5 |
gdunlap@1 | 43 }, |
gdunlap@1 | 44 } |
gdunlap@1 | 45 }, |
gdunlap@1 | 46 } |
gdunlap@1 | 47 }, |
gdunlap@1 | 48 { |
gdunlap@0 | 49 .name="Sx3", |
gdunlap@0 | 50 .vm_count=3, |
gdunlap@0 | 51 .vm_workloads = { |
gdunlap@0 | 52 { .phase_count = 2, |
gdunlap@0 | 53 .list = { |
gdunlap@0 | 54 { |
gdunlap@0 | 55 .type=PHASE_RUN, |
gdunlap@0 | 56 .time=695 |
gdunlap@0 | 57 }, |
gdunlap@0 | 58 { |
gdunlap@0 | 59 .type=PHASE_BLOCK, |
gdunlap@0 | 60 .time=5 |
gdunlap@0 | 61 }, |
gdunlap@0 | 62 } |
gdunlap@0 | 63 }, |
gdunlap@0 | 64 { .phase_count = 2, |
gdunlap@0 | 65 .list = { |
gdunlap@0 | 66 { |
gdunlap@0 | 67 .type=PHASE_RUN, |
gdunlap@0 | 68 .time=1095 |
gdunlap@0 | 69 }, |
gdunlap@0 | 70 { |
gdunlap@0 | 71 .type=PHASE_BLOCK, |
gdunlap@0 | 72 .time=5 |
gdunlap@0 | 73 }, |
gdunlap@0 | 74 } |
gdunlap@0 | 75 }, |
gdunlap@0 | 76 { .phase_count = 2, |
gdunlap@0 | 77 .list = { |
gdunlap@0 | 78 { |
gdunlap@0 | 79 .type=PHASE_RUN, |
gdunlap@0 | 80 .time=1295 |
gdunlap@0 | 81 }, |
gdunlap@0 | 82 { |
gdunlap@0 | 83 .type=PHASE_BLOCK, |
gdunlap@0 | 84 .time=5 |
gdunlap@0 | 85 }, |
gdunlap@0 | 86 } |
gdunlap@0 | 87 }, |
gdunlap@0 | 88 } |
gdunlap@0 | 89 }, |
gdunlap@0 | 90 }; |