xcp-1.6-updates/xen-4.1.hg

changeset 23239:04e5091cc08f

x86, amd: Disable GartTlbWlkErr when BIOS forgets it

This patch disables GartTlbWlk errors on AMD Fam10h CPUs if the BIOS
forgets to do is (or is just too old). Letting these errors enabled
can cause a sync-flood on the CPU causing a reboot.

The AMD BKDG recommends disabling GART TLB Wlk Error completely.

Based on a Linux patch from Joerg Roedel <joerg.roedel@amd.com>; see
e.g.
https://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=patch;h=5bbc097d890409d8eff4e3f1d26f11a9d6b7c07e

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Keir Fraser <keir@xen.org>
xen-unstable changeset: 24389:868d82faf651
xen-unstable date: Tue Dec 13 09:45:11 2011 +0100
author Jan Beulich <jbeulich@suse.com>
date Wed Mar 07 08:16:53 2012 +0000 (2012-03-07)
parents 95f48f40299f
children 0bea45ab39f7
files xen/arch/x86/cpu/mcheck/amd_f10.c xen/arch/x86/cpu/mcheck/mce_amd_quirks.c xen/arch/x86/cpu/mcheck/mce_quirks.h xen/include/asm-x86/msr-index.h
line diff
     1.1 --- a/xen/arch/x86/cpu/mcheck/amd_f10.c	Wed Mar 07 08:15:50 2012 +0000
     1.2 +++ b/xen/arch/x86/cpu/mcheck/amd_f10.c	Wed Mar 07 08:16:53 2012 +0000
     1.3 @@ -46,6 +46,7 @@
     1.4  #include <asm/msr.h>
     1.5  
     1.6  #include "mce.h"
     1.7 +#include "mce_quirks.h"
     1.8  #include "x86_mca.h"
     1.9  
    1.10  
    1.11 @@ -91,9 +92,14 @@ amd_f10_handler(struct mc_info *mi, uint
    1.12  /* AMD Family10 machine check */
    1.13  enum mcheck_type amd_f10_mcheck_init(struct cpuinfo_x86 *c)
    1.14  { 
    1.15 +	enum mcequirk_amd_flags quirkflag = mcequirk_lookup_amd_quirkdata(c);
    1.16 +
    1.17  	if (amd_k8_mcheck_init(c) == mcheck_none)
    1.18  		return mcheck_none;
    1.19  
    1.20 +	if (quirkflag == MCEQUIRK_F10_GART)
    1.21 +		mcequirk_amd_apply(quirkflag);
    1.22 +
    1.23  	x86_mce_callback_register(amd_f10_handler);
    1.24  
    1.25  	return mcheck_amd_famXX;
     2.1 --- a/xen/arch/x86/cpu/mcheck/mce_amd_quirks.c	Wed Mar 07 08:15:50 2012 +0000
     2.2 +++ b/xen/arch/x86/cpu/mcheck/mce_amd_quirks.c	Wed Mar 07 08:16:53 2012 +0000
     2.3 @@ -29,6 +29,8 @@ static const struct mce_quirkdata mce_am
     2.4  	  MCEQUIRK_K7_BANK0 },
     2.5  	{ 0xf /* cpu family */, ANY /* all models */, ANY /* all steppings */,
     2.6  	  MCEQUIRK_K8_GART },
     2.7 +	{ 0x10 /* cpu family */, ANY /* all models */, ANY /* all steppings */,
     2.8 +	  MCEQUIRK_F10_GART },
     2.9  };
    2.10  
    2.11  enum mcequirk_amd_flags
    2.12 @@ -54,6 +56,8 @@ mcequirk_lookup_amd_quirkdata(struct cpu
    2.13  
    2.14  int mcequirk_amd_apply(enum mcequirk_amd_flags flags)
    2.15  {
    2.16 +	u64 val;
    2.17 +
    2.18  	switch (flags) {
    2.19  	case MCEQUIRK_K7_BANK0:
    2.20  		return 1; /* first bank */
    2.21 @@ -67,6 +71,10 @@ int mcequirk_amd_apply(enum mcequirk_amd
    2.22  		wrmsrl(MSR_IA32_MC4_CTL, ~(1ULL << 10));
    2.23  		wrmsrl(MSR_IA32_MC4_STATUS, 0ULL);
    2.24  		break;
    2.25 +	case MCEQUIRK_F10_GART:
    2.26 +		if (rdmsr_safe(MSR_AMD64_MCx_MASK(4), val) == 0)
    2.27 +			wrmsr_safe(MSR_AMD64_MCx_MASK(4), val | (1 << 10));
    2.28 +		break;
    2.29  	}
    2.30  
    2.31  	return 0;
     3.1 --- a/xen/arch/x86/cpu/mcheck/mce_quirks.h	Wed Mar 07 08:15:50 2012 +0000
     3.2 +++ b/xen/arch/x86/cpu/mcheck/mce_quirks.h	Wed Mar 07 08:16:53 2012 +0000
     3.3 @@ -33,8 +33,9 @@ struct mce_quirkdata {
     3.4   */
     3.5  
     3.6  enum mcequirk_amd_flags {
     3.7 -	MCEQUIRK_K7_BANK0 = 0x1,
     3.8 -	MCEQUIRK_K8_GART = 0x2,
     3.9 +	MCEQUIRK_K7_BANK0 = 1,
    3.10 +	MCEQUIRK_K8_GART,
    3.11 +	MCEQUIRK_F10_GART
    3.12  };
    3.13  
    3.14  enum mcequirk_intel_flags {
     4.1 --- a/xen/include/asm-x86/msr-index.h	Wed Mar 07 08:15:50 2012 +0000
     4.2 +++ b/xen/include/asm-x86/msr-index.h	Wed Mar 07 08:16:53 2012 +0000
     4.3 @@ -98,6 +98,8 @@
     4.4  #define CMCI_EN 			(1UL<<30)
     4.5  #define CMCI_THRESHOLD_MASK		0x7FFF
     4.6  
     4.7 +#define MSR_AMD64_MC0_MASK		0xc0010044
     4.8 +
     4.9  #define MSR_IA32_MC1_CTL		0x00000404
    4.10  #define MSR_IA32_MC1_CTL2		0x00000281
    4.11  #define MSR_IA32_MC1_STATUS		0x00000405
    4.12 @@ -151,6 +153,8 @@
    4.13  #define MSR_IA32_MCx_ADDR(x)		(MSR_IA32_MC0_ADDR + 4*(x))
    4.14  #define MSR_IA32_MCx_MISC(x)		(MSR_IA32_MC0_MISC + 4*(x)) 
    4.15  
    4.16 +#define MSR_AMD64_MCx_MASK(x)		(MSR_AMD64_MC0_MASK + (x))
    4.17 +
    4.18  #define MSR_P6_PERFCTR0			0x000000c1
    4.19  #define MSR_P6_PERFCTR1			0x000000c2
    4.20  #define MSR_P6_EVNTSEL0			0x00000186