xcp-1.6-updates/xen-4.1.hg

changeset 23287:a21938b58fc4

svm: Fake out the Bus Unit Config MSR on revF AMD CPUs

Win2k8 x64 reads this MSR on revF chips, where it wasn't publically
available; it uses a magic constant in %rdi as a password, which we
don't have in rdmsr_safe(). Since we'll ignore the later writes, just
use a plausible value here (the reset value from rev10h chips) if the
real CPU didn't provide one.

Signed-off-by: George Dunlap <george.dunlap@eu.citrix.com>
Committed-by: Keir Fraser <keir@xen.org>
xen-unstable changeset: 24990:322300fd2ebd
xen-unstable date: Thu Mar 08 09:17:21 2012 +0000

svm: amend c/s 24990:322300fd2ebd (fake BU_CFG MSR on AMD revF)

Let's restrict such a hack to the known affected family.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Keir Fraser <keir@xen.org>
Acked-by: George Dunlap <george.dunlap@eu.citrix.com>
xen-unstable changeset: 25058:f47d91cb0faa
xen-unstable date: Thu Mar 15 15:09:18 2012 +0100
author George Dunlap <george.dunlap@eu.citrix.com>
date Tue May 01 14:15:20 2012 +0100 (2012-05-01)
parents b1e2ca715ae7
children da64f68730cf
files xen/arch/x86/hvm/svm/svm.c xen/include/asm-x86/msr-index.h
line diff
     1.1 --- a/xen/arch/x86/hvm/svm/svm.c	Tue May 01 14:13:58 2012 +0100
     1.2 +++ b/xen/arch/x86/hvm/svm/svm.c	Tue May 01 14:15:20 2012 +0100
     1.3 @@ -1197,6 +1197,18 @@ static int svm_msr_read_intercept(unsign
     1.4          if ( rdmsr_safe(msr, *msr_content) == 0 )
     1.5              break;
     1.6  
     1.7 +        if ( boot_cpu_data.x86 == 0xf && msr == MSR_F10_BU_CFG )
     1.8 +        {
     1.9 +            /* Win2k8 x64 reads this MSR on revF chips, where it
    1.10 +             * wasn't publically available; it uses a magic constant
    1.11 +             * in %rdi as a password, which we don't have in
    1.12 +             * rdmsr_safe().  Since we'll ignore the later writes,
    1.13 +             * just use a plausible value here (the reset value from
    1.14 +             * rev10h chips) if the real CPU didn't provide one. */
    1.15 +            *msr_content = 0x0000000010200020ull;
    1.16 +            break;
    1.17 +        }
    1.18 +
    1.19          goto gpf;
    1.20      }
    1.21  
     2.1 --- a/xen/include/asm-x86/msr-index.h	Tue May 01 14:13:58 2012 +0100
     2.2 +++ b/xen/include/asm-x86/msr-index.h	Tue May 01 14:15:20 2012 +0100
     2.3 @@ -253,6 +253,9 @@
     2.4  #define MSR_F10_MC4_MISC2		0xc0000409
     2.5  #define MSR_F10_MC4_MISC3		0xc000040A
     2.6  
     2.7 +/* AMD Family10h MMU control MSRs */
     2.8 +#define MSR_F10_BU_CFG                  0xc0011023
     2.9 +
    2.10  /* Other AMD Fam10h MSRs */
    2.11  #define MSR_FAM10H_MMIO_CONF_BASE	0xc0010058
    2.12  #define FAM10H_MMIO_CONF_ENABLE         (1<<0)