x86/vIRQ: IRR and TMR race condition bug fix

In vlapic_set_irq, we set the IRR register before the TMR. And the IRR
might be serviced before setting TMR, and even worse EOI might occur
before TMR setting, in which case the vioapic_update_EOI won't be
called, and further prevent all the subsequent interrupt injecting.
Reorder setting the TMR and IRR will solve the problem.

Besides, KVM has fixed a similar bug in:
http://markmail.org/search/?q=APIC_TMR#query:APIC_TMR+page:1+mid:rphs4f7lkxjlldne+state:results

Signed-off-by: Yongan Liu<Liuyongan@huawei.com>
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Committed-by: Jan Beulich <jbeulich@suse.com>
xen-unstable changeset: 24453:02b92d035f64
xen-unstable date: Thu Jan 05 09:29:59 2012 +0100

     1.1 --- a/xen/arch/x86/hvm/vlapic.c	Tue Jan 17 11:30:37 2012 +0000
     1.2 +++ b/xen/arch/x86/hvm/vlapic.c	Tue Jan 17 11:31:28 2012 +0000
     1.3 @@ -142,14 +142,11 @@ static int vlapic_find_highest_irr(struc
     1.4  
     1.5  int vlapic_set_irq(struct vlapic *vlapic, uint8_t vec, uint8_t trig)
     1.6  {
     1.7 -    int ret;
     1.8 -
     1.9 -    ret = !vlapic_test_and_set_irr(vec, vlapic);
    1.10      if ( trig )
    1.11          vlapic_set_vector(vec, &vlapic->regs->data[APIC_TMR]);
    1.12  
    1.13      /* We may need to wake up target vcpu, besides set pending bit here */
    1.14 -    return ret;
    1.15 +    return !vlapic_test_and_set_irr(vec, vlapic);
    1.16  }
    1.17  
    1.18  static int vlapic_find_highest_isr(struct vlapic *vlapic)